media: i2c: nvp6324 drivers synchronize with kernel 4.4

kernel 4.4 commit ends 9784ddae3834e1d2a27a55abfadeed635f6bd008

Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: If7d53e4c6667c09a8db90dca571599f12a2088ce

drivers/media/i2c/Kconfig

@@ -1669,6 +1669,15 @@ config VIDEO_I2C
 	  To compile this driver as a module, choose M here: the
 	  module will be called video-i2c
 
+config VIDEO_NVP6324
+	tristate "NEXTCHIP nvp6324 driver support"
+	depends on VIDEO_V4L2 && I2C
+	---help---
+	  Support for the NVP6324.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called jaguar1_drv.
+
 config VIDEO_HALL_DC_MOTOR
 	tristate "Hall dc-motor driver for camera iris"
 	depends on PWM && VIDEO_V4L2

drivers/media/i2c/Makefile

@@ -7,6 +7,7 @@ obj-$(CONFIG_VIDEO_ET8EK8)	+= et8ek8/
 obj-$(CONFIG_VIDEO_CX25840) += cx25840/
 obj-$(CONFIG_VIDEO_M5MOLS)	+= m5mols/
 obj-y				+= soc_camera/
+obj-$(CONFIG_VIDEO_NVP6324)	+= jaguar1_drv/
 
 obj-$(CONFIG_VIDEO_APTINA_PLL) += aptina-pll.o
 obj-$(CONFIG_VIDEO_TVAUDIO) += tvaudio.o

drivers/media/i2c/jaguar1_drv/Makefile

@@ -0,0 +1,5 @@
+subdir-ccflags-y += -DNC_DEBUG
+obj-y := jaguar1_drv.o jaguar1_i2c.o \
+	 jaguar1_video.o jaguar1_coax_protocol.o \
+	 jaguar1_motion.o jaguar1_video_eq.o \
+	 jaguar1_mipi.o  jaguar1_v4l2.o

drivers/media/i2c/jaguar1_drv/jaguar1_coax_protocol.h

@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/********************************************************************************
+ *
+ *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
+ *  Module		: Jaguar1 Device Driver
+ *  Description	: coax_protocol.h
+ *  Author		:
+ *  Date         :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History      :
+ *
+ *
+ ********************************************************************************/
+#ifndef _JAGUAR1_COAX_PROTOCOL_
+#define _JAGUAR1_COAX_PROTOCOL_
+
+#include "jaguar1_common.h"
+
+#define BANK1 0x01
+#define BANK2 0x02
+#define BANK3 0x03
+#define BANKC 0x0C
+
+#define FW_SUCCESS 0
+#define FW_FAILURE -1
+
+#define DBG_TX_INIT_PRINT 0
+#define DBG_TX_CMD_PRINT 0
+#define DBG_RX_INIT_PRINT 0
+
+/* ACP command status */
+#define ACP_CAM_STAT			0x55
+#define ACP_REG_WR				0x60
+#define ACP_REG_RD				0x61
+#define ACP_MODE_ID				0x60
+
+typedef enum NC_COAX_CMD_DEF
+{
+	COAX_CMD_UNKNOWN = 0,
+	COAX_CMD_IRIS_INC,
+	COAX_CMD_IRIS_DEC,
+	COAX_CMD_FOCUS_INC,
+	COAX_CMD_FOCUS_DEC,
+	COAX_CMD_ZOOM_INC,
+	COAX_CMD_ZOOM_DEC,
+	COAX_CMD_OSD_ON,
+	COAX_CMD_PTZ_UP,
+	COAX_CMD_PTZ_DOWN,
+	COAX_CMD_PTZ_LEFT,
+	COAX_CMD_PTZ_RIGHT,
+	COAX_CMD_OSD_ENTER,
+	COAX_CMD_SPECIAL_FW,
+	COAX_CMD_SPECIAL_CAMEQ,
+	COAX_CMD_SPECIAL_FPS,
+	COAX_CMD_SPECIAL_MOTION,
+	COAX_CMD_TVI_DOWNSTREAM_REQUEST,
+
+	COAX_CMD_MAX,
+
+} NC_COAX_CMD_DEF;
+
+typedef struct _nc_acp_rw_data_
+{
+	unsigned char opt;
+    unsigned char ch;
+	unsigned int addr;
+	unsigned char data;
+}nc_acp_rw_data;
+
+
+/*=============================================================
+ * Coaxial Test Structure[APP <-> DRV]
+ ==============================================================*/
+typedef struct NC_VD_COAX_TEST_STR{
+	unsigned char ch;
+	unsigned char chip_num;
+	unsigned char bank;
+	unsigned char data_addr;
+	unsigned char param;
+
+	unsigned char rx_src;             //B5/6/7/8 0x7C
+	unsigned char rx_slice_lev;       //B5/6/7/8 0x7D
+	unsigned char tx_baud;            //B3/4 0x00/80
+	unsigned char tx_pel_baud;        //B3/4 0x02/82
+	unsigned char tx_line_pos0;       //B3/4 0x03/83
+	unsigned char tx_line_pos1;       //B3/4 0x04/84
+	unsigned char tx_pel_line_pos0;   //B3/4 0x07/87
+	unsigned char tx_pel_line_pos1;   //B3/4 0x08/88
+	unsigned char tx_line_count;      //B3/4 0x05/85
+	unsigned char tx_line_count_max;  //B3/4 0x0A/8A
+	unsigned char tx_mode;            //B3/4 0x0B/8B
+	unsigned char tx_sync_pos0;       //B3/4 0x0D/8D
+	unsigned char tx_sync_pos1;       //B3/4 0x0E/8E
+	unsigned char tx_even;            //B3/4 0x2F/AF
+	unsigned char tx_zero_length;     //B3/4 0x0C/
+}NC_VD_COAX_TEST_STR;
+
+typedef struct NC_VD_COAX_BANK_DUMP_STR{
+	unsigned char ch;
+	unsigned char vd_dev;
+	unsigned char bank;
+
+	unsigned char rx_pelco_data[256];
+
+}NC_VD_COAX_BANK_DUMP_STR;
+
+/*=============================================================
+ * Coaxial UP/Down Stream Initialize Structure[APP -> DRV]
+ ==============================================================*/
+typedef struct NC_VD_COAX_STR{
+	char *name;
+	unsigned char ch;
+	unsigned char vd_dev;
+	unsigned char param;
+	NC_FORMAT_STANDARD format_standard;
+	NC_FORMAT_RESOLUTION format_resolution;
+	NC_FORMAT_FPS format_fps;
+	NC_VIVO_CH_FORMATDEF vivo_fmt;
+	NC_COAX_CMD_DEF cmd;
+
+	unsigned char rx_pelco_data[8];
+	unsigned char rx_data1[8];
+	unsigned char rx_data2[8];
+	unsigned char rx_data3[8];
+	unsigned char rx_data4[8];
+	unsigned char rx_data5[8];
+	unsigned char rx_data6[8];
+
+}NC_VD_COAX_STR;
+
+/*=============================================================
+ * COAX FW Upgrade
+ ==============================================================*/
+typedef struct __file_information
+{
+	unsigned int	channel;                // FirmUP Channel
+	unsigned int	cp_mode;                // Channel Format
+	unsigned char 	filename[64];           //
+	unsigned char 	filePullname[64+32];    // FirmUP FileNmae
+	unsigned int	filesize;
+	unsigned int	filechecksum;			// (sum of file&0x0000FFFFF)
+	unsigned int	currentpacketnum;		// current packet sequnce number(0,1,2........)
+	unsigned int	filepacketnum;			// file packet number = (total size/128bytes), if remain exist, file packet number++
+	unsigned char 	onepacketbuf[128+32];
+
+	unsigned int	currentFileOffset;		// Current file offset
+	unsigned int	readsize;				// currnet read size
+
+	unsigned int receive_addr;
+
+	unsigned int	ispossiblefirmup[16]; 	// is it possible to update firmware?
+	int 			result;
+
+	int				appstatus[16];			// Application status
+
+} FIRMWARE_UP_FILE_INFO, *PFIRMWARE_UP_FILE_INFO;
+
+// Coaxial UP Stream Function
+void coax_tx_init( void *p_param );     // Coax Tx : Initialize
+void coax_tx_cmd_send( void *p_param ); // Coax Tx : Command Send
+
+void coax_tx_16bit_init( void *p_param );
+void coax_tx_16bit_cmd_send( void *p_param );
+void coax_tx_cvi_new_cmd_send( void *p_param );
+
+// Coaxial Down Stream Function
+void coax_rx_init( void *p_param );          // Coax Rx : Initialize
+void coax_rx_data_get( void *p_param );      // Coax Rx : All Rx Buffer read
+void coax_rx_buffer_clear( void *p_param );  // Coax Rx : Rx Buffer Clear
+void coax_rx_deinit( void *p_param );        // Coax Rx : 3x63 Set[ 1 -> 0 ]
+void coax_acp_rx_detect_get( void *p_param );
+
+// Coaxial FW Update Function
+void coax_fw_ready_header_check_from_isp_recv(void *p_param);
+void coax_fw_ready_cmd_to_isp_send(void *p_param);                // 1.1 FW Update Ready Command Send
+void coax_fw_ready_cmd_ack_from_isp_recv(void *p_param);          // 1.2 FW Update Ready ACK
+void coax_fw_start_cmd_to_isp_send( void *p_param );              // 2.1 FW Update Start Command Send
+void coax_fw_start_cmd_ack_from_isp_recv( void *p_param );        // 2.2 FW Update Start ACK
+void coax_fw_one_packet_data_to_isp_send( void *p_param );        // 3.1 FW Update One Packet Data Send
+void coax_fw_one_packet_data_ack_from_isp_recv( void *p_param );  // 3.2 FW Update One Packet Data ACK
+void coax_fw_end_cmd_to_isp_send( void *p_param );                // 4.1 FW Update End Command Send
+void coax_fw_end_cmd_ack_from_isp_recv( void *p_param );          // 4.2 FW Update End ACK
+void coax_fw_revert_to_previous_fmt_set(void *p_param);
+
+// Coaxial Option
+void coax_option_rt_nrt_mode_change_set(void *p_param);    // RT, NRT Mode change
+
+// Coaxial Test Function
+void coax_test_tx_init_read(NC_VD_COAX_TEST_STR *coax_tx_mode);    // Coax Test : Tx Init Read
+void coax_test_data_set(NC_VD_COAX_TEST_STR *coax_data);           // Coax Test : 1byte Data write
+void coax_test_data_get(NC_VD_COAX_TEST_STR *coax_data);           // Coax Test : 1byte Data read
+void coax_test_Bank_dump_get(NC_VD_COAX_BANK_DUMP_STR *coax_data); // Bank Dump
+void acp_isp_write(unsigned char ch, unsigned int reg_addr, unsigned char reg_data);
+unsigned char acp_isp_read(unsigned char ch, unsigned int reg_addr);
+
+#endif
+/********************************************************************
+ *  End of file
+ ********************************************************************/

drivers/media/i2c/jaguar1_drv/jaguar1_common.h

@@ -0,0 +1,454 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/********************************************************************************
+ *
+ *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
+ *  Module		: Jaguar1 Device Driver
+ *  Description	: common.h
+ *  Author		:
+ *  Date         :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History      :
+ *
+ *
+ ********************************************************************************/
+#ifndef __COMMON_H__
+#define __COMMON_H__
+
+unsigned char jaguar1_I2CReadByte8(unsigned char devaddress, unsigned char address);
+void jaguar1_I2CWriteByte8(unsigned char devaddress, unsigned char address, unsigned char data);
+#define  gpio_i2c_read    jaguar1_I2CReadByte8
+#define  gpio_i2c_write   jaguar1_I2CWriteByte8
+
+#define DRIVER_VER "1.1.7"
+
+#define JAGUAR1_MAX_CHAN_CNT 4
+
+extern unsigned int jaguar1_i2c_addr[4];
+
+#define HI_CHIPID_BASE 0x12050000
+#define HI_CHIPID0 IO_ADDRESS(HI_CHIPID_BASE + 0xEEC)
+#define HI_CHIPID1 IO_ADDRESS(HI_CHIPID_BASE + 0xEE8)
+#define HI_CHIPID2 IO_ADDRESS(HI_CHIPID_BASE + 0xEE4)
+#define HI_CHIPID3 IO_ADDRESS(HI_CHIPID_BASE + 0xEE0)
+#define HW_REG(reg) *((volatile unsigned int *)(reg))
+
+#define _SET_BIT(data,bit) ((data)|=(1<<(bit)))
+#define _CLE_BIT(data,bit) ((data)&=(~(1<<(bit))))
+
+#define JAGUAR1_BANK_CHANGE(bank) gpio_i2c_write(jaguar1_i2c_addr[0], 0xFF, bank );
+
+#define PORTA		0x00
+#define PORTB		0x01
+#define PORTC		0x02
+#define PORTD		0x03
+#define PORTAB		0x04
+#define PORTCD		0x05
+
+#define FUNC_ON		0x01
+#define FUNC_OFF	0x00
+
+#define BANK_0  0x00
+#define BANK_1  0x01
+#define BANK_2  0x02
+#define BANK_3  0x03
+#define BANK_4  0x04
+#define BANK_5  0x05
+#define BANK_A  0x0A
+#define BANK_B  0x0B
+#define BANK_11 0x11
+#define BANK_13 0x13
+#define BANK_20 0x20
+#define BANK_21 0x21
+#define BANK_22 0x22
+
+
+typedef struct _decoder_get_information_str
+{
+	unsigned char chip_id[4];
+	unsigned char chip_rev[4];
+	unsigned char chip_addr[4];
+
+	unsigned char Total_Port_Num;
+	unsigned char Total_Chip_Cnt;
+
+}decoder_get_information_str;
+
+typedef struct _decoder_dev_ch_info_s
+{
+	unsigned char ch;
+	unsigned char devnum;
+	unsigned char fmt_def;
+}decoder_dev_ch_info_s;
+
+
+typedef enum NC_FORMAT_FPS
+{
+	FMT_FPS_UNKNOWN = 0,
+	FMT_NT = 1,
+	FMT_PAL,
+	FMT_12_5P,
+	FMT_7_5P,
+	FMT_30P,
+	FMT_25P,
+	FMT_50P,
+	FMT_60P,
+	FMT_15P,
+	FMT_18P,
+	FMT_18_75P,
+	FMT_20P,
+
+	FMT_FPS_MAX,
+
+} NC_FORMAT_FPS;
+
+//#define FMT_AUTO (-1)
+
+typedef enum NC_FORMAT_STANDARD
+{
+	FMT_STD_UNKNOWN = 0,
+	FMT_SD,
+	FMT_AHD20,
+	FMT_AHD30,
+	FMT_TVI,
+	FMT_CVI,
+
+	FMT_AUTO,		// FIXME
+
+	FMT_STD_MAX,
+
+} NC_FORMAT_STANDARD;
+
+
+typedef enum NC_FORMAT_RESOLUTION
+{
+	FMT_RESOL_UNKNOWN = 0,
+	FMT_SH720,
+	FMT_H960,
+	FMT_H1280,
+	FMT_H1440,
+	FMT_H960_EX,
+	FMT_H960_2EX,
+	FMT_H960_Btype_2EX,
+	FMT_720P,
+	FMT_720P_EX,
+	FMT_720P_Btype,
+	FMT_720P_Btype_EX,
+	FMT_1080P,
+	FMT_3M,
+	FMT_4M,
+	FMT_5M,
+	FMT_5_3M,
+	FMT_6M,
+	FMT_8M_X,
+	FMT_8M,
+	FMT_960P,
+
+	FMT_H960_Btype_2EX_SP,
+	FMT_720P_Btype_EX_SP,
+
+	FMT_RESOL_MAX,
+} NC_FORMAT_RESOLUTION;
+
+
+typedef enum NC_VIVO_CH_FORMATDEF
+{
+	NC_VIVO_CH_FORMATDEF_UNKNOWN = 0,
+	NC_VIVO_CH_FORMATDEF_AUTO,
+
+	AHD20_SD_H960_NT,
+	AHD20_SD_H960_PAL,
+	AHD20_SD_SH720_NT,
+	AHD20_SD_SH720_PAL,
+	AHD20_SD_H1280_NT,
+	AHD20_SD_H1280_PAL,
+	AHD20_SD_H1440_NT,
+	AHD20_SD_H1440_PAL,
+	AHD20_SD_H960_EX_NT,
+	AHD20_SD_H960_EX_PAL,
+	AHD20_SD_H960_2EX_NT,
+	AHD20_SD_H960_2EX_PAL,
+	AHD20_SD_H960_2EX_Btype_NT,
+	AHD20_SD_H960_2EX_Btype_PAL,
+	AHD20_1080P_60P, // For Test
+	AHD20_1080P_50P, // For Test
+	AHD20_1080P_30P,
+	AHD20_1080P_25P,
+	AHD20_720P_60P,
+	AHD20_720P_50P,
+	AHD20_720P_30P,
+	AHD20_720P_25P,
+	AHD20_720P_30P_EX,
+	AHD20_720P_25P_EX,
+	AHD20_720P_30P_EX_Btype,
+	AHD20_720P_25P_EX_Btype,
+	AHD20_720P_960P_30P,
+	AHD20_720P_960P_25P,
+
+	AHD30_4M_30P,
+	AHD30_4M_25P,
+	AHD30_4M_15P,
+	AHD30_3M_30P,
+	AHD30_3M_25P,
+	AHD30_3M_18P,
+	AHD30_5M_12_5P,
+	AHD30_5M_20P,
+	AHD30_5_3M_20P,
+	AHD30_6M_18P,
+	AHD30_6M_20P,
+	AHD30_8M_X_30P,
+	AHD30_8M_X_25P,
+	AHD30_8M_7_5P,
+	AHD30_8M_12_5P,
+	AHD30_8M_15P,
+
+	TVI_FHD_30P,
+	TVI_FHD_25P,
+	TVI_HD_60P,
+	TVI_HD_50P,
+	TVI_HD_30P,
+	TVI_HD_25P,
+	TVI_HD_30P_EX,
+	TVI_HD_25P_EX,
+	TVI_HD_B_30P,
+	TVI_HD_B_25P,
+	TVI_HD_B_30P_EX,
+	TVI_HD_B_25P_EX,
+	TVI_3M_18P,
+	TVI_5M_12_5P,
+	TVI_4M_30P,
+	TVI_4M_25P,
+	TVI_4M_15P,
+
+	CVI_FHD_30P,
+	CVI_FHD_25P,
+	CVI_HD_60P,
+	CVI_HD_50P,
+	CVI_HD_30P,
+	CVI_HD_25P,
+	CVI_HD_30P_EX,
+	CVI_HD_25P_EX,
+	CVI_4M_30P,
+	CVI_4M_25P,
+	CVI_8M_15P,
+	CVI_8M_12_5P,
+
+	AHD20_SD_H960_2EX_Btype_SP_NT,
+	AHD20_SD_H960_2EX_Btype_SP_PAL,
+
+	AHD20_720P_30P_EX_Btype_SP,
+	AHD20_720P_25P_EX_Btype_SP,
+
+	NC_VIVO_CH_FORMATDEF_MAX,
+
+} NC_VIVO_CH_FORMATDEF;
+
+typedef enum NC_OUTPUT_MUX_MODE
+{
+	NC_MX_MUX1 = 0,
+	NC_MX_MUX2,
+	NC_MX_MUX4,
+} NC_OUTPUT_MUX_MODE;
+
+typedef enum NC_OUTPUT_INTERFACE
+{
+	NC_OI_BT656 = 0,              /* ITU-R BT.656 YUV4:2:2 */
+	NC_OI_BT601,                  /* ITU-R BT.601 YUV4:2:2 */
+	NC_OI_DIGITAL_CAMERA,         /* digatal camera mode */
+	NC_OI_BT1120_STANDARD,        /* BT.1120 progressive mode */
+	NC_OI_BT1120_INTERLEAVED,     /* BT.1120 interstage mode */
+} NC_OUTPUT_INTERFACE;
+
+typedef enum NC_OUTPUT_EDGE
+{
+	NC_OE_SINGLE_UP = 0,         /* single-edge mode and in rising edge */
+	NC_OE_SINGLE_DOWN,           /* single-edge mode and in falling edge */
+	NC_OE_DOUBLE ,
+} NC_OUTPUT_EDGE;
+
+
+
+typedef enum NC_ANALOG_INPUT
+{
+	SINGLE_ENDED = 0,
+	DIFFERENTIAL,
+} NC_ANALOG_INPUT;
+
+typedef enum NC_CABLE
+{
+	CABLE_A = 0,
+	CABLE_B,
+	CABLE_C,
+	CABLE_D,
+} NC_CABLE;
+
+typedef enum NC_STAGE
+{
+	STAGE_0 = 0,
+	STAGE_1,
+	STAGE_2,
+	STAGE_3,
+	STAGE_4,
+	STAGE_5,
+} NC_STAGE;
+
+typedef enum NC_JAGUAR1_EQ
+{
+	NC_EQ_SETTING_FMT_UNKNOWN = 0,
+
+	AHD20_SD_H720_NT_SINGLE_ENDED,
+	AHD20_SD_H720_NT_DIFFERENTIAL,
+	AHD20_SD_H720_PAL_SINGLE_ENDED,
+	AHD20_SD_H720_PAL_DIFFERENTIAL,
+
+	AHD20_SD_H960_2EX_Btype_NT_SINGLE_ENDED,
+	AHD20_SD_H960_2EX_Btype_NT_DIFFERENTIAL,
+	AHD20_SD_H960_2EX_Btype_PAL_SINGLE_ENDED,
+	AHD20_SD_H960_2EX_Btype_PAL_DIFFERENTIAL,
+
+	AHD20_SD_H1440_NT_SINGLE_ENDED,
+	AHD20_SD_H1440_NT_DIFFERENTIAL,
+	AHD20_SD_H1440_PAL_SINGLE_ENDED,
+	AHD20_SD_H1440_PAL_DIFFERENTIAL,
+
+	AHD20_1080P_30P_SINGLE_ENDED,
+	AHD20_1080P_30P_DIFFERENTIAL,
+	AHD20_1080P_25P_SINGLE_ENDED,
+	AHD20_1080P_25P_DIFFERENTIAL,
+
+	AHD20_720P_60P_SINGLE_ENDED,
+	AHD20_720P_60P_DIFFERENTIAL,
+	AHD20_720P_50P_SINGLE_ENDED,
+	AHD20_720P_50P_DIFFERENTIAL,
+
+	AHD20_720P_30P_SINGLE_ENDED,
+	AHD20_720P_30P_DIFFERENTIAL,
+	AHD20_720P_25P_SINGLE_ENDED,
+	AHD20_720P_25P_DIFFERENTIAL,
+
+	AHD20_720P_30P_EX_SINGLE_ENDED,
+	AHD20_720P_30P_EX_DIFFERENTIAL,
+	AHD20_720P_25P_EX_SINGLE_ENDED,
+	AHD20_720P_25P_EX_DIFFERENTIAL,
+
+	AHD20_720P_30P_EX_Btype_SINGLE_ENDED,
+	AHD20_720P_30P_EX_Btype_DIFFERENTIAL,
+	AHD20_720P_25P_EX_Btype_SINGLE_ENDED,
+	AHD20_720P_25P_EX_Btype_DIFFERENTIAL,
+
+	AHD20_960P_30P_SINGLE_ENDED,
+	AHD20_960P_30P_DIFFERENTIAL,
+	AHD20_960P_25P_SINGLE_ENDED,
+	AHD20_960P_25P_DIFFERENTIAL,
+
+	TVI_FHD_30P_SINGLE_ENDED,
+	TVI_FHD_30P_DIFFERENTIAL,
+	TVI_FHD_25P_SINGLE_ENDED,
+	TVI_FHD_25P_DIFFERENTIAL,
+
+	TVI_HD_60P_SINGLE_ENDED,
+	TVI_HD_60P_DIFFERENTIAL,
+	TVI_HD_50P_SINGLE_ENDED,
+	TVI_HD_50P_DIFFERENTIAL,
+
+	TVI_HD_30P_SINGLE_ENDED,
+	TVI_HD_30P_DIFFERENTIAL,
+	TVI_HD_25P_SINGLE_ENDED,
+	TVI_HD_25P_DIFFERENTIAL,
+
+	TVI_HD_30P_EX_SINGLE_ENDED,
+	TVI_HD_30P_EX_DIFFERENTIAL,
+	TVI_HD_25P_EX_SINGLE_ENDED,
+	TVI_HD_25P_EX_DIFFERENTIAL,
+
+	TVI_HD_B_30P_SINGLE_ENDED,
+	TVI_HD_B_30P_DIFFERENTIAL,
+	TVI_HD_B_25P_SINGLE_ENDED,
+	TVI_HD_B_25P_DIFFERENTIAL,
+
+	TVI_HD_B_30P_EX_SINGLE_ENDED,
+	TVI_HD_B_30P_EX_DIFFERENTIAL,
+	TVI_HD_B_25P_EX_SINGLE_ENDED,
+	TVI_HD_B_25P_EX_DIFFERENTIAL,
+
+	CVI_FHD_30P_SINGLE_ENDED,
+	CVI_FHD_30P_DIFFERENTIAL,
+	CVI_FHD_25P_SINGLE_ENDED,
+	CVI_FHD_25P_DIFFERENTIAL,
+
+	CVI_HD_60P_SINGLE_ENDED,
+	CVI_HD_60P_DIFFERENTIAL,
+	CVI_HD_50P_SINGLE_ENDED,
+	CVI_HD_50P_DIFFERENTIAL,
+
+	CVI_HD_30P_SINGLE_ENDED,
+	CVI_HD_30P_DIFFERENTIAL,
+	CVI_HD_25P_SINGLE_ENDED,
+	CVI_HD_25P_DIFFERENTIAL,
+
+	CVI_HD_30P_EX_SINGLE_ENDED,
+	CVI_HD_30P_EX_DIFFERENTIAL,
+	CVI_HD_25P_EX_SINGLE_ENDED,
+	CVI_HD_25P_EX_DIFFERENTIAL,
+
+	NC_EQ_SETTING_FMT_MAX,
+
+
+}NC_JAGUAR1_EQ;
+
+typedef enum NC_D2S_OUTPUT_INTERFACE
+{
+	DISABLE = 0,
+	YUV_422,
+	YUV_420,
+	YUV_420_LEGACY,
+} NC_D2S_OUTPUT_INTERFACE;
+
+typedef struct _NC_DEOCDER_SET_STR
+{
+	NC_VIVO_CH_FORMATDEF FmtDef;
+	NC_FORMAT_STANDARD fmt_std;
+	NC_FORMAT_RESOLUTION fmt_res;
+	NC_FORMAT_FPS fmt_fps;
+	NC_ANALOG_INPUT input;
+	NC_D2S_OUTPUT_INTERFACE interface;
+}NC_DEOCDER_SET_STR;
+
+#define UNUSED(x) ((void)(x))
+
+#if 0
+#define dbg_printk(...) _kernel_dbg_printk( __VA_ARGS__)
+
+static void _kernel_dbg_printk(const char* s, ...)
+{
+	unsigned char buffer[128];
+	char *pS = buffer;
+
+	va_list args;
+	va_start(args, s);
+	vsprintf(buffer, s, args);
+	va_end(args);
+
+
+	while(*pS) { if( *pS == '\n' ) *pS= ' '; pS++; }
+
+	printk("\033[33m\033[1m [KERNEL] \033[0m:\033[32m\033[1m %s \033[0m\n", buffer);
+}
+#endif
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#endif
+

drivers/media/i2c/jaguar1_drv/jaguar1_drv.c

@@ -0,0 +1,918 @@
+// SPDX-License-Identifier: GPL-2.0
+/********************************************************************************
+ *
+ *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
+ *  Module		: jaguar1_drv.c
+ *  Description	:
+ *  Author		:
+ *  Date        :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History     :
+ *
+ *
+ ********************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/fcntl.h>
+#include <linux/mm.h>
+#include <linux/proc_fs.h>
+#include <linux/miscdevice.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/string.h>
+#include <linux/list.h>
+#include <asm/delay.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/proc_fs.h>
+#include <linux/poll.h>
+#include <asm/bitops.h>
+#include <asm/uaccess.h>
+#include <asm/irq.h>
+#include <linux/moduleparam.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/semaphore.h>
+#include <linux/kthread.h>
+#include <linux/i2c.h>
+#include <linux/i2c-dev.h>
+
+#include "jaguar1_common.h"
+#include "jaguar1_video.h"
+#include "jaguar1_coax_protocol.h"
+#include "jaguar1_motion.h"
+#include "jaguar1_ioctl.h"
+#include "jaguar1_video_eq.h"
+#include "jaguar1_mipi.h"
+#include "jaguar1_drv.h"
+#ifdef FOR_IMX6
+#include "imx_mipi.h"
+#endif
+//#include "video_eq.h" //To do
+
+//#define STREAM_ON_DEFLAULT
+
+#define I2C_0       (0)
+#define I2C_1       (1)
+#define I2C_2       (2)
+#define I2C_3       (3)
+
+#define JAGUAR1_4PORT_R0_ID 0xB0
+#define JAGUAR1_2PORT_R0_ID 0xA0
+#define JAGUAR1_1PORT_R0_ID 0xA2
+#define AFE_NVP6134E_R0_ID 	0x80
+
+#define JAGUAR1_4PORT_REV_ID 0x00
+#define JAGUAR1_2PORT_REV_ID 0x00
+#define JAGUAR1_1PORT_REV_ID 0x00
+
+static int chip_id[4];
+static int rev_id[4];
+static int jaguar1_cnt;
+unsigned int jaguar1_i2c_addr[4] = {0x60, 0x62, 0x64, 0x66};
+unsigned int jaguar1_mclk = 0; //0:756 1:594 2:378 3:1242
+module_param_named(jaguar1_mclk, jaguar1_mclk, uint, S_IRUGO);
+unsigned int jaguar1_lane = 4; //2 or 4
+module_param_named(jaguar1_lane, jaguar1_lane, uint, S_IRUGO);
+static unsigned int chn = 4;
+module_param_named(jaguar1_chn, chn, uint, S_IRUGO);
+static unsigned int init = 0;
+module_param_named(jaguar1_init, init, uint, S_IRUGO);
+static unsigned int fmt = 2;  //0:960H;1:720P 2:1080P 3:960P 4:SH720
+module_param_named(jaguar1_fmt, fmt, uint, S_IRUGO);
+static unsigned int ntpal = 0;
+module_param_named(jaguar1_ntpal, ntpal, uint, S_IRUGO);
+
+static bool jaguar1_init_state;
+struct semaphore jaguar1_lock;
+struct i2c_client* jaguar1_client;
+static struct i2c_board_info hi_info =
+{
+	I2C_BOARD_INFO("jaguar1", 0x60),
+};
+decoder_get_information_str decoder_inform;
+
+unsigned int acp_mode_enable = 1;
+module_param(acp_mode_enable, uint, S_IRUGO);
+
+static void vd_pattern_enable(void)
+{
+	gpio_i2c_write(0x60, 0xFF, 0x00);
+	gpio_i2c_write(0x60, 0x1C, 0x1A);
+	gpio_i2c_write(0x60, 0x1D, 0x1A);
+	gpio_i2c_write(0x60, 0x1E, 0x1A);
+	gpio_i2c_write(0x60, 0x1F, 0x1A);
+
+	gpio_i2c_write(0x60, 0xFF, 0x05);
+	gpio_i2c_write(0x60, 0x6A, 0x80);
+	gpio_i2c_write(0x60, 0xFF, 0x06);
+	gpio_i2c_write(0x60, 0x6A, 0x80);
+	gpio_i2c_write(0x60, 0xFF, 0x07);
+	gpio_i2c_write(0x60, 0x6A, 0x80);
+	gpio_i2c_write(0x60, 0xFF, 0x08);
+	gpio_i2c_write(0x60, 0x6A, 0x80);
+}
+
+/*******************************************************************************
+ *	Description		: Sample function - for select video format
+ *	Argurments		: int dev_num(i2c_address array's num)
+ *	Return value	: void
+ *	Modify			:
+ *	warning			:
+ *******************************************************************************/
+#if 0
+static void set_default_video_fmt(int dev_num)
+{
+#if 0 // Activate this block if a default video-setting is required.
+	int i;
+	video_input_init  video_val;
+
+	/* default video datatype setting */
+	mipi_datatype_set(VD_DATA_TYPE_YUV422);
+
+	/* mipi_tx_initial */
+	mipi_tx_init(dev_num);
+
+	/* run default video format setting */
+	for( i=0 ; i<4 ; i++)
+	{
+		video_val.ch = i;
+
+		/* select video format, include struct'vd_vi_init_list' in jaguar1_video_table.h
+		 *  ex > AHD20_1080P_30P / AHD20_720P_25P_EX_Btype / AHD20_SD_H960_2EX_Btype_NT */
+		video_val.format = AHD20_720P_30P_EX_Btype;
+		// select analog input type, SINGLE_ENDED or DIFFERENTIAL
+		video_val.input = SINGLE_ENDED;
+		// select decoder to soc interface
+		video_val.interface = YUV_422;
+
+		// run video setting
+		vd_jaguar1_init_set(&video_val);
+
+		// run video format setting for mipi/arbiter
+		mipi_video_format_set(&video_val);
+		set_imx_video_format(&video_val);
+		init_imx_mipi(i);
+	}
+	arb_init(dev_num);
+	disable_parallel(dev_num);
+#endif
+}
+#endif
+
+/*******************************************************************************
+ *	Description		: Check ID
+ *	Argurments		: dec(slave address)
+ *	Return value	: Device ID
+ *	Modify			:
+ *	warning			:
+ *******************************************************************************/
+static void vd_set_all(video_init_all *param)
+{
+	int i, dev_num=0;
+	video_input_init  video_val[4];
+
+#if 0
+	for(i=0 ; i<4 ; i++)
+	{
+		printk("[DRV || %s] ch%d / fmt:%d / input:%d / interface:%d\n",__func__
+				, param->ch_param[i].ch
+				, param->ch_param[i].format
+				, param->ch_param[i].input
+				, param->ch_param[i].interface);
+	}
+#endif
+	mipi_datatype_set(VD_DATA_TYPE_YUV422); // to do
+	mipi_tx_init(dev_num);
+
+	for( i=0 ; i<4 ; i++)
+	{
+		video_val[i].ch = param->ch_param[i].ch;
+		video_val[i].format = param->ch_param[i].format;
+		video_val[i].input = param->ch_param[i].input;
+		if(i<chn)
+			video_val[i].interface = param->ch_param[i].interface;
+		else
+			video_val[i].interface = DISABLE;
+
+		vd_jaguar1_init_set(&video_val[i]);
+		mipi_video_format_set(&video_val[i]);
+#ifdef FOR_IMX6
+		set_imx_video_format(&video_val[i]);
+		if(video_val[i].interface == DISABLE)
+		{
+			printk("[DRV] Nothing selected [video ch : %d]\n", i);
+		}
+		else
+		{
+			init_imx_mipi(i);
+		}
+#endif
+	}
+	arb_init(dev_num);
+	disable_parallel(dev_num);
+	vd_pattern_enable();
+}
+
+/*******************************************************************************
+ *	Description		: Check ID
+ *	Argurments		: dec(slave address)
+ *	Return value	: Device ID
+ *	Modify			:
+ *	warning			:
+ *******************************************************************************/
+static int check_id(unsigned int dec)
+{
+	int ret;
+	gpio_i2c_write(dec, 0xFF, 0x00);
+	ret = gpio_i2c_read(dec, 0xf4);
+	return ret;
+}
+
+/*******************************************************************************
+ *	Description		: Get rev ID
+ *	Argurments		: dec(slave address)
+ *	Return value	: rev ID
+ *	Modify			:
+ *	warning			:
+ *******************************************************************************/
+static int check_rev(unsigned int dec)
+{
+	int ret;
+	gpio_i2c_write(dec, 0xFF, 0x00);
+	ret = gpio_i2c_read(dec, 0xf5);
+	return ret;
+}
+
+/*******************************************************************************
+ *	Description		: Check decoder count
+ *	Argurments		: void
+ *	Return value	: (total chip count - 1) or -1(not found any chip)
+ *	Modify			:
+ *	warning			:
+ *******************************************************************************/
+static int check_decoder_count(void)
+{
+	int chip, i;
+	int ret = -1;
+
+	for(chip=0;chip<4;chip++)
+	{
+		chip_id[chip] = check_id(jaguar1_i2c_addr[chip]);
+		rev_id[chip]  = check_rev(jaguar1_i2c_addr[chip]);
+		if( (chip_id[chip] != JAGUAR1_4PORT_R0_ID )  	&&
+				(chip_id[chip] != JAGUAR1_2PORT_R0_ID) 		&&
+				(chip_id[chip] != JAGUAR1_1PORT_R0_ID)		&&
+				(chip_id[chip] != AFE_NVP6134E_R0_ID)
+		  )
+		{
+			printk("Device ID Error... %x, Chip Count:[%d]\n", chip_id[chip], chip);
+			jaguar1_i2c_addr[chip] = 0xFF;
+			chip_id[chip] = 0xFF;
+		}
+		else
+		{
+			printk("Device (0x%x) ID OK... %x , Chip Count:[%d]\n", jaguar1_i2c_addr[chip], chip_id[chip], chip);
+			printk("Device (0x%x) REV %x\n", jaguar1_i2c_addr[chip], rev_id[chip]);
+			jaguar1_i2c_addr[jaguar1_cnt] = jaguar1_i2c_addr[chip];
+
+			if(jaguar1_cnt<chip)
+			{
+				jaguar1_i2c_addr[chip] = 0xFF;
+			}
+
+			chip_id[jaguar1_cnt] = chip_id[chip];
+			rev_id[jaguar1_cnt]  = rev_id[chip];
+
+			jaguar1_cnt++;
+		}
+
+		if((chip == 3) && (jaguar1_cnt < chip))
+		{
+			for(i = jaguar1_cnt; i < 4; i++)
+			{
+				chip_id[i] = 0xff;
+				rev_id[i]  = 0xff;
+			}
+		}
+	}
+	printk("Chip Count = %d\n", jaguar1_cnt);
+	printk("Address [0x%x][0x%x][0x%x][0x%x]\n",jaguar1_i2c_addr[0],jaguar1_i2c_addr[1],jaguar1_i2c_addr[2],jaguar1_i2c_addr[3]);
+	printk("Chip Id [0x%x][0x%x][0x%x][0x%x]\n",chip_id[0],chip_id[1],chip_id[2],chip_id[3]);
+	printk("Rev Id [0x%x][0x%x][0x%x][0x%x]\n",rev_id[0],rev_id[1],rev_id[2],rev_id[3]);
+
+	for( i = 0; i < 4; i++ )
+	{
+		decoder_inform.chip_id[i] = chip_id[i];
+		decoder_inform.chip_rev[i] = rev_id[i];
+		decoder_inform.chip_addr[i] = jaguar1_i2c_addr[i];
+	}
+	decoder_inform.Total_Chip_Cnt = jaguar1_cnt;
+	ret = jaguar1_cnt;
+
+	return ret;
+}
+
+/*******************************************************************************
+ *	Description		: Video decoder initial
+ *	Argurments		: void
+ *	Return value	: void
+ *	Modify			:
+ *	warning			:
+ *******************************************************************************/
+static void video_decoder_init(void)
+{
+	int ii = 0;
+
+	// Pad Control Setting
+	gpio_i2c_write(jaguar1_i2c_addr[0], 0xff, 0x04);
+
+	for(ii =0; ii<36; ii++)
+	{
+		gpio_i2c_write(jaguar1_i2c_addr[0], 0xa0 + ii , 0x24);
+	}
+
+	// Clock Delay Setting
+	gpio_i2c_write(jaguar1_i2c_addr[0], 0xff, 0x01);
+	for(ii =0; ii<4; ii++)
+	{
+		gpio_i2c_write(jaguar1_i2c_addr[0], 0xcc + ii , 0x64);
+	}
+#if 1
+	// MIPI_V_REG_OFF
+	gpio_i2c_write(jaguar1_i2c_addr[0], 0xff, 0x21);
+	gpio_i2c_write(jaguar1_i2c_addr[0], 0x07, 0x80);
+	gpio_i2c_write(jaguar1_i2c_addr[0], 0x07, 0x00);
+#endif
+
+#if 1
+	// AGC_OFF  08.31
+	gpio_i2c_write(jaguar1_i2c_addr[0], 0xff, 0x0A);
+	gpio_i2c_write(jaguar1_i2c_addr[0], 0x77, 0x8F);
+	gpio_i2c_write(jaguar1_i2c_addr[0], 0xF7, 0x8F);
+	gpio_i2c_write(jaguar1_i2c_addr[0], 0xff, 0x0B);
+	gpio_i2c_write(jaguar1_i2c_addr[0], 0x77, 0x8F);
+	gpio_i2c_write(jaguar1_i2c_addr[0], 0xF7, 0x8F);
+#endif
+}
+
+/*******************************************************************************
+ *	Description		: Driver open
+ *	Argurments		:
+ *	Return value	:
+ *	Modify			:
+ *	warning			:
+ *******************************************************************************/
+static int jaguar1_open(struct inode * inode, struct file * file)
+{
+	printk("[DRV] Jaguar1 Driver Open\n");
+	printk("[DRV] Jaguar1 Driver Ver::%s\n", DRIVER_VER);
+	return 0;
+} 
+
+/*******************************************************************************
+ *	Description		: Driver close
+ *	Argurments		:
+ *	Return value	:
+ *	Modify			:
+ *	warning			:
+ *******************************************************************************/
+static int jaguar1_close(struct inode * inode, struct file * file)
+{
+	printk("[DRV] Jaguar1 Driver Close\n");
+	return 0;
+}
+
+/*******************************************************************************
+ *	Description		: Driver IOCTL function
+ *	Argurments		:
+ *	Return value	:
+ *	Modify			:
+ *	warning			:
+ *******************************************************************************/
+static long jaguar1_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+	int cpy2usr_ret;
+	unsigned int __user *argp = (unsigned int __user *)arg;	
+
+	/* AllVideo Variable */
+	video_init_all all_vd_val;
+
+	/* Video Variable */
+	video_input_init  video_val;
+	video_output_init vo_seq_set;
+	video_equalizer_info_s video_eq;
+	video_video_loss_s vidloss;
+
+	/* Coaxial Protocol Variable */
+	NC_VD_COAX_STR           coax_val;
+	NC_VD_COAX_BANK_DUMP_STR coax_bank_dump;
+	FIRMWARE_UP_FILE_INFO    coax_fw_val;
+	NC_VD_COAX_TEST_STR      coax_test_val;
+
+	/* Motion Variable */
+	motion_mode motion_set;
+
+	nc_acp_rw_data ispdata;
+
+	down(&jaguar1_lock);
+
+	switch (cmd)
+	{
+		/*===============================================================================================
+		 * Set All - for MIPI Interface
+		 *===============================================================================================*/
+		case IOC_VDEC_INIT_ALL:
+			if(copy_from_user(&all_vd_val, argp, sizeof(video_init_all)))
+				printk("IOC_VDEC_INPUT_INIT error\n");
+			vd_set_all(&all_vd_val);
+			break;
+		/*===============================================================================================
+		 * Video Initialize
+		 *===============================================================================================*/
+		case IOC_VDEC_INPUT_INIT:
+			if(copy_from_user(&video_val, argp, sizeof(video_input_init)))
+				printk("IOC_VDEC_INPUT_INIT error\n");
+			vd_jaguar1_init_set(&video_val);
+			break;
+		case IOC_VDEC_OUTPUT_SEQ_SET:
+			if(copy_from_user(&vo_seq_set, argp, sizeof(video_output_init)))
+				printk("IOC_VDEC_INPUT_INIT error\n");
+			vd_jaguar1_vo_ch_seq_set(&vo_seq_set);
+			break;
+		case IOC_VDEC_VIDEO_EQ_SET:
+			if(copy_from_user(&video_eq, argp, sizeof(video_equalizer_info_s)))
+				printk("IOC_VDEC_INPUT_INIT error\n");
+			video_input_eq_val_set(&video_eq);
+			break;
+		case IOC_VDEC_VIDEO_SW_RESET:
+			if(copy_from_user(&video_val, argp, sizeof(video_input_init)))
+				printk("IOC_VDEC_INPUT_INIT error\n");
+			vd_jaguar1_sw_reset(&video_val);
+			break;
+		case IOC_VDEC_VIDEO_EQ_CABLE_SET:
+			if(copy_from_user(&video_eq, argp, sizeof(video_equalizer_info_s)))
+				printk("IOC_VDEC_INPUT_INIT error\n");
+			video_input_eq_cable_set(&video_eq);
+			break;
+		case IOC_VDEC_VIDEO_EQ_ANALOG_INPUT_SET:
+			if(copy_from_user(&video_eq, argp, sizeof(video_equalizer_info_s)))
+				printk("IOC_VDEC_INPUT_INIT error\n");
+			video_input_eq_analog_input_set(&video_eq);
+			break;
+		case IOC_VDEC_VIDEO_GET_VIDEO_LOSS:
+			if(copy_from_user(&vidloss, argp, sizeof(video_video_loss_s)))
+				printk("IOC_VDEC_VIDEO_GET_VIDEO_LOSS error\n");
+			vd_jaguar1_get_novideo(&vidloss);
+			cpy2usr_ret = copy_to_user(argp, &vidloss, sizeof(video_video_loss_s));
+			break;
+			/*===============================================================================================
+			 * Coaxial Protocol
+			 *===============================================================================================*/
+		case IOC_VDEC_COAX_TX_INIT:   //SK_CHANGE 170703
+			if(copy_from_user(&coax_val, argp, sizeof(NC_VD_COAX_STR)))
+				printk("IOC_VDEC_COAX_TX_INIT error\n");
+			coax_tx_init(&coax_val);
+			break;
+		case IOC_VDEC_COAX_TX_16BIT_INIT:   //SK_CHANGE 170703
+			if(copy_from_user(&coax_val, argp, sizeof(NC_VD_COAX_STR)))
+				printk("IOC_VDEC_COAX_TX_INIT error\n");
+			coax_tx_16bit_init(&coax_val);
+			break;
+		case IOC_VDEC_COAX_TX_CMD_SEND: //SK_CHANGE 170703
+			if(copy_from_user(&coax_val, argp, sizeof(NC_VD_COAX_STR)))
+				printk(" IOC_VDEC_COAX_TX_CMD_SEND error\n");
+			coax_tx_cmd_send(&coax_val);
+			break;
+		case IOC_VDEC_COAX_TX_16BIT_CMD_SEND: //SK_CHANGE 170703
+			if(copy_from_user(&coax_val, argp, sizeof(NC_VD_COAX_STR)))
+				printk(" IOC_VDEC_COAX_TX_CMD_SEND error\n");
+			coax_tx_16bit_cmd_send(&coax_val);
+			break;
+		case IOC_VDEC_COAX_TX_CVI_NEW_CMD_SEND: //SK_CHANGE 170703
+			if(copy_from_user(&coax_val, argp, sizeof(NC_VD_COAX_STR)))
+				printk(" IOC_VDEC_COAX_TX_CMD_SEND error\n");
+			coax_tx_cvi_new_cmd_send(&coax_val);
+			break;
+		case IOC_VDEC_COAX_RX_INIT:
+			if(copy_from_user(&coax_val, argp, sizeof(NC_VD_COAX_STR)))
+				printk(" IOC_VDEC_COAX_RX_INIT error\n");
+			coax_rx_init(&coax_val);
+			break;
+		case IOC_VDEC_COAX_RX_DATA_READ:
+			if(copy_from_user(&coax_val, argp, sizeof(NC_VD_COAX_STR)))
+				printk(" IOC_VDEC_COAX_RX_DATA_READ error\n");
+			coax_rx_data_get(&coax_val);
+			cpy2usr_ret = copy_to_user(argp, &coax_val, sizeof(NC_VD_COAX_STR));
+			break;
+		case IOC_VDEC_COAX_RX_BUF_CLEAR:
+			if(copy_from_user(&coax_val, argp, sizeof(NC_VD_COAX_STR)))
+				printk(" IOC_VDEC_COAX_RX_BUF_CLEAR error\n");
+			coax_rx_buffer_clear(&coax_val);
+			break;
+		case IOC_VDEC_COAX_RX_DEINIT:
+			if(copy_from_user(&coax_val, argp, sizeof(NC_VD_COAX_STR)))
+				printk("IOC_VDEC_COAX_RX_DEINIT error\n");
+			coax_rx_deinit(&coax_val);
+			break;
+		case IOC_VDEC_COAX_BANK_DUMP_GET:
+			if(copy_from_user(&coax_bank_dump, argp, sizeof(NC_VD_COAX_BANK_DUMP_STR)))
+				printk("IOC_VDEC_COAX_BANK_DUMP_GET error\n");
+			coax_test_Bank_dump_get(&coax_bank_dump);
+			cpy2usr_ret = copy_to_user(argp, &coax_bank_dump, sizeof(NC_VD_COAX_BANK_DUMP_STR));
+			break;
+		case IOC_VDEC_COAX_RX_DETECTION_READ:
+			if(copy_from_user(&coax_val, argp, sizeof(NC_VD_COAX_STR)))
+				printk(" IOC_VDEC_COAX_RX_DATA_READ error\n");
+			coax_acp_rx_detect_get(&coax_val);
+			cpy2usr_ret = copy_to_user(argp, &coax_val, sizeof(NC_VD_COAX_STR));
+			break;
+			/*===============================================================================================
+			 * Coaxial Protocol. Function
+			 *===============================================================================================*/
+		case IOC_VDEC_COAX_RT_NRT_MODE_CHANGE_SET:
+			if(copy_from_user(&coax_val, argp, sizeof(NC_VD_COAX_STR)))
+				printk(" IOC_VDEC_COAX_SHOT_SET error\n");
+			coax_option_rt_nrt_mode_change_set(&coax_val);
+			cpy2usr_ret = copy_to_user(argp, &coax_val, sizeof(NC_VD_COAX_STR));
+			break;
+		case IOC_VDEC_ACP_WRITE:
+			if (copy_from_user(&ispdata, argp, sizeof(nc_acp_rw_data))) {
+				up(&jaguar1_lock);
+				return -1;
+			}
+			if(ispdata.opt == 0)
+				acp_isp_write(ispdata.ch, ispdata.addr, ispdata.data);
+			else
+			{
+				ispdata.data = acp_isp_read(ispdata.ch, ispdata.addr);
+				if(copy_to_user(argp, &ispdata, sizeof(nc_acp_rw_data)))
+					printk("IOC_VDEC_ACP_WRITE error\n");	
+			}
+			break;
+			/*===============================================================================================
+			 * Coaxial Protocol FW Update
+			 *===============================================================================================*/
+		case IOC_VDEC_COAX_FW_ACP_HEADER_GET:
+			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
+				printk("IOC_VDEC_COAX_FW_READY_CMD_SET error\n");
+			coax_fw_ready_header_check_from_isp_recv(&coax_fw_val);
+			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
+			break;
+		case IOC_VDEC_COAX_FW_READY_CMD_SET:
+			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
+				printk("IOC_VDEC_COAX_FW_READY_CMD_SET error\n");
+			coax_fw_ready_cmd_to_isp_send(&coax_fw_val);
+			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
+			break;
+		case IOC_VDEC_COAX_FW_READY_ACK_GET:
+			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
+				printk("IOC_VDEC_COAX_FW_READY_ISP_STATUS_GET error\n");
+			coax_fw_ready_cmd_ack_from_isp_recv(&coax_fw_val);
+			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
+			break;
+		case IOC_VDEC_COAX_FW_START_CMD_SET:
+			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
+				printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
+			coax_fw_start_cmd_to_isp_send(&coax_fw_val);
+			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
+			break;
+		case IOC_VDEC_COAX_FW_START_ACK_GET:
+			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
+				printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
+			coax_fw_start_cmd_ack_from_isp_recv(&coax_fw_val);
+			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
+			break;
+		case IOC_VDEC_COAX_FW_SEND_DATA_SET:
+			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
+				printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
+			coax_fw_one_packet_data_to_isp_send(&coax_fw_val);
+			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
+			break;
+		case IOC_VDEC_COAX_FW_SEND_ACK_GET:
+			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
+				printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
+			coax_fw_one_packet_data_ack_from_isp_recv(&coax_fw_val);
+			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
+			break;
+		case IOC_VDEC_COAX_FW_END_CMD_SET:
+			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
+				printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
+			coax_fw_end_cmd_to_isp_send(&coax_fw_val);
+			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
+			break;
+		case IOC_VDEC_COAX_FW_END_ACK_GET:
+			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
+				printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
+			coax_fw_end_cmd_ack_from_isp_recv(&coax_fw_val);
+			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
+			break;
+			/*===============================================================================================
+			 * Test Function
+			 *===============================================================================================*/
+		case IOC_VDEC_COAX_TEST_TX_INIT_DATA_READ:
+			if(copy_from_user(&coax_test_val, argp, sizeof(NC_VD_COAX_TEST_STR)))
+				printk("IOC_VDEC_COAX_INIT_SET error\n");
+			coax_test_tx_init_read(&coax_test_val);
+			cpy2usr_ret = copy_to_user(argp, &coax_test_val, sizeof(NC_VD_COAX_TEST_STR));
+			break;
+		case IOC_VDEC_COAX_TEST_DATA_SET:
+			if(copy_from_user(&coax_test_val, argp, sizeof(NC_VD_COAX_TEST_STR)))
+				printk("IOC_VDEC_COAX_TEST_DATA_SET error\n");
+			coax_test_data_set(&coax_test_val);
+			break;
+		case IOC_VDEC_COAX_TEST_DATA_READ:
+			if(copy_from_user(&coax_test_val, argp, sizeof(NC_VD_COAX_TEST_STR)))
+				printk("IOC_VDEC_COAX_TEST_DATA_SET error\n");
+			coax_test_data_get(&coax_test_val);
+			cpy2usr_ret = copy_to_user(argp, &coax_test_val, sizeof(NC_VD_COAX_TEST_STR));
+			break;
+			/*===============================================================================================
+			 * Motion
+			 *===============================================================================================*/
+		case IOC_VDEC_MOTION_DETECTION_GET :
+			if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
+				printk("IOC_VDEC_MOTION_SET error\n");
+			motion_detection_get(&motion_set);
+			cpy2usr_ret = copy_to_user(argp, &motion_set, sizeof(motion_mode));
+			break;
+		case IOC_VDEC_MOTION_SET :
+			if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
+				printk("IOC_VDEC_MOTION_SET error\n");
+			motion_onoff_set(&motion_set);
+			break;
+		case IOC_VDEC_MOTION_PIXEL_SET :
+			if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
+				printk("IOC_VDEC_MOTION_Pixel_SET error\n");
+			motion_pixel_onoff_set(&motion_set);
+			break;
+		case IOC_VDEC_MOTION_PIXEL_GET :
+			if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
+				printk("IOC_VDEC_MOTION_Pixel_SET error\n");
+			motion_pixel_onoff_get(&motion_set);
+			cpy2usr_ret = copy_to_user(argp, &motion_set, sizeof(motion_mode));
+			break;
+		case IOC_VDEC_MOTION_ALL_PIXEL_SET :
+			if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
+				printk("IOC_VDEC_MOTION_Pixel_SET error\n");
+			motion_pixel_all_onoff_set(&motion_set);
+			break;
+		case IOC_VDEC_MOTION_TSEN_SET :
+			if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
+				printk("IOC_VDEC_MOTION_TSEN_SET error\n");
+			motion_tsen_set(&motion_set);
+			break;
+		case IOC_VDEC_MOTION_PSEN_SET :
+			if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
+				printk("IOC_VDEC_MOTION_PSEN_SET error\n");
+			motion_psen_set(&motion_set);
+			break;
+			/*===============================================================================================
+			 * Version
+			 *===============================================================================================*/
+		case IOC_VDEC_GET_DRIVERVER :
+			if(copy_to_user(argp, &DRIVER_VER, sizeof(DRIVER_VER)))
+				printk("IOC_VDEC_GET_DRIVERVER error\n");
+			break;
+	}
+
+	up(&jaguar1_lock);
+
+	return 0;
+}
+
+/*
+ * mclk
+ * default: 756MHZ
+ *       1: 378MHZ
+ *       2: 594MHZ
+ *	 3: 1242MHZ
+ */
+void jaguar1_set_mclk(unsigned int mclk)
+{
+	jaguar1_mclk = mclk;
+}
+
+void jaguar1_start(video_init_all *video_init)
+{
+	down(&jaguar1_lock);
+	vd_set_all(video_init);
+	up(&jaguar1_lock);
+}
+
+void jaguar1_stop(void)
+{
+	video_input_init  video_val;
+
+	down(&jaguar1_lock);
+	arb_disable(0);
+	gpio_i2c_write(0x60, 0xff, 0x20);
+
+	// ARB RESET High
+	gpio_i2c_write(0x60, 0x40, 0x11);
+	usleep_range(3000, 5000);
+	gpio_i2c_write(0x60, 0x40, 0x00);
+	vd_jaguar1_sw_reset(&video_val);
+	up(&jaguar1_lock);
+}
+
+/*******************************************************************************
+ *	Description		: i2c client initial
+ *	Argurments		: void
+ *	Return value	: 0
+ *	Modify			:
+ *	warning			:
+ *******************************************************************************/
+static int i2c_client_init(int i2c_bus)
+{
+	struct i2c_adapter* i2c_adap;
+
+	printk("[DRV] I2C Client Init \n");
+	i2c_adap = i2c_get_adapter(i2c_bus);
+	if (!i2c_adap)
+		return -EINVAL;
+
+	jaguar1_client = i2c_new_device(i2c_adap, &hi_info);
+	i2c_put_adapter(i2c_adap);
+
+	return 0;
+}
+
+/*******************************************************************************
+ *	Description		: i2c client release
+ *	Argurments		: void
+ *	Return value	: void
+ *	Modify			:
+ *	warning			:
+ *******************************************************************************/
+static void i2c_client_exit(void)
+{
+	i2c_unregister_device(jaguar1_client);
+}
+
+static struct file_operations jaguar1_fops = {
+	.owner      = THIS_MODULE,
+	.unlocked_ioctl	= jaguar1_ioctl,
+	.open       = jaguar1_open,
+	.release    = jaguar1_close
+};
+
+static struct miscdevice jaguar1_dev = {
+	.minor		= MISC_DYNAMIC_MINOR,
+	.name		= "jaguar1",
+	.fops  		= &jaguar1_fops,
+};
+
+int jaguar1_init(int i2c_bus)
+{
+	int ret = 0;
+#ifdef FMT_SETTING_SAMPLE
+	int dev_num = 0;
+#endif
+
+	if (jaguar1_init_state)
+		return 0;
+
+	ret = i2c_client_init(i2c_bus);
+	if (ret) {
+		printk(KERN_ERR "ERROR: could not find jaguar1\n");
+		return ret;
+	}
+
+	/* decoder count function */
+	ret = check_decoder_count();
+	if (ret <= 0) {
+		printk(KERN_ERR "ERROR: could not find jaguar1 devices:%#x\n", ret);
+		i2c_client_exit();
+		return -ENODEV;
+	}
+
+	/* initialize semaphore */
+	sema_init(&jaguar1_lock, 1);
+	down(&jaguar1_lock);
+	video_decoder_init();
+	up(&jaguar1_lock);
+	jaguar1_init_state = true;
+
+	return 0;
+}
+
+void jaguar1_exit(void)
+{
+	i2c_client_exit();
+	jaguar1_init_state = false;
+}
+
+/*******************************************************************************
+ *	Description		: It is called when "insmod jaguar1.ko" command run
+ *	Argurments		: void
+ *	Return value	: -1(could not register jaguar1 device), 0(success)
+ *	Modify			:
+ *	warning			:
+ *******************************************************************************/
+static int __init jaguar1_module_init(void)
+{
+	int ret = 0;
+#ifdef STREAM_ON_DEFLAULT
+	video_init_all sVideoall;
+	int ch;
+
+	jaguar1_mclk= 3;
+	init = true;
+	fmt = 2;
+#endif
+
+	ret = misc_register(&jaguar1_dev);
+	if (ret)
+	{
+		printk(KERN_ERR "ERROR: could not register jaguar1-i2c :%#x\n", ret);
+		return -1;
+	}
+
+#ifdef STREAM_ON_DEFLAULT
+	ret = jaguar1_init(I2C_3);
+	if (ret)
+	{
+		printk(KERN_ERR "ERROR: jaguar1 init failed\n");
+		return -1;
+	}
+
+	down(&jaguar1_lock);
+	if(init)
+	{
+		for(ch=0;ch<jaguar1_cnt*4;ch++)
+		{
+			sVideoall.ch_param[ch].ch = ch;
+			switch(fmt)
+			{
+				case 0:
+					sVideoall.ch_param[ch].format = AHD20_SD_H960_2EX_Btype_NT+ntpal;
+				break;
+				case 2:
+					sVideoall.ch_param[ch].format = AHD20_1080P_25P+ntpal;
+				break;
+				case 3:
+					sVideoall.ch_param[ch].format = AHD20_720P_960P_30P+ntpal;
+				break;
+				case 4:
+					sVideoall.ch_param[ch].format = AHD20_SD_SH720_NT+ntpal;
+				break;
+				default:
+					sVideoall.ch_param[ch].format = AHD20_720P_30P_EX_Btype+ntpal;
+				break;
+			}
+			sVideoall.ch_param[ch].input = SINGLE_ENDED;
+			if(ch<chn)
+				sVideoall.ch_param[ch].interface = YUV_422;
+			else
+				sVideoall.ch_param[ch].interface = DISABLE;
+		}
+		vd_set_all(&sVideoall);
+	}
+
+	up(&jaguar1_lock);
+#endif
+
+	return 0;
+}
+
+/*******************************************************************************
+ *	Description		: It is called when "rmmod nvp61XX_ex.ko" command run
+ *	Argurments		: void
+ *	Return value	: void
+ *	Modify			:
+ *	warning			:
+ *******************************************************************************/
+static void __exit jaguar1_module_exit(void)
+{
+#ifdef FOR_IMX6
+	close_imx_mipi();
+#endif
+	misc_deregister(&jaguar1_dev);
+
+#ifdef STREAM_ON_DEFLAULT
+	jaguar1_exit();
+#endif
+
+	printk("JAGUAR1 DEVICE DRIVER UNLOAD SUCCESS\n");
+}
+
+module_init(jaguar1_module_init);
+module_exit(jaguar1_module_exit);
+
+MODULE_LICENSE("GPL");
+
+/*******************************************************************************
+ *	End of file
+ *******************************************************************************/

drivers/media/i2c/jaguar1_drv/jaguar1_drv.h

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/********************************************************************************
+ *
+ *  Copyright (C) 2017 NEXTCHIP Inc. All rights reserved.
+ *  Module		: Jaguar1 Device Driver
+ *  Description	: MIPI
+ *  Author		:
+ *  Date         :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History      :
+ *
+ *
+ ********************************************************************************/
+#ifndef _JAGUAR1_DRV_
+#define _JAGUAR1_DRV_
+
+#include "jaguar1_video.h"
+
+#define JAGUAR1_MCLK_594MHZ  0x01
+#define JAGUAR1_MCLK_378MHZ  0x02
+#define JAGUAR1_MCLK_1242MHZ 0x03
+
+void jaguar1_set_mclk(unsigned int mclk);
+void jaguar1_start(video_init_all *video_init);
+void jaguar1_stop(void);
+int jaguar1_init(int i2c_bus);
+void jaguar1_exit(void);
+
+#endif

drivers/media/i2c/jaguar1_drv/jaguar1_i2c.c

@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0
+/********************************************************************************
+ *
+ *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
+ *  Module		: i2c.c
+ *  Description	:
+ *  Author		:
+ *  Date         :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History      :
+ *
+ *
+ ********************************************************************************/
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c-dev.h>
+#include "jaguar1_common.h"
+
+extern struct i2c_client* jaguar1_client;
+
+void jaguar1_I2CWriteByte8(unsigned char chip_addr, unsigned char reg_addr, unsigned char value)
+{
+	int ret;
+	unsigned char buf[2];
+	struct i2c_client* client = jaguar1_client;
+
+	client->addr = chip_addr>>1;
+
+	buf[0] = reg_addr;
+	buf[1] = value;
+
+	ret = i2c_master_send(client, buf, 2);
+	udelay(300);
+}
+
+unsigned char jaguar1_I2CReadByte8(unsigned char chip_addr, unsigned char reg_addr)
+{
+	struct i2c_client* client = jaguar1_client;
+
+	client->addr = chip_addr>>1;
+
+	return i2c_smbus_read_byte_data(client, reg_addr);
+}

drivers/media/i2c/jaguar1_drv/jaguar1_ioctl.h

@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __JAGUAR1_IOCTL_H__
+#define __JAGUAR1_IOCTL_H__
+
+/*----------------------- Set All - for MIPI interface  ---------------------*/
+#define IOC_VDEC_INIT_ALL                     0xF0
+
+/*----------------------- VIDEO Initialize  ---------------------*/
+#define IOC_VDEC_INPUT_INIT			 		  0x10
+#define IOC_VDEC_OUTPUT_SEQ_SET		  		  0x11
+#define IOC_VDEC_VIDEO_EQ_SET		  	  	  0x13
+#define IOC_VDEC_VIDEO_SW_RESET				  0x14
+#define IOC_VDEC_SINGLE_DIFFERNTIAL_SET		  0x15
+#define IOC_VDEC_VIDEO_EQ_CABLE_SET		  	  0x16
+#define IOC_VDEC_VIDEO_EQ_ANALOG_INPUT_SET	  0x17
+#define IOC_VDEC_VIDEO_GET_VIDEO_LOSS         0x18
+
+/*----------------------- Coaxial protocol  ---------------------*/
+// Coax UP Stream - 8bit
+#define IOC_VDEC_COAX_TX_INIT			  0xA0
+#define IOC_VDEC_COAX_TX_CMD_SEND	  0xA1
+
+// Coax UP Stream - 16bit only ACP 720P Support
+#define IOC_VDEC_COAX_TX_16BIT_INIT		  0xB4
+#define IOC_VDEC_COAX_TX_16BIT_CMD_SEND	  0xB5
+#define IOC_VDEC_COAX_TX_CVI_NEW_CMD_SEND 0xB6
+
+// Coax Down Stream
+#define IOC_VDEC_COAX_RX_INIT      0xA2
+#define IOC_VDEC_COAX_RX_DATA_READ 0xA3
+#define IOC_VDEC_COAX_RX_BUF_CLEAR 0xA4
+#define IOC_VDEC_COAX_RX_DEINIT    0xA5
+
+// Coax Test
+#define IOC_VDEC_COAX_TEST_TX_INIT_DATA_READ  0xA6
+#define IOC_VDEC_COAX_TEST_DATA_SET           0xA7
+#define IOC_VDEC_COAX_TEST_DATA_READ          0xA8
+
+
+// Coax FW Update
+#define IOC_VDEC_COAX_FW_ACP_HEADER_GET     0xA9
+#define IOC_VDEC_COAX_FW_READY_CMD_SET  0xAA
+#define IOC_VDEC_COAX_FW_READY_ACK_GET  0xAB
+#define IOC_VDEC_COAX_FW_START_CMD_SET  0xAC
+#define IOC_VDEC_COAX_FW_START_ACK_GET  0xAD
+#define IOC_VDEC_COAX_FW_SEND_DATA_SET  0xAE
+#define IOC_VDEC_COAX_FW_SEND_ACK_GET   0xAF
+#define IOC_VDEC_COAX_FW_END_CMD_SET    0xB0
+#define IOC_VDEC_COAX_FW_END_ACK_GET    0xB1
+
+// Bank Dump Test
+#define IOC_VDEC_COAX_BANK_DUMP_GET    0xB2
+
+// ACP Option
+#define IOC_VDEC_COAX_RT_NRT_MODE_CHANGE_SET 0xB3
+#define IOC_VDEC_COAX_RX_DETECTION_READ      0x12
+#define IOC_VDEC_ACP_WRITE                   0xB7
+
+
+/*----------------------- MOTION -----------------*/
+#define IOC_VDEC_MOTION_SET			0x70
+#define IOC_VDEC_MOTION_PIXEL_SET     0x71
+#define IOC_VDEC_MOTION_PIXEL_GET     0x72
+#define IOC_VDEC_MOTION_TSEN_SET      0x73
+#define IOC_VDEC_MOTION_PSEN_SET      0x74
+#define IOC_VDEC_MOTION_ALL_PIXEL_SET 0x75
+#define IOC_VDEC_MOTION_DETECTION_GET 0x76
+
+/*----------------------  GET CHIP ID FUNCTION ---------------------*/
+#define IOC_VDEC_GET_CHIP_ID		0x90
+#define IOC_VDEC_CH_SW_RESET		0x91
+#define IOC_VDEC_HAFC_GAIN12_CTRL	0x92
+#define IOC_VDEC_AFE_RESET			0x93
+#define IOC_VDEC_GET_DRIVERVER      0x94
+
+#define IOC_VDEC_MANUAL_AGC_STABLE_ENABLE	0x82
+#define IOC_VDEC_MANUAL_AGC_STABLE_DISABLE	0x83
+
+#endif

drivers/media/i2c/jaguar1_drv/jaguar1_mipi.c

@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: GPL-2.0
+/********************************************************************************
+ *
+ *  Copyright (C) 2016 	NEXTCHIP Inc. All rights reserved.
+ *  Module		: Jaguar1 Device Driver
+ *  Description	: MIPI
+ *  Author		:
+ *  Date         :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History      :
+ *
+ *
+ ********************************************************************************/
+#include <linux/string.h>
+#include <linux/delay.h>
+#include "jaguar1_common.h"
+#include "jaguar1_mipi.h"
+#include "jaguar1_mipi_table.h"
+
+static unsigned char mipi_dtype, arb_dtype, en_param;
+
+
+/*-------------------------------------------------------------------
+
+  Arbiter function 
+
+  -------------------------------------------------------------------*/
+
+static void arb_scale_set(video_input_init *dev_ch_info, unsigned char val)
+{
+	int devnum = dev_ch_info->ch / 4;
+	unsigned char arb_scale = 0;
+
+	gpio_i2c_write(jaguar1_i2c_addr[devnum], 0xFF, 0x20);
+
+	arb_scale = gpio_i2c_read(jaguar1_i2c_addr[devnum], 0x01);
+	arb_scale &= ~(0x3<<(dev_ch_info->ch*2));
+	arb_scale |= val<<(dev_ch_info->ch*2);
+
+	gpio_i2c_write(jaguar1_i2c_addr[devnum], 0x01, arb_scale);
+}
+
+void arb_enable(int dev_num)
+{
+	if((dev_num < 0) || (dev_num > 3))
+	{
+		printk("[DRV] %s input channel Error (%d)\n",__func__, dev_num);
+		return;
+	}
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xff, 0x20);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x00, en_param);
+	printk("VDEC_ARBITER_INIT done 0x%X\n", en_param);
+}
+
+void arb_disable(int dev_num)
+{
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xff, 0x20);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x00, 0x00);
+}
+
+void arb_init(int dev_num)
+{
+	arb_disable(dev_num);
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xff, 0x20);
+
+	// ARB RESET High
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x40, 0x01);
+	// MIPI Video type Init
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x0F, arb_dtype);
+	// ARB 32Bit Mode
+	if(2 == jaguar1_lane)
+		gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x0D, 0x00); 
+	else
+		gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x0D, 0x01);
+
+	// ARB RESET Low
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x40, 0x00);
+
+	arb_enable(dev_num);
+}
+
+
+/*-------------------------------------------------------------------
+
+  MIPI function 
+
+-------------------------------------------------------------------*/
+
+static void mipi_frame_opt_set(video_input_init *dev_ch_info, unsigned char val)
+{
+	int devnum = dev_ch_info->ch / 4;
+	unsigned char mipi_frame_opt;
+
+	gpio_i2c_write(jaguar1_i2c_addr[devnum], 0xFF, 0x21);
+
+	switch(dev_ch_info->ch)
+	{
+		case 0 :
+			mipi_frame_opt = gpio_i2c_read(jaguar1_i2c_addr[devnum], 0x3E);
+			mipi_frame_opt = (mipi_frame_opt & 0xF0) | val;
+			gpio_i2c_write(jaguar1_i2c_addr[devnum], 0x3E, mipi_frame_opt);
+			break;
+		case 1 :
+			mipi_frame_opt = gpio_i2c_read(jaguar1_i2c_addr[devnum], 0x3E);
+			mipi_frame_opt = (mipi_frame_opt & 0x0F) | val;
+			gpio_i2c_write(jaguar1_i2c_addr[devnum], 0x3E, mipi_frame_opt);
+			break;
+		case 2 :
+			mipi_frame_opt = gpio_i2c_read(jaguar1_i2c_addr[devnum], 0x3F);
+			mipi_frame_opt = (mipi_frame_opt & 0xF0) | val;
+			gpio_i2c_write(jaguar1_i2c_addr[devnum], 0x3F, mipi_frame_opt);
+			break;
+		case 3 :
+			mipi_frame_opt = gpio_i2c_read(jaguar1_i2c_addr[devnum], 0x3F);
+			mipi_frame_opt = (mipi_frame_opt & 0x0F) | val;
+			gpio_i2c_write(jaguar1_i2c_addr[devnum], 0x3F, mipi_frame_opt);
+			break;
+	}
+}
+
+void mipi_video_format_set(video_input_init *dev_ch_info)
+{
+	mipi_vdfmt_set_s mipi_vd_fmt = (mipi_vdfmt_set_s)decoder_mipi_fmtdef[dev_ch_info->format];
+
+	if(dev_ch_info->interface != DISABLE)
+	{
+		en_param |= 0x11<<(dev_ch_info->ch);
+	}
+
+	mipi_frame_opt_set(dev_ch_info, mipi_vd_fmt.mipi_frame_opt);
+	arb_scale_set(dev_ch_info, mipi_vd_fmt.arb_scale);
+}
+
+int mipi_datatype_set(unsigned char data_type)
+{
+	int ret = 0;
+
+	switch(data_type)
+	{
+		case VD_DATA_TYPE_YUV422 :
+			mipi_dtype = 0x1E;
+			arb_dtype = 0x00;
+			break;
+		case VD_DATA_TYPE_YUV420 :
+			mipi_dtype = 0x18;
+			arb_dtype = 0xAA;
+			break;
+		case VD_DATA_TYPE_LEGACY420 :
+			mipi_dtype = 0x1A;
+			arb_dtype = 0x55;
+			break;
+		default :
+			printk("[DRV]%s : invalid data type [0x%X]\n", __func__,  data_type);
+			ret = -1;
+			break;
+	}
+
+	return ret;
+}
+
+void mipi_tx_init(int dev_num)
+{
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xFF, 0x21);	
+
+	pr_info("%s: mclk: %d\n", __func__,  jaguar1_mclk);
+	switch(jaguar1_mclk)
+	{
+		case 3:
+			printk("[DRV] SET_MIPI_1242MHZ\n");
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x40, 0xB4);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x41, 0x00);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x42, 0x03);
+			break;	
+			//		case 3:
+			//		printk("[DRV]_MIPI_252MHZ_TEST_\n");
+			//		gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x40, 0xDC);
+			//		gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x41, 0x20);
+			//		gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x42, 0x05);
+			//		break;
+		case 2:
+			printk("[DRV] SET_MIPI_378MHZ\n");
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x40, 0xDC);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x41, 0x20);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x42, 0x03);
+			break;
+		case 1:
+			printk("[DRV] SET_MIPI_594MHZ\n");
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x40, 0xCC);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x41, 0x10);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x42, 0x03);
+			break;
+		default:
+			printk("[DRV] SET_MIPI_756MHZ\n");
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x40, 0xDC);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x41, 0x10);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x42, 0x03);
+			break;
+	}
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x43, 0x43);
+
+	switch(jaguar1_mclk)
+	{
+		case 3: // 1242MHz MIPI_CLK for FHD*4ch
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x11, 0x08);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x10, 0x13);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x12, 0x0B);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x13, 0x12);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x17, 0x02);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x18, 0x12);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x15, 0x07);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x14, 0x2D);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x16, 0x0B);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x19, 0x09);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1A, 0x15);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1B, 0x11);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1C, 0x0E);
+			break;	
+		case 2: // 378MHz MIPI_CLK for low-clock test
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x11, 0x03);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x10, 0x07);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x12, 0x04);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x13, 0x06);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x17, 0x01);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x18, 0x0B);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x15, 0x02);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x14, 0x0E);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x16, 0x04);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x19, 0x03);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1A, 0x07);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1B, 0x06);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1C, 0x05);
+			break;
+		case 1: // 594MHz MIPI_CLK for HD*4ch
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x11, 0x04);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x10, 0x0A);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x12, 0x06);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x13, 0x09);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x17, 0x01);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x18, 0x0D);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x15, 0x04);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x14, 0x16);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x16, 0x05);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x19, 0x05);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1A, 0x0A);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1B, 0x08);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1C, 0x07);
+			break;
+		default: // 756MHz MIPI_CLK
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x11, 0x05);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x10, 0x0C);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x12, 0x07);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x13, 0x0B);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x17, 0x01);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x18, 0x0E);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x15, 0x04);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x14, 0x1C);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x16, 0x07);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x19, 0x06);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1A, 0x0D);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1B, 0x0B);
+			gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1C, 0x09);
+			break;
+	}
+
+	// MIPI setting
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x44, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x49, 0xF3);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x49, 0xF0);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x44, 0x02);
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x08, 0x40);
+
+	// MIPI_TX_FRAME_CNT_EN
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x0F, 0x01);
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x38, mipi_dtype);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x39, mipi_dtype);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x3A, mipi_dtype);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x3B, mipi_dtype);
+
+	// MIPI Enable
+	if(2 == jaguar1_lane)
+	{
+		gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x07, 0x07);  //two lanes test
+		gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x2D, 0x00);
+		printk("NOTE >>> 2 lanes mode enabled\n");
+	}
+	else
+	{
+		gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x07, 0x0F);
+		gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x2D, 0x01);
+	}
+	
+	printk("[DRV]VDEC_MIPI_TX_INIT done\n");
+}
+
+void disable_parallel(int dev_num)
+{
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xFF, 0x01);
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xC8, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xC9, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xCA, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xCB, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xCC, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xCD, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xCE, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xCF, 0x00);
+
+	printk("[DRV]Parallel block Disable\n");
+}
+

drivers/media/i2c/jaguar1_drv/jaguar1_mipi.h

@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/********************************************************************************
+ *
+ *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
+ *  Module		: Jaguar1 Device Driver
+ *  Description	: MIPI
+ *  Author		:
+ *  Date         :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History      :
+ *
+ *
+ ********************************************************************************/
+#ifndef _JAGUAR1_CLOCK_
+#define _JAGUAR1_CLOCK_
+
+#include "jaguar1_video.h"
+
+#define VD_DATA_TYPE_YUV422         (0x01)
+#define VD_DATA_TYPE_YUV420         (0x02)
+#define VD_DATA_TYPE_LEGACY420      (0x03)
+
+typedef struct _mipi_vdfmt_set_s{
+	unsigned char arb_scale;
+	unsigned char mipi_frame_opt;
+}mipi_vdfmt_set_s;
+
+extern unsigned int jaguar1_mclk;
+extern unsigned int jaguar1_lane;
+
+void arb_init(int dev_num);
+void arb_enable(int dev_num);
+void arb_disable(int dev_num);
+int mipi_datatype_set(unsigned char data_type);
+void mipi_tx_init(int dev_num);
+void mipi_video_format_set(video_input_init *dev_ch_info);
+void disable_parallel(int dev_num);
+
+#endif

drivers/media/i2c/jaguar1_drv/jaguar1_mipi_table.h

@@ -0,0 +1,315 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/********************************************************************************
+ *
+ *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
+ *  Module		: Jaguar1 Device Driver
+ *  Description	: arb_mipi_table.h
+ *  Author		:
+ *  Date         :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History      :
+ *
+ *
+ ********************************************************************************/
+#ifndef _ARB_MIPI_TABLE_H_
+#define _ARB_MIPI_TABLE_H_
+
+#include "jaguar1_common.h"
+
+/* -----------------------------------------------------------------------------
+ * arb_scale(20x01)                  : SD=2(1/4), HD=1(1/2), FHD=0(bypass)
+ * mipi_frame_opt(21x3E, 21x3F)      : SD only [TBD]
+ *-----------------------------------------------------------------------------*/
+
+
+mipi_vdfmt_set_s decoder_mipi_fmtdef[ NC_VIVO_CH_FORMATDEF_MAX ] =
+{
+	[ AHD20_SD_H960_2EX_Btype_NT ] = {
+		.arb_scale = 0x02,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_SD_H960_2EX_Btype_PAL ] = {
+		.arb_scale = 0x02,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_SD_SH720_NT] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_SD_SH720_PAL] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_SD_H960_NT ] = {
+		.arb_scale = 0x02,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_SD_H960_PAL ] = {
+		.arb_scale = 0x02,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_SD_H1280_NT ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_SD_H1280_PAL ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_SD_H1440_NT ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_SD_H1440_PAL ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_SD_H960_EX_NT ] = {
+		.arb_scale = 0x02,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_SD_H960_EX_PAL ] = {
+		.arb_scale = 0x02,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_SD_H960_2EX_NT ] = {
+		.arb_scale = 0x02,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_SD_H960_2EX_PAL ] = {
+		.arb_scale = 0x02,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_1080P_30P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_1080P_25P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_720P_60P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_720P_50P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_720P_30P ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_720P_25P ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_720P_30P_EX ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_720P_25P_EX ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_720P_30P_EX_Btype ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_720P_25P_EX_Btype ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_720P_960P_30P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD20_720P_960P_25P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_3M_30P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_3M_25P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_3M_18P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_4M_30P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_4M_25P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_4M_15P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_5M_20P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_5M_12_5P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_5_3M_20P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_6M_18P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_6M_20P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_8M_X_30P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_8M_X_25P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_8M_7_5P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_8M_12_5P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ AHD30_8M_15P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+
+	/* TVI */
+	[ TVI_FHD_30P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_FHD_25P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_HD_60P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_HD_50P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_HD_30P ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_HD_25P ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_HD_30P_EX ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_HD_25P_EX ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_HD_B_30P ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_HD_B_25P ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_HD_B_30P_EX ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_HD_B_25P_EX ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_3M_18P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_5M_12_5P  ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_4M_30P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ TVI_4M_25P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+
+	/* CVI */
+	[ CVI_FHD_30P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ CVI_FHD_25P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ CVI_HD_60P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ CVI_HD_50P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ CVI_HD_30P ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ CVI_HD_25P ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ CVI_HD_30P_EX ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ CVI_HD_25P_EX ] = {
+		.arb_scale = 0x01,
+		.mipi_frame_opt = 0x00,
+	},
+	[ CVI_4M_30P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ CVI_4M_25P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ CVI_8M_12_5P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+	[ CVI_8M_15P ] = {
+		.arb_scale = 0x00,
+		.mipi_frame_opt = 0x00,
+	},
+};
+
+#endif /* VIDEO_DECODER_JAGUAR1_DRV_ARB_MIPI_TABLE_H_ */

drivers/media/i2c/jaguar1_drv/jaguar1_motion.c

@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: GPL-2.0
+/********************************************************************************
+ *
+ *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
+ *  Module		: motion.c
+ *  Description	:
+ *  Author		:
+ *  Date         :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History      :
+ *
+ *
+ ********************************************************************************/
+#include <linux/string.h>
+#include <linux/delay.h>
+#include "jaguar1_common.h"
+#include "jaguar1_motion.h"
+
+/**************************************************************************************
+ * @desc
+ * 	JAGUAR1's
+ *
+ * @param_in		(motion_mode *)p_param->channel                  FW Update channel
+ *
+ * @return   	void  		       								 None
+ *
+ * ioctl : IOC_VDEC_MOTION_SET
+ ***************************************************************************************/
+
+void motion_detection_get(motion_mode *motion_set)
+{
+	//BANK2_MOTION
+	unsigned char ReadVal = 0;
+	unsigned char ch_mask = 1;
+	unsigned char ch = motion_set->ch;
+	unsigned char ret = 0;
+
+	ch_mask = ch_mask<<ch;
+
+	gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0xFF, 0x00);
+	ReadVal = gpio_i2c_read(jaguar1_i2c_addr[motion_set->devnum], 0xA1);
+
+	ret = ReadVal&ch_mask;
+	motion_set->set_val = ret;
+
+	//	printk("motion_detection_get:: %x\n", motion_set->set_val);
+
+}
+
+void motion_onoff_set(motion_mode *motion_set)
+{
+	//BANK2_MOTION
+	gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0xFF, 0x04);
+
+	if(motion_set->fmtdef == TVI_3M_18P || motion_set->fmtdef == TVI_5M_12_5P || motion_set->fmtdef == TVI_5M_12_5P/*TVI_5M_20P*/)
+	{
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x00 + (0x07 * motion_set->ch), 0x0C);
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x02 + (0x07 * motion_set->ch), 0x23);
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x28 + (0x06 * motion_set->ch), 0x11);
+
+		if(motion_set->fmtdef == TVI_3M_18P)
+		{
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x29 + (0x06 * motion_set->ch), 0x78);
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2A + (0x06 * motion_set->ch), 0x40);
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2C + (0x06 * motion_set->ch), 0x72);
+		}
+		else if(motion_set->fmtdef == TVI_5M_12_5P)
+		{
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x29 + (0x06 * motion_set->ch), 0xA2);
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2A + (0x06 * motion_set->ch), 0x51);
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2C + (0x06 * motion_set->ch), 0x96);
+		}
+
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2B + (0x06 * motion_set->ch), 0x6);
+
+		printk("[DRV_Motion_OnOff] ch(%d) fmtdef(%d)\n", motion_set->ch, motion_set->fmtdef);
+	}
+	else
+	{
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x28 + (0x06 * motion_set->ch), 0x00);
+	}
+
+	if(motion_set->set_val<0 || motion_set->set_val>1)
+	{
+		printk("[DRV_Motion_OnOff]Error!! ch(%d) Setting Value Over:%x!! Only 0 or 1\n", motion_set->ch, motion_set->set_val);
+		return;
+	}
+
+	switch(motion_set->set_val)
+	{
+		case FUNC_OFF : gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], (0x00 + (0x07 * motion_set->ch)), 0x0D);
+						gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x28 + (0x06 * motion_set->ch), 0x00);
+						break;
+		case FUNC_ON : gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], (0x00 + (0x07 * motion_set->ch)), 0x0C);
+					   break;
+	}
+
+
+}
+
+void motion_pixel_all_onoff_set(motion_mode *motion_set)
+{
+	int ii=0;
+	unsigned char addr = 0;
+
+	//BANK2_MOTION
+	gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0xFF, 0x04);
+
+	if(motion_set->fmtdef == TVI_3M_18P || motion_set->fmtdef == TVI_5M_12_5P || motion_set->fmtdef == TVI_5M_12_5P/*TVI_5M_20P*/)
+	{
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x00 + (0x07 * motion_set->ch), 0x0C);
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x02 + (0x07 * motion_set->ch), 0x23);
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x28 + (0x06 * motion_set->ch), 0x11);
+
+		if(motion_set->fmtdef == TVI_3M_18P)
+		{
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x29 + (0x06 * motion_set->ch), 0x78);
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2A + (0x06 * motion_set->ch), 0x40);
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2C + (0x06 * motion_set->ch), 0x72);
+		}
+		else if(motion_set->fmtdef == TVI_5M_12_5P)
+		{
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x29 + (0x06 * motion_set->ch), 0xA2);
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2A + (0x06 * motion_set->ch), 0x51);
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2C + (0x06 * motion_set->ch), 0x96);
+		}
+
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2B + (0x06 * motion_set->ch), 0x6);
+
+		printk("[DRV_Motion_OnOff] ch(%d) fmtdef(%d)\n", motion_set->ch, motion_set->fmtdef);
+	}
+	else
+	{
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x28 + (0x06 * motion_set->ch), 0x00);
+	}
+
+	for(ii=0; ii<24; ii++)
+	{
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], (0x40 +(0x18 *motion_set->ch)) + ii, motion_set->set_val);
+		addr = (0x40 +(0x18 *motion_set->ch)) + ii;
+	}
+}
+
+void motion_pixel_onoff_set(motion_mode *motion_set)
+{
+	unsigned char val = 0x80;
+	unsigned char ReadVal;
+	unsigned char on;
+
+	unsigned char ch      = motion_set->ch;
+	unsigned char SetPix  = motion_set->set_val/8;
+	unsigned char SetVal  = motion_set->set_val%8;
+
+	val = val >> SetVal;
+
+	//BANK2_MOTION
+	gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0xFF, 0x04);
+
+	if(motion_set->fmtdef == TVI_3M_18P || motion_set->fmtdef == TVI_5M_12_5P || motion_set->fmtdef == TVI_5M_12_5P/*TVI_5M_20P*/)
+	{
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x00 + (0x07 * motion_set->ch), 0x0C);
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x02 + (0x07 * motion_set->ch), 0x23);
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x28 + (0x06 * motion_set->ch), 0x11);
+
+		if(motion_set->fmtdef == TVI_3M_18P)
+		{
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x29 + (0x06 * motion_set->ch), 0x78);
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2A + (0x06 * motion_set->ch), 0x40);
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2C + (0x06 * motion_set->ch), 0x72);
+		}
+		else if(motion_set->fmtdef == TVI_5M_12_5P)
+		{
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x29 + (0x06 * motion_set->ch), 0xA2);
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2A + (0x06 * motion_set->ch), 0x51);
+			gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2C + (0x06 * motion_set->ch), 0x96);
+		}
+
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x2B + (0x06 * motion_set->ch), 0x6);
+
+		printk("[DRV_Motion_OnOff] ch(%d) fmtdef(%d)\n", motion_set->ch, motion_set->fmtdef);
+	}
+	else
+	{
+		gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0x28 + (0x06 * motion_set->ch), 0x00);
+	}
+
+	ReadVal = gpio_i2c_read(jaguar1_i2c_addr[motion_set->devnum], (0x40 +(0x18 *ch)) + SetPix);
+	on = val&ReadVal;
+	if(on)
+	{
+		val = ~val;
+		val = val&ReadVal;
+	}
+	else
+	{
+		val = val|ReadVal;
+	}
+	gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], (0x40 +(0x18 *ch)) + SetPix, val);
+}
+
+void motion_pixel_onoff_get(motion_mode *motion_set)
+{
+	unsigned char val = 0x80;
+	unsigned char ReadVal;
+	unsigned char on;
+
+	unsigned char Ch      = motion_set->ch;
+	unsigned char SetPix  = motion_set->set_val/8;
+	unsigned char SetVal  = motion_set->set_val%8;
+
+	val = val >> SetVal;
+
+	//BANK2_MOTION
+	gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0xFF, 0x04);
+	ReadVal = gpio_i2c_read(jaguar1_i2c_addr[motion_set->devnum], (0x40 +(0x18 *Ch)) + SetPix);
+
+	on = val&ReadVal;
+
+	if(on)
+	{
+		motion_set->set_val = 1;
+	}
+	else
+	{
+		motion_set->set_val = 0;
+	}
+}
+
+void motion_tsen_set(motion_mode *motion_set)
+{
+	unsigned char ch = motion_set->ch;
+	unsigned char SetVal = motion_set->set_val;
+
+	//BANK2_MOTION
+	gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0xFF, 0x04);
+	gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], (0x01 +(0x07 * ch)), SetVal);
+	printk("[DRV_Motion]ch(%d), TSEN Val(%x)\n", ch, SetVal);
+}
+
+void motion_psen_set(motion_mode *motion_set)
+{
+	unsigned char msb_mask = 0xf0;
+	unsigned char lsb_mask = 0x07;
+	unsigned char ch = motion_set->ch;
+	unsigned char SetVal = motion_set->set_val;
+	unsigned char ReadVal;
+
+	//BANK2_MOTION
+	gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], 0xFF, 0x04);
+	ReadVal = gpio_i2c_read(jaguar1_i2c_addr[motion_set->devnum], (0x02 +(0x07 * ch)));
+
+	msb_mask = msb_mask&ReadVal;
+	SetVal = lsb_mask&SetVal;
+
+	SetVal = SetVal|msb_mask;
+
+	gpio_i2c_write(jaguar1_i2c_addr[motion_set->devnum], (0x02 +(0x07 * ch)), SetVal);
+	printk("[DRV_Motion]ch(%d), readVal(%x), SetVal(%x)\n", ch, ReadVal, SetVal);
+}
+

drivers/media/i2c/jaguar1_drv/jaguar1_motion.h

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/********************************************************************************
+ *
+ *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
+ *  Module		: motion.h
+ *  Description	:
+ *  Author		:
+ *  Date         :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History      :
+ *
+ *
+ ********************************************************************************/
+#ifndef _MOTION_H_
+#define _MOTION_H_
+
+#include "jaguar1_common.h"
+
+typedef struct _motion_mode{
+	unsigned char ch;
+	unsigned char devnum;
+	unsigned char set_val;
+
+	unsigned char fmtdef;
+}motion_mode;
+
+void motion_onoff_set(motion_mode *motion_set);
+void motion_display_onoff_set(motion_mode *motion_set);
+void motion_pixel_all_onoff_set(motion_mode *motion_set);
+void motion_pixel_onoff_set(motion_mode *motion_set);
+void motion_pixel_onoff_get(motion_mode *motion_set);
+void motion_tsen_set(motion_mode *motion_set);
+void motion_psen_set(motion_mode *motion_set);
+void motion_detection_get(motion_mode *motion_set);
+
+#endif /* _MOTION_H_ */

drivers/media/i2c/jaguar1_drv/jaguar1_reg_set_def.h

@@ -0,0 +1,268 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/********************************************************************************
+ *
+ *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
+ *  Module		: Jaguar1 Device Driver
+ *  Description	: coax_table.h
+ *  Author		:
+ *  Date         :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History      :
+ *
+ *
+ ********************************************************************************/
+#ifndef _JAGUAR1_REGISTER_SET_DEFINE_
+#define _JAGUAR1_REGISTER_SET_DEFINE_
+
+#include "jaguar1_video.h"
+
+
+/*=================================================================================================
+ *
+ * REG_SET_BANKxADDR_StartBit_Size_RegName( Channel, Setting Value )
+ *
+ *=================================================================================================*/
+
+
+// vd_jaguar1_init_set
+#define REG_SET_0x00_0_8_EACH_SET(ch, val) vd_register_set ( 0 , 0x00 , 0x00 + ch , val , 0 , 8 )
+
+// vd_jaguar1_single_differ_set
+#define REG_SET_0x18_0_8_EX_CBAR_ON(ch, val) vd_register_set ( 0 , 0x00 , 0x18 + ch , val , 0 , 8 )
+#define REG_SET_5x00_0_8_CMP(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x00 , val , 0 , 8 )
+#define REG_SET_5x01_0_8_CML(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x01 , val , 0 , 8 )
+#define REG_SET_5x1D_0_8_AFE(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x1d , val , 0 , 8 )
+#define REG_SET_5x92_0_8_PWM(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x92 , val , 0 , 8 )
+
+// vd_vo_port_y_c_merge_set
+#define REG_SET_1xEC_0_8_yc_merge(ch, val) vd_register_set ( 0 , 0x01 , 0xec + ch , val , 0 , 8 )
+
+// vd_vo_mux_mode_set
+#define REG_SET_1xC8_0_8_out_sel(ch, val) vd_register_set ( 0 , 0x01 , 0xc8 + ch , val , 0 , 8 )
+
+// vd_vo_manual_mode_set
+
+
+// vd_vi_manual_set_seq1
+#define REG_SET_1x7C_0_1_clk_auto_1(ch, val) vd_register_set ( 0 , 0x01 , 0x7c , val , 0 , 1 )
+#define REG_SET_1x7C_1_1_clk_auto_2(ch, val) vd_register_set ( 0 , 0x01 , 0x7c , val , 1 , 1 )
+#define REG_SET_1x7C_2_1_clk_auto_3(ch, val) vd_register_set ( 0 , 0x01 , 0x7c , val , 2 , 1 )
+#define REG_SET_1x7C_3_1_clk_auto_4(ch, val) vd_register_set ( 0 , 0x01 , 0x7c , val , 3 , 1 )
+
+#define REG_SET_5x32_0_8_NOVIDEO_DET_A(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x32 , val , 0 , 8 )
+#define REG_SET_5xB9_0_8_HAFC_LPF_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0xb9 , val , 0 , 8 )
+#define REG_SET_9x44_0_8_FSC_EXT_EN(ch, val) vd_register_set ( 0 , 0x09 , 0x44 + ch , val , 0 , 8 )
+#define REG_SET_5x6E_0_8_VBLK_END_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x6e , val , 0 , 8 )
+#define REG_SET_5x6F_0_8_VBLK_END_EXT(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x6f , val , 0 , 8 )
+
+// afe_reg
+#define REG_SET_5x00_0_8_A_CMP_PW_MODE(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x00 , val , 0 , 8 )
+#define REG_SET_5x02_0_8_A_CMP_TIMEUNIT(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x02 , val , 0 , 8 )
+#define REG_SET_5x1E_0_8_VAFEMD(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x1e , val , 0 , 8 )
+#define REG_SET_5x58_0_8_VAFE1_EQ_BAND_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x58 , val , 0 , 8 )
+#define REG_SET_5x59_0_8_LPF_BYPASS(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x59 , val , 0 , 8 )
+#define REG_SET_5x5A_0_8_VAFE_IMP_CNT(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x5a , val , 0 , 8 )
+#define REG_SET_5x5B_0_8_VAFE_DUTY(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x5b , val , 0 , 8 )
+#define REG_SET_5x5C_0_8_VAFE_B_LPF_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x5c , val , 0 , 8 )
+#define REG_SET_5x94_0_8_PWM_DELAY_H(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x94 , val , 0 , 8 )
+#define REG_SET_5x95_0_8_PWM_DELAY_L(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x95 , val , 0 , 8 )
+#define REG_SET_5x65_0_8_VAFE_CML_SPEED(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x65 , val , 0 , 8 )
+
+
+// vd_vi_format_set_seq3
+#define REG_SET_0x10_0_8_VD_FMT(ch, val) vd_register_set ( 0 , 0x00 , 0x10 + ch , val , 0 , 8 )
+#define REG_SET_0x0C_0_8_SPL_MODE(ch, val) vd_register_set ( 0 , 0x00 , 0x0c + ch , val , 0 , 8 )
+#define REG_SET_0x04_0_8_SD_MODE(ch, val) vd_register_set ( 0 , 0x00 , 0x04 + ch , val , 0 , 8 )
+#define REG_SET_0x08_0_8_AHD_MODE(ch, val) vd_register_set ( 0 , 0x00 , 0x08 + ch , val , 0 , 8 )
+#define REG_SET_5x69_0_1_SD_FREQ_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x69 , val , 0 , 1 )
+#define REG_SET_5x62_0_8_SYNC_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x62 , val , 0 , 8 )
+
+
+// vd_vi_chroma_set_seq4
+#define REG_SET_0x5C_0_8_PAL_CM_OFF(ch, val) vd_register_set ( 0 , 0x00 , 0x5c + ch , val , 0 , 8 )
+#define REG_SET_5x28_0_8_S_POINT(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x28 , val , 0 , 8 )
+#define REG_SET_5x25_0_8_FSC_LOCK_MODE(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x25 , val , 0 , 8 )
+#define REG_SET_5x90_0_8_COMB_MODE(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x90 , val , 0 , 8 )
+
+
+// vd_vi_h_timing_set_seq5
+#define REG_SET_0x68_0_8_H_DLY_LSB(ch, val) vd_register_set ( 0 , 0x00 , 0x68 + ch , val , 0 , 8 )
+#define REG_SET_0x6c_0_8_H_DLY_MSB(ch, val) vd_register_set ( 0 , 0x00 , 0x6c + ch , val , 0 , 8 )
+#define REG_SET_0x60_0_8_Y_DLY(ch, val) vd_register_set ( 0 , 0x00 , 0x60 + ch , val , 0 , 8 )
+#define REG_SET_0x78_0_8_V_BLK_END_A(ch, val) vd_register_set ( 0 , 0x00 , 0x78 + ch , val , 0 , 8 )
+#define REG_SET_5x38_4_1_H_MASK_ON(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x38 , val , 4 , 1 )
+#define REG_SET_5x38_0_4_H_MASK_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x38 , val , 0 , 4 )
+#define REG_SET_0x64_0_8_V_BLK_END_B(ch, val) vd_register_set ( 0 , 0x00 , 0x64 + ch , val , 0 , 8 )
+#define REG_SET_0x14_4_1_FLD_INV(ch, val) vd_register_set ( 0 , 0x00 , 0x14 + ch , val , 4 , 1 )
+#define REG_SET_5x64_0_8_MEM_RDP(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x64 , val , 0 , 8 )
+#define REG_SET_5x47_0_8_SYNC_RS(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x47 , val , 0 , 8 )
+#define REG_SET_5xA9_0_8_V_BLK_END_B(ch, val) vd_register_set ( 0 , 0x05 + ch , 0xa9 , val , 0 , 8 )
+
+
+// vd_vi_h_scaler_mode_set_seq6
+#define REG_SET_5x53_2_2_LINEMEM_MD(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x53 , val , 2 , 2 )
+#define REG_SET_9x96_0_8_H_DOWN_SCALER(ch, val) vd_register_set ( 0 , 0x09 , 0x96 + (0x20 * ch) , val , 0 , 8 )
+#define REG_SET_9x97_0_8_H_SCALER_MODE(ch, val) vd_register_set ( 0 , 0x09 , 0x97 + (0x20 * ch) , val , 0 , 8 )
+#define REG_SET_9x98_0_8_REF_BASE_LSB(ch, val) vd_register_set ( 0 , 0x09 , 0x98 + (0x20 * ch) , val , 0 , 8 )
+#define REG_SET_9x99_0_8_REF_BASE_MSB(ch, val) vd_register_set ( 0 , 0x09 , 0x99 + (0x20 * ch) , val , 0 , 8 )
+#define REG_SET_9x9E_0_8_H_SCALER_OUTPUT_H_ACTIVE(ch, val) vd_register_set ( 0 , 0x09 , 0x9e + (0x20 * ch) , val , 0 , 8 )
+
+
+//vd_vi_hpll_set_seq7
+#define REG_SET_5x50_0_8_HPLL_MASK_ON(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x50 , val , 0 , 8 )
+#define REG_SET_5xB8_0_8_HAFC_OP_MD(ch, val) vd_register_set ( 0 , 0x05 + ch , 0xb8 , val , 0 , 8 )
+#define REG_SET_5xBB_0_8_HAFC_BYP_TH_E(ch, val) vd_register_set ( 0 , 0x05 + ch , 0xbb , val , 0 , 8 )
+#define REG_SET_5xB7_0_8_HAFC_BYP_TH_S(ch, val) vd_register_set ( 0 , 0x05 + ch , 0xb7 , val , 0 , 8 )
+
+// vd_vi_color_set_seq8
+#define REG_SET_0x20_0_8_BRIGHTNESS(ch, val) vd_register_set ( 0 , 0x00 , 0x20 + ch , val , 0 , 8 )
+#define REG_SET_0x24_0_8_CONTARST(ch, val) vd_register_set ( 0 , 0x00 , 0x24 + ch , val , 0 , 8 )
+#define REG_SET_0x28_0_8_BLACK_LEVEL(ch, val) vd_register_set ( 0 , 0x00 , 0x28 + ch , val , 0 , 8 )
+#define REG_SET_0x58_0_8_SATURATION_A(ch, val) vd_register_set ( 0 , 0x00 , 0x58 + ch , val , 0 , 8 )
+#define REG_SET_0x40_0_8_HUE(ch, val) vd_register_set ( 0 , 0x00 , 0x40 + ch , val , 0 , 8 )
+#define REG_SET_0x44_0_8_U_GAIN(ch, val) vd_register_set ( 0 , 0x00 , 0x44 + ch , val , 0 , 8 )
+#define REG_SET_0x48_0_8_V_GAIN(ch, val) vd_register_set ( 0 , 0x00 , 0x48 + ch , val , 0 , 8 )
+#define REG_SET_0x4C_0_8_U_OFFSET(ch, val) vd_register_set ( 0 , 0x00 , 0x4c + ch , val , 0 , 8 )
+#define REG_SET_0x50_0_8_V_OFFSET(ch, val) vd_register_set ( 0 , 0x00 , 0x50 + ch , val , 0 , 8 )
+#define REG_SET_5x2B_0_8_SATURATION_B(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x2b , val , 0 , 8 )
+#define REG_SET_5x24_0_8_BURSET_DEC_A(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x24 , val , 0 , 8 )
+#define REG_SET_5x5F_0_8_BURSET_DEC_B(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x5f , val , 0 , 8 )
+#define REG_SET_5xD1_0_8_BURSET_DEC_C(ch, val) vd_register_set ( 0 , 0x05 + ch , 0xd1 , val , 0 , 8 )
+#define REG_SET_9x44_0_8_FSC_EXT_EN(ch, val) vd_register_set ( 0 , 0x09 , 0x44 + ch , val , 0 , 8 )
+#define REG_SET_9x50_0_8_FSC_EXT_VAL_7_0(ch, val) vd_register_set ( 0 , 0x09 , 0x50 + (ch*4) , val , 0 , 8 )
+#define REG_SET_9x51_0_8_FSC_EXT_VAL_15_8(ch, val) vd_register_set ( 0 , 0x09 , 0x51 + (ch*4) , val , 0 , 8 )
+#define REG_SET_9x52_0_8_FSC_EXT_VAL_23_16(ch, val) vd_register_set ( 0 , 0x09 , 0x52 + (ch*4) , val , 0 , 8 )
+#define REG_SET_9x53_0_8_FSC_EXT_VAL_31_24(ch, val) vd_register_set ( 0 , 0x09 , 0x53 + (ch*4) , val , 0 , 8 )
+#define REG_SET_5x26_0_8_FSC_LOCK_SENSE(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x26 , val , 0 , 8 )
+#define REG_SET_5xB8_0_8_HPLL_MASK_END(ch, val) vd_register_set ( 0 , 0x05 + ch , 0xb8 , val , 0 , 8 )
+#define REG_SET_9x40_0_8_FSC_DET_MODE(ch, val) vd_register_set ( 0 , 0x09 , 0x40 + ch , val , 0 , 8 )
+
+// vd_vi_clock_set_seq9
+#define REG_SET_1x84_0_8_CLK_ADC(ch, val) vd_register_set ( 0 , 0x01 , 0x84 + ch , val , 0 , 8 )
+#define REG_SET_1x88_0_8_CLK_PRE(ch, val) vd_register_set ( 0 , 0x01 , 0x88 + ch , val , 0 , 8 )
+#define REG_SET_1x8c_0_8_CLK_POST(ch, val) vd_register_set ( 0 , 0x01 , 0x8c + ch , val , 0 , 8 )
+
+#define REG_SET_5x01_0_8_CML_MODE(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x01 , val , 0 , 8 )
+#define REG_SET_5x05_0_8_AGC_OP(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x05 , val , 0 , 8 )
+#define REG_SET_5x1D_0_8_G_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x1D , val , 0 , 8 )
+
+
+// vd_jaguar1_sw_reset
+#define REG_SET_1x81_0_1_VPLL_RST(ch, val) vd_register_set ( 0 , 0x01 , 0x81 , val , 0 , 1 )
+#define REG_SET_1x80_0_1_VPLL_C(ch, val) vd_register_set ( 0 , 0x01 , 0x80 , val , 0 , 1 )
+
+
+// __eq_base_set_value
+#define REG_SET_5x65_0_8_EQ_BYPASS(ch, val) vd_register_set (   0, 0x05 + ch, 0x65 , val, 0, 8 )
+#define REG_SET_5x58_0_8_EQ_BAND_SEL(ch, val) vd_register_set ( 0, 0x05 + ch, 0x58 , val, 0, 8 )
+#define REG_SET_5x5C_0_8_EQ_GAIN_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x5c , val , 0 , 8 )
+#define REG_SET_Ax3D_0_8_EQ_DEQ_A_ON(ch, val) vd_register_set ( 0, 0x0a + ((ch%4)/2), 0x3d + (ch%2 * 0x80), val, 0 , 8 )
+#define REG_SET_Ax3C_0_8_EQ_DEQ_A_SEL(ch, val) vd_register_set ( 0 , 0x0a + ((ch%4)/2) , 0x3c + (ch%2 * 0x80), val , 0 , 8 )
+#define REG_SET_9x80_0_8_EQ_DEQ_B_SEL(ch, val) vd_register_set ( 0 , 0x09 , 0x80 + (ch * 0x20) , val , 0 , 8 )
+
+
+// __eq_coeff_set_value
+#define REG_SET_Ax30_0_8_EQ_DEQ_A_01(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x30 + (ch%2 * 0x80) , val , 0 , 8 )
+#define REG_SET_Ax31_0_8_EQ_DEQ_A_02(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x31 + (ch%2 * 0x80) , val , 0 , 8 )
+#define REG_SET_Ax32_0_8_EQ_DEQ_A_03(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x32 + (ch%2 * 0x80) , val , 0 , 8 )
+#define REG_SET_Ax33_0_8_EQ_DEQ_A_04(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x33 + (ch%2 * 0x80) , val , 0 , 8 )
+#define REG_SET_Ax34_0_8_EQ_DEQ_A_05(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x34 + (ch%2 * 0x80) , val , 0 , 8 )
+#define REG_SET_Ax35_0_8_EQ_DEQ_A_06(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x35 + (ch%2 * 0x80) , val , 0 , 8 )
+#define REG_SET_Ax36_0_8_EQ_DEQ_A_07(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x36 + (ch%2 * 0x80) , val , 0 , 8 )
+#define REG_SET_Ax37_0_8_EQ_DEQ_A_08(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x37 + (ch%2 * 0x80) , val , 0 , 8 )
+#define REG_SET_Ax38_0_8_EQ_DEQ_A_09(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x38 + (ch%2 * 0x80) , val , 0 , 8 )
+#define REG_SET_Ax39_0_8_EQ_DEQ_A_10(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x39 + (ch%2 * 0x80) , val , 0 , 8 )
+#define REG_SET_Ax3A_0_8_EQ_DEQ_A_11(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x3a + (ch%2 * 0x80) , val , 0 , 8 )
+#define REG_SET_Ax3B_0_8_EQ_DEQ_A_12(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x3b + (ch%2 * 0x80) , val , 0 , 8 )
+
+
+// __eq_color_set_value
+#define REG_SET_0x24_0_8_EQ_COLOR_CONTRAST(ch, val) vd_register_set( 0, 0x00 , 0x24 + ch , val , 0 , 8 )
+#define REG_SET_0x30_0_8_EQ_COLOR_H_PEAKING_1(ch, val) vd_register_set( 0, 0x00 , 0x30 + ch , val , 0 , 8 )
+#define REG_SET_0x34_0_8_EQ_COLOR_H_PEAKING_2(ch, val) vd_register_set( 0, 0x00 , 0x34 + ch , val , 0 , 8 )
+#define REG_SET_0x40_0_8_EQ_COLOR_HUE(ch, val) vd_register_set( 0, 0x00 , 0x40 + ch , val , 0 , 8 )
+#define REG_SET_0x44_0_8_EQ_COLOR_U_GAIN(ch, val) vd_register_set( 0, 0x00 , 0x44 + ch , val , 0 , 8 )
+#define REG_SET_0x48_0_8_EQ_COLOR_V_GAIN(ch, val) vd_register_set( 0, 0x00 , 0x48 + ch , val , 0 , 8 )
+#define REG_SET_0x4C_0_8_EQ_COLOR_U_OFFSET(ch, val) vd_register_set( 0, 0x00 , 0x4c + ch , val , 0 , 8 )
+#define REG_SET_0x50_0_8_EQ_COLOR_V_OFFSET(ch, val) vd_register_set( 0, 0x00 , 0x50 + ch , val , 0 , 8 )
+#define REG_SET_0x28_0_8_EQ_COLOR_BLACK_LEVEL(ch, val) vd_register_set( 0, 0x00 , 0x28 + ch , val , 0 , 8 )
+#define REG_SET_5x31_0_8_EQ_COLOR_C_FILTER(ch, val) vd_register_set( 0, 0x05 + ch , 0x31 , val , 0 , 8 )
+#define REG_SET_5x27_0_8_EQ_COLOR_ACC_REF(ch, val) vd_register_set( 0, 0x05 + ch , 0x27 , val , 0 , 8 )
+#define REG_SET_5x28_0_8_EQ_COLOR_CTI_DELAY(ch, val) vd_register_set( 0, 0x05 + ch , 0x28 , val , 0 , 8 )
+#define REG_SET_5x2b_0_8_EQ_COLOR_SUB_SATURATION(ch, val) vd_register_set( 0, 0x05 + ch , 0x2b , val , 0 , 8 )
+#define REG_SET_5x24_0_8_EQ_COLOR_BURST_DEC_A(ch, val) vd_register_set( 0, 0x05 + ch , 0x24 , val , 0 , 8 )
+#define REG_SET_5x5F_0_8_EQ_COLOR_BURST_DEC_B(ch, val) vd_register_set( 0, 0x05 + ch , 0x5f , val , 0 , 8 )
+#define REG_SET_5xD1_0_8_EQ_COLOR_BURST_DEC_C(ch, val) vd_register_set( 0, 0x05 + ch , 0xd1 , val , 0 , 8 )
+#define REG_SET_5xD5_0_8_EQ_COLOR_C_OPTION(ch, val) vd_register_set( 0, 0x05 + ch , 0xd5 , val , 0 , 8 )
+#define REG_SET_Ax25_0_8_EQ_COLOR_Y_FILTER_B(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x25 + (ch%2 * 0x80) , val , 0 , 8 )
+#define REG_SET_Ax27_0_8_EQ_COLOR_Y_FILTER_B_SEL(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x27 + (ch%2 * 0x80) , val , 0 , 8 )
+
+
+// __eq_clk_set_value
+#define REG_SET_1x84_0_8_EQ_CLOCK_ADC_CLK(ch, val) vd_register_set( 0, 0x01 , 0x84 + ch , val , 0 , 8 )
+#define REG_SET_1x88_0_8_EQ_CLOCK_PRE_CLK(ch, val) vd_register_set( 0, 0x01 , 0x88 + ch , val , 0 , 8 )
+#define REG_SET_1x8C_0_8_EQ_CLOCK_POST_CLK(ch, val) vd_register_set( 0, 0x01 , 0x8C + ch , val , 0 , 8 )
+
+
+// eq_timing_b_set_value
+#define REG_SET_9x96_0_8_EQ_TIMING_B_HSCALER_1(ch, val) vd_register_set( 0, 0x09 , 0x96 + (ch * 0x20) , val , 0 , 8 )
+#define REG_SET_9x97_0_8_EQ_TIMING_B_HSCALER_2(ch, val) vd_register_set( 0, 0x09 , 0x97 + (ch * 0x20) , val , 0 , 8 )
+#define REG_SET_9x98_0_8_EQ_TIMING_B_HSCALER_3(ch, val) vd_register_set( 0, 0x09 , 0x98 + (ch * 0x20) , val , 0 , 8 )
+#define REG_SET_9x99_0_8_EQ_TIMING_B_HSCALER_4(ch, val) vd_register_set( 0, 0x09 , 0x99 + (ch * 0x20) , val , 0 , 8 )
+#define REG_SET_9x9A_0_8_EQ_TIMING_B_HSCALER_5(ch, val) vd_register_set( 0, 0x09 , 0x9a + (ch * 0x20) , val , 0 , 8 )
+#define REG_SET_9x9B_0_8_EQ_TIMING_B_HSCALER_6(ch, val) vd_register_set( 0, 0x09 , 0x9b + (ch * 0x20) , val , 0 , 8 )
+#define REG_SET_9x9C_0_8_EQ_TIMING_B_HSCALER_7(ch, val) vd_register_set( 0, 0x09 , 0x9c + (ch * 0x20) , val , 0 , 8 )
+#define REG_SET_9x9D_0_8_EQ_TIMING_B_HSCALER_8(ch, val) vd_register_set( 0, 0x09 , 0x9d + (ch * 0x20) , val , 0 , 8 )
+#define REG_SET_9x9E_0_8_EQ_TIMING_B_HSCALER_9(ch, val) vd_register_set( 0, 0x09 , 0x9e + (ch * 0x20) , val , 0 , 8 )
+#define REG_SET_9x40_0_8_EQ_TIMING_B_PN_AUTO(ch, val) vd_register_set( 0, 0x09 , 0x40 + ch , val , 0 , 8 )
+#define REG_SET_5x90_0_8_EQ_TIMINING_B_COMB_MODE(ch, val) vd_register_set( 0, 0x05 + ch , 0x90 , val , 0 , 8 )
+#define REG_SET_5xB9_0_8_EQ_TIMING_B_HPLL_OP_A(ch, val) vd_register_set( 0, 0x05 + ch , 0xb9 , val , 0 , 8 )
+#define REG_SET_5x57_0_8_EQ_TIMING_B_MEM_PATH(ch, val) vd_register_set( 0, 0x05 + ch , 0x57 , val , 0 , 8 )
+#define REG_SET_5x25_0_8_EQ_TIMING_B_FSC_LOCK_SPD(ch, val) vd_register_set( 0, 0x05 + ch , 0x25 , val , 0 , 8 )
+#define REG_SET_0x04_0_8_EQ_TIMING_B_SD_MD(ch, val) vd_register_set( 0, 0x00 , 0x04 + ch , val , 0 , 8 )
+#define REG_SET_0x08_0_8_EQ_TIMING_B_AHD_MD(ch, val) vd_register_set( 0, 0x00 , 0x08 + ch , val , 0 , 8 )
+#define REG_SET_0x0C_0_8_EQ_TIMING_B_SPECIAL_MD(ch, val) vd_register_set( 0, 0x00 , 0x0c + ch , val , 0 , 8 )
+#define REG_SET_0x78_0_8_EQ_TIMING_B_VBLK_END(ch, val) vd_register_set( 0, 0x00 , 0x78 + ch , val , 0 , 8 )
+
+
+#define REG_SET_5x53_2_2_EQ_SD_LINE_MEM_MD(ch, val) vd_register_set( 0, 0x05 + ch , 0x53 , val , 2 , 2 )
+#define REG_SET_0x14_4_1_EQ_SD_FLD_INV(ch, val) vd_register_set( 0, 0x00 , 0x14 + ch , val , 4 , 1 )
+#define REG_SET_5x2F_7_1_EQ_SD_AUTO(ch, val) vd_register_set( 0, 0x05 + ch , 0x2f , val , 7 , 1 )
+#define REG_SET_0x10_0_8_EQ_VIDEO_FORMAT(ch, val) vd_register_set( 0, 0x00 , 0x10 + ch , val , 0 , 8 )
+#define REG_SET_5x64_0_8_EQ_MEM_RDP(ch, val) vd_register_set( 0, 0x05 + ch , 0x64 + ch , val , 0 , 8 )
+#define REG_SET_5x69_0_1_EQ_SD_FREQ_SEL(ch, val) vd_register_set( 0, 0x05 + ch , 0x69 , val , 0 , 1 )
+
+#define REG_SET_0x68_0_8_EQ_TIMING_A_H_DELAY_A(ch, val) vd_register_set( 0, 0x00 , 0x68 + ch , val , 0 , 8 )
+#define REG_SET_5x38_0_8_EQ_TIMING_A_H_DELAY_B(ch, val) vd_register_set( 0, 0x05 + ch , 0x38 , val , 0 , 8 )
+#define REG_SET_0x6C_0_4_EQ_TIMING_A_H_DELAY_C(ch, val) vd_register_set( 0, 0x00 , 0x6C + ch , val , 0 , 4 )
+#define REG_SET_0x64_0_8_EQ_TIMING_A_Y_DELAY(ch, val) vd_register_set( 0, 0x00 , 0x64 + ch , val , 0 , 8 )
+
+// ADD
+#define REG_SET_0x7C_0_8_HZOOM(ch, val) vd_register_set( 0, 0x00 , 0x7c + ch , val , 0 , 8 )
+#define REG_SET_5x31_0_8_EQ_C_FILTER(ch, val) vd_register_set( 0, 0x05 + ch , 0x31 , val , 0 , 8 )
+#define REG_SET_0x5c_0_8_EQ_PAL_CM_OFF(ch, val) vd_register_set( 0, 0x00 , 0x5c + ch , val , 0 , 8 )
+
+#define REG_SET_5x1D_0_8_EQ_AFE_G_SEL(ch, val) vd_register_set( 0, 0x05 + ch , 0x1d , val , 0 , 8 )
+#define REG_SET_5x01_0_8_EQ_AFE_CTR_CLP(ch, val) vd_register_set( 0, 0x05 + ch , 0x01 , val , 0 , 8 )
+#define REG_SET_5x05_0_8_EQ_D_AGC_OPTION(ch, val) vd_register_set( 0, 0x05 + ch , 0x05 , val , 0 , 8 )
+
+#define REG_SET_0x70_0_8_V_DELAY(ch, val) vd_register_set( 0, 0x00 , 0x70 + ch , val , 0 , 8 )
+
+#define REG_SET_0x14_0_8_FLD_INV_CHID(ch, val) vd_register_set( 0, 0x00, 0x14 + ch, val + ch, 0, 8)
+#define REG_SET_0x34_0_8_Y_FIR_MODE(ch, val) vd_register_set( 0, 0x00, 0x34 + ch, val, 0, 8)
+#define REG_SET_1xA0_0_8_TM_CLK_EN_SET(ch, val) vd_register_set( 0, 0x01, 0xA0 + ch, val, 0, 8 )
+#define REG_SET_1xCC_0_8_VPORT_OCLK_SEL_VPORT_OVCLK_DLY_SEL(ch, val) vd_register_set( 0, 0x01, 0xCC + ch, val, 0, 8 )
+#define REG_SET_5x21_0_8_CONT_SUB(ch, val) vd_register_set( 0, 0x05 + ch, 0x21, val, 0, 8 )
+#define REG_SET_5x55_0_8_C_MEM_CLK_SEL(ch, val) vd_register_set( 0, 0x05 + ch, 0x55, val, 0, 8 )
+#define REG_SET_5x56_0_8_FREQ_MEM_CLK_SEL(ch, val) vd_register_set( 0, 0x05 + ch, 0x56, val, 0, 8 )
+#define REG_SET_5x57_0_8_LINE_MEM_CLK_INV(ch, val) vd_register_set( 0, 0x05 + ch, 0x57, val, 0, 8 )
+#define REG_SET_5xB5_0_8_HAFC_MASK_SEL(ch, val) vd_register_set( 0, 0x05 + ch, 0xB5, val, 0, 8)
+#define REG_SET_5xB8_0_8_HAFC_HCOEFF_SEL(ch, val) vd_register_set( 0, 0x05 + ch, 0xB8, val, 0, 8)
+
+/********************************************************************
+ *  End of file
+ ********************************************************************/
+
+#endif

drivers/media/i2c/jaguar1_drv/jaguar1_v4l2.c

@@ -0,0 +1,959 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * jaguar1 driver
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <linux/sysfs.h>
+#include <media/media-entity.h>
+#include <media/v4l2-async.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-fwnode.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
+#include <linux/mfd/syscon.h>
+#include <linux/version.h>
+#include <linux/rk-camera-module.h>
+#include <linux/rk-preisp.h>
+
+#include "jaguar1_common.h"
+#include "jaguar1_video.h"
+#include "jaguar1_coax_protocol.h"
+#include "jaguar1_motion.h"
+#include "jaguar1_ioctl.h"
+#include "jaguar1_video_eq.h"
+#include "jaguar1_mipi.h"
+#include "jaguar1_drv.h"
+
+#define DRIVER_VERSION				KERNEL_VERSION(0, 0x01, 0x0)
+
+#ifndef V4L2_CID_DIGITAL_GAIN
+#define V4L2_CID_DIGITAL_GAIN			V4L2_CID_GAIN
+#endif
+
+#define JAGUAR1_XVCLK_FREQ			24000000
+#define JAGUAR1_LINK_FREQ			320000000
+#define JAGUAR1_LANES			4
+#define JAGUAR1_BITS_PER_SAMPLE		8
+
+/* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
+#define JAGUAR1_PIXEL_RATE \
+	(JAGUAR1_LINK_FREQ * 2 / JAGUAR1_BITS_PER_SAMPLE * JAGUAR1_LANES)
+
+#define OF_CAMERA_PINCTRL_STATE_DEFAULT		"rockchip,camera_default"
+#define OF_CAMERA_PINCTRL_STATE_SLEEP		"rockchip,camera_sleep"
+
+#define OF_CAMERA_MODULE_REGULATORS		"rockchip,regulator-names"
+#define OF_CAMERA_MODULE_REGULATOR_VOLTAGES	"rockchip,regulator-voltages"
+
+#define JAGUAR1_NAME				"jaguar1"
+
+/* #define FORCE_720P */
+
+struct jaguar1_gpio {
+	int pltfrm_gpio;
+	const char *label;
+	enum of_gpio_flags active_low;
+};
+
+struct jaguar1_regulator {
+	struct regulator *regulator;
+	u32 min_uV;
+	u32 max_uV;
+};
+
+struct jaguar1_regulators {
+	u32 cnt;
+	struct jaguar1_regulator *regulator;
+};
+
+struct jaguar1_pixfmt {
+	u32 code;
+};
+
+struct jaguar1_framesize {
+	u16 width;
+	u16 height;
+	enum NC_VIVO_CH_FORMATDEF fmt_idx;
+};
+
+struct jaguar1 {
+	struct i2c_client	*client;
+	struct clk		*xvclk;
+	struct gpio_desc	*rst_gpio;
+	struct gpio_desc	*rst2_gpio;
+	struct gpio_desc	*pd_gpio;
+	struct gpio_desc	*pd2_gpio;
+	struct gpio_desc	*pwd_gpio;
+	struct gpio_desc	*pwd2_gpio;
+
+	struct pinctrl		*pinctrl;
+	struct pinctrl_state	*pins_default;
+	struct pinctrl_state	*pins_sleep;
+
+	struct v4l2_subdev	subdev;
+	struct media_pad	pad;
+	struct v4l2_ctrl_handler ctrl_handler;
+	struct mutex		mutex;
+	bool			power_on;
+	struct jaguar1_regulators regulators;
+
+	u32			module_index;
+	const char		*module_facing;
+	const char		*module_name;
+	const char		*len_name;
+
+	struct v4l2_mbus_framefmt format;
+	const struct jaguar1_framesize *frame_size;
+	int streaming;
+};
+
+#define to_jaguar1(sd) container_of(sd, struct jaguar1, subdev)
+
+static const struct jaguar1_framesize jaguar1_framesizes[] = {
+#ifdef FORCE_720P
+	{
+		.width		= 1280,
+		.height		= 720,
+		.fmt_idx	= AHD20_720P_25P,
+	}
+#elif defined CONFIG_VIDEO_ROCKCHIP_USBACM_CONTROL
+	{
+		.width		= 2560,
+		.height		= 1440,
+		.fmt_idx	= AHD20_720P_25P,
+	}
+#else
+	{
+		.width		= 1280,
+		.height		= 720,
+		.fmt_idx	= AHD20_720P_25P,
+	},
+	{
+		.width		= 1920,
+		.height		= 1080,
+		.fmt_idx	= AHD20_1080P_25P,
+	},
+	{
+		.width		= 2560,
+		.height		= 1440,
+		.fmt_idx	= AHD20_720P_25P,
+	}
+#endif
+};
+
+static const struct jaguar1_pixfmt jaguar1_formats[] = {
+	{
+		.code = MEDIA_BUS_FMT_YUYV8_2X8
+	},
+};
+
+static const s64 link_freq_menu_items[] = {
+	JAGUAR1_LINK_FREQ
+};
+static int __jaguar1_power_on(struct jaguar1 *jaguar1)
+{
+	u32 i;
+	int ret;
+	struct jaguar1_regulator *regulator;
+	struct device *dev = &jaguar1->client->dev;
+
+	if (!IS_ERR_OR_NULL(jaguar1->pins_default)) {
+		ret = pinctrl_select_state(jaguar1->pinctrl,
+					   jaguar1->pins_default);
+		if (ret < 0)
+			dev_err(dev, "could not set pins. ret=%d\n", ret);
+	}
+
+	ret = clk_prepare_enable(jaguar1->xvclk);
+	if (ret < 0) {
+		dev_err(dev, "Failed to enable xvclk\n");
+		return ret;
+	}
+
+	if (jaguar1->regulators.regulator) {
+		for (i = 0; i < jaguar1->regulators.cnt; i++) {
+			regulator = jaguar1->regulators.regulator + i;
+			if (IS_ERR(regulator->regulator))
+				continue;
+			regulator_set_voltage(
+				regulator->regulator,
+				regulator->min_uV,
+				regulator->max_uV);
+			if (regulator_enable(regulator->regulator)) {
+				dev_err(dev,
+					"regulator_enable failed!\n");
+				goto disable_clk;
+			}
+		}
+	}
+	usleep_range(3000, 5000);
+
+	if (!IS_ERR(jaguar1->pwd_gpio)) {
+		gpiod_direction_output(jaguar1->pwd_gpio, 1);
+		usleep_range(3000, 5000);
+	}
+
+	if (!IS_ERR(jaguar1->pwd2_gpio)) {
+		gpiod_direction_output(jaguar1->pwd2_gpio, 1);
+		usleep_range(3000, 5000);
+	}
+
+	if (!IS_ERR(jaguar1->pd_gpio)) {
+		gpiod_direction_output(jaguar1->pd_gpio, 1);
+		usleep_range(1500, 2000);
+	}
+
+	if (!IS_ERR(jaguar1->pd2_gpio)) {
+		gpiod_direction_output(jaguar1->pd2_gpio, 1);
+		usleep_range(1500, 2000);
+	}
+
+	if (!IS_ERR(jaguar1->rst_gpio)) {
+		gpiod_direction_output(jaguar1->rst_gpio, 0);
+		usleep_range(1500, 2000);
+		gpiod_direction_output(jaguar1->rst_gpio, 1);
+	}
+
+	if (!IS_ERR(jaguar1->rst2_gpio)) {
+		gpiod_direction_output(jaguar1->rst2_gpio, 0);
+		usleep_range(1500, 2000);
+		gpiod_direction_output(jaguar1->rst2_gpio, 1);
+	}
+
+	return 0;
+
+disable_clk:
+	clk_disable_unprepare(jaguar1->xvclk);
+
+	return ret;
+}
+
+static void __jaguar1_power_off(struct jaguar1 *jaguar1)
+{
+	u32 i;
+	int ret;
+	struct jaguar1_regulator *regulator;
+	struct device *dev = &jaguar1->client->dev;
+
+	if (!IS_ERR(jaguar1->pd_gpio))
+		gpiod_direction_output(jaguar1->pd_gpio, 0);
+
+	if (!IS_ERR(jaguar1->pd2_gpio))
+		gpiod_direction_output(jaguar1->pd2_gpio, 0);
+
+	clk_disable_unprepare(jaguar1->xvclk);
+
+	if (!IS_ERR(jaguar1->rst_gpio))
+		gpiod_direction_output(jaguar1->rst_gpio, 0);
+
+	if (!IS_ERR(jaguar1->rst2_gpio))
+		gpiod_direction_output(jaguar1->rst2_gpio, 0);
+
+	if (!IS_ERR(jaguar1->pwd_gpio))
+		gpiod_direction_output(jaguar1->pwd_gpio, 0);
+
+	if (!IS_ERR(jaguar1->pwd2_gpio))
+		gpiod_direction_output(jaguar1->pwd2_gpio, 0);
+
+	if (!IS_ERR_OR_NULL(jaguar1->pins_sleep)) {
+		ret = pinctrl_select_state(jaguar1->pinctrl,
+					   jaguar1->pins_sleep);
+		if (ret < 0)
+			dev_err(dev, "could not set pins\n");
+	}
+
+	if (jaguar1->regulators.regulator) {
+		for (i = 0; i < jaguar1->regulators.cnt; i++) {
+			regulator = jaguar1->regulators.regulator + i;
+			if (IS_ERR(regulator->regulator))
+				continue;
+			regulator_disable(regulator->regulator);
+		}
+	}
+}
+
+static int jaguar1_power(struct v4l2_subdev *sd, int on)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct jaguar1 *jaguar1 = to_jaguar1(sd);
+	int ret = 0;
+
+	dev_dbg(&client->dev, "%s: on %d\n", __func__, on);
+	mutex_lock(&jaguar1->mutex);
+
+	/* If the power state is not modified - no work to do. */
+	if (jaguar1->power_on == !!on)
+		goto exit;
+
+	if (on) {
+		ret = __jaguar1_power_on(jaguar1);
+		if (ret < 0)
+			goto exit;
+
+		jaguar1->power_on = true;
+	} else {
+		__jaguar1_power_off(jaguar1);
+		jaguar1->power_on = false;
+	}
+
+exit:
+	mutex_unlock(&jaguar1->mutex);
+
+	return ret;
+}
+
+static int jaguar1_initialize_controls(struct jaguar1 *jaguar1)
+{
+	struct v4l2_ctrl_handler *handler;
+	struct v4l2_ctrl *ctrl;
+	int ret;
+
+	handler = &jaguar1->ctrl_handler;
+	ret = v4l2_ctrl_handler_init(handler, 2);
+	if (ret)
+		return ret;
+	handler->lock = &jaguar1->mutex;
+
+	ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
+				      0, 0, link_freq_menu_items);
+	if (ctrl)
+		ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
+	v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
+			  0, JAGUAR1_PIXEL_RATE, 1, JAGUAR1_PIXEL_RATE);
+
+	if (handler->error) {
+		ret = handler->error;
+		dev_err(&jaguar1->client->dev,
+			"Failed to init controls(%d)\n", ret);
+		goto err_free_handler;
+	}
+
+	jaguar1->subdev.ctrl_handler = handler;
+
+	return 0;
+
+err_free_handler:
+	v4l2_ctrl_handler_free(handler);
+
+	return ret;
+}
+static void jaguar1_get_default_format(struct v4l2_mbus_framefmt *format)
+{
+	format->width = jaguar1_framesizes[0].width;
+	format->height = jaguar1_framesizes[0].height;
+	format->colorspace = V4L2_COLORSPACE_SRGB;
+	format->code = jaguar1_formats[0].code;
+	format->field = V4L2_FIELD_NONE;
+}
+
+static int jaguar1_stream(struct v4l2_subdev *sd, int on)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct jaguar1 *jaguar1 = to_jaguar1(sd);
+	video_init_all video_init;
+	enum NC_VIVO_CH_FORMATDEF fmt_idx;
+	int ch;
+
+	dev_dbg(&client->dev, "%s: on %d\n", __func__, on);
+	mutex_lock(&jaguar1->mutex);
+	on = !!on;
+
+	if (jaguar1->streaming == on)
+		goto unlock;
+
+	if (on) {
+		jaguar1_set_mclk(JAGUAR1_MCLK_1242MHZ);
+		fmt_idx = jaguar1->frame_size->fmt_idx;
+		for (ch = 0; ch < 4; ch++) {
+			video_init.ch_param[ch].ch = ch;
+			video_init.ch_param[ch].format = fmt_idx;
+			video_init.ch_param[ch].input = SINGLE_ENDED;
+			video_init.ch_param[ch].interface = YUV_422;
+		}
+		jaguar1_start(&video_init);
+	} else {
+		jaguar1_stop();
+	}
+
+	jaguar1->streaming = on;
+
+unlock:
+	mutex_unlock(&jaguar1->mutex);
+
+	return 0;
+}
+
+static int jaguar1_enum_mbus_code(struct v4l2_subdev *sd,
+				 struct v4l2_subdev_pad_config *cfg,
+				 struct v4l2_subdev_mbus_code_enum *code)
+{
+	if (code->index >= ARRAY_SIZE(jaguar1_formats))
+		return -EINVAL;
+
+	code->code = jaguar1_formats[code->index].code;
+
+	return 0;
+}
+
+static int jaguar1_enum_frame_sizes(struct v4l2_subdev *sd,
+				   struct v4l2_subdev_pad_config *cfg,
+				   struct v4l2_subdev_frame_size_enum *fse)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int i = ARRAY_SIZE(jaguar1_formats);
+
+	dev_dbg(&client->dev, "%s:\n", __func__);
+
+	if (fse->index >= ARRAY_SIZE(jaguar1_framesizes))
+		return -EINVAL;
+
+	while (--i)
+		if (fse->code == jaguar1_formats[i].code)
+			break;
+
+	fse->code = jaguar1_formats[i].code;
+
+	fse->min_width  = jaguar1_framesizes[fse->index].width;
+	fse->max_width  = fse->min_width;
+	fse->max_height = jaguar1_framesizes[fse->index].height;
+	fse->min_height = fse->max_height;
+
+	return 0;
+}
+
+static int jaguar1_g_mbus_config(struct v4l2_subdev *sd,
+				 struct v4l2_mbus_config *cfg)
+{
+	cfg->type = V4L2_MBUS_CSI2;
+	cfg->flags = V4L2_MBUS_CSI2_4_LANE |
+		     V4L2_MBUS_CSI2_CHANNELS;
+
+	return 0;
+}
+
+static int jaguar1_get_fmt(struct v4l2_subdev *sd,
+			  struct v4l2_subdev_pad_config *cfg,
+			  struct v4l2_subdev_format *fmt)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct jaguar1 *jaguar1 = to_jaguar1(sd);
+
+	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+		struct v4l2_mbus_framefmt *mf;
+
+		mf = v4l2_subdev_get_try_format(sd, cfg, 0);
+		mutex_lock(&jaguar1->mutex);
+		fmt->format = *mf;
+		mutex_unlock(&jaguar1->mutex);
+		return 0;
+#else
+	return -ENOTTY;
+#endif
+	}
+
+	mutex_lock(&jaguar1->mutex);
+	fmt->format = jaguar1->format;
+	mutex_unlock(&jaguar1->mutex);
+
+	dev_dbg(&client->dev, "%s: %x %dx%d\n", __func__,
+		jaguar1->format.code, jaguar1->format.width,
+		jaguar1->format.height);
+
+	return 0;
+}
+
+static void __jaguar1_try_frame_size(struct v4l2_mbus_framefmt *mf,
+				    const struct jaguar1_framesize **size)
+{
+	const struct jaguar1_framesize *fsize = &jaguar1_framesizes[0];
+	const struct jaguar1_framesize *match = NULL;
+	int i = ARRAY_SIZE(jaguar1_framesizes);
+	unsigned int min_err = UINT_MAX;
+
+	while (i--) {
+		unsigned int err = abs(fsize->width - mf->width)
+				+ abs(fsize->height - mf->height);
+		if (err < min_err) {
+			min_err = err;
+			match = fsize;
+		}
+		fsize++;
+	}
+
+	if (!match)
+		match = &jaguar1_framesizes[0];
+
+	mf->width  = match->width;
+	mf->height = match->height;
+
+	if (size)
+		*size = match;
+}
+
+static int jaguar1_set_fmt(struct v4l2_subdev *sd,
+			  struct v4l2_subdev_pad_config *cfg,
+			  struct v4l2_subdev_format *fmt)
+{
+	int index = ARRAY_SIZE(jaguar1_formats);
+	struct v4l2_mbus_framefmt *mf = &fmt->format;
+	const struct jaguar1_framesize *size = NULL;
+	struct jaguar1 *jaguar1 = to_jaguar1(sd);
+	int ret = 0;
+
+	__jaguar1_try_frame_size(mf, &size);
+
+	while (--index >= 0)
+		if (jaguar1_formats[index].code == mf->code)
+			break;
+
+	if (index < 0)
+		return -EINVAL;
+
+	mf->colorspace = V4L2_COLORSPACE_SRGB;
+	mf->code = jaguar1_formats[index].code;
+	mf->field = V4L2_FIELD_NONE;
+
+	mutex_lock(&jaguar1->mutex);
+
+	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+		mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
+		*mf = fmt->format;
+#else
+		return -ENOTTY;
+#endif
+	} else {
+		if (jaguar1->streaming) {
+			mutex_unlock(&jaguar1->mutex);
+			return -EBUSY;
+		}
+
+		jaguar1->frame_size = size;
+		jaguar1->format = fmt->format;
+	}
+
+	mutex_unlock(&jaguar1->mutex);
+	return ret;
+}
+
+static void jaguar1_get_module_inf(struct jaguar1 *jaguar1,
+				   struct rkmodule_inf *inf)
+{
+	memset(inf, 0, sizeof(*inf));
+	strlcpy(inf->base.sensor, JAGUAR1_NAME, sizeof(inf->base.sensor));
+	strlcpy(inf->base.module, jaguar1->module_name,
+		sizeof(inf->base.module));
+	strlcpy(inf->base.lens, jaguar1->len_name, sizeof(inf->base.lens));
+}
+
+static long jaguar1_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
+{
+	struct jaguar1 *jaguar1 = to_jaguar1(sd);
+	long ret = 0;
+
+	switch (cmd) {
+	case RKMODULE_GET_MODULE_INFO:
+		jaguar1_get_module_inf(jaguar1, (struct rkmodule_inf *)arg);
+		break;
+	default:
+		ret = -ENOTTY;
+		break;
+	}
+
+	return ret;
+}
+
+#ifdef CONFIG_COMPAT
+static long jaguar1_compat_ioctl32(struct v4l2_subdev *sd,
+				   unsigned int cmd, unsigned long arg)
+{
+	void __user *up = compat_ptr(arg);
+	struct rkmodule_inf *inf;
+	struct rkmodule_awb_cfg *cfg;
+	long ret;
+
+	switch (cmd) {
+	case RKMODULE_GET_MODULE_INFO:
+		inf = kzalloc(sizeof(*inf), GFP_KERNEL);
+		if (!inf) {
+			ret = -ENOMEM;
+			return ret;
+		}
+
+		ret = jaguar1_ioctl(sd, cmd, inf);
+		if (!ret)
+			ret = copy_to_user(up, inf, sizeof(*inf));
+		kfree(inf);
+		break;
+	case RKMODULE_AWB_CFG:
+		cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
+		if (!cfg) {
+			ret = -ENOMEM;
+			return ret;
+		}
+
+		ret = copy_from_user(cfg, up, sizeof(*cfg));
+		if (!ret)
+			ret = jaguar1_ioctl(sd, cmd, cfg);
+		kfree(cfg);
+		break;
+	default:
+		ret = -ENOIOCTLCMD;
+		break;
+	}
+
+	return ret;
+}
+#endif
+
+static int jaguar1_runtime_resume(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct jaguar1 *jaguar1 = to_jaguar1(sd);
+
+	return __jaguar1_power_on(jaguar1);
+}
+
+static int jaguar1_runtime_suspend(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct jaguar1 *jaguar1 = to_jaguar1(sd);
+
+	__jaguar1_power_off(jaguar1);
+
+	return 0;
+}
+
+static const struct dev_pm_ops jaguar1_pm_ops = {
+	SET_RUNTIME_PM_OPS(jaguar1_runtime_suspend,
+			   jaguar1_runtime_resume, NULL)
+};
+
+static const struct v4l2_subdev_video_ops jaguar1_video_ops = {
+	.s_stream = jaguar1_stream,
+	.g_mbus_config = jaguar1_g_mbus_config,
+};
+
+static const struct v4l2_subdev_pad_ops jaguar1_subdev_pad_ops = {
+	.enum_mbus_code = jaguar1_enum_mbus_code,
+	.enum_frame_size = jaguar1_enum_frame_sizes,
+	.get_fmt = jaguar1_get_fmt,
+	.set_fmt = jaguar1_set_fmt,
+};
+
+static const struct v4l2_subdev_core_ops jaguar1_core_ops = {
+	.s_power = jaguar1_power,
+	.ioctl = jaguar1_ioctl,
+#ifdef CONFIG_COMPAT
+	.compat_ioctl32 = jaguar1_compat_ioctl32,
+#endif
+};
+
+static const struct v4l2_subdev_ops jaguar1_subdev_ops = {
+	.core = &jaguar1_core_ops,
+	.video = &jaguar1_video_ops,
+	.pad   = &jaguar1_subdev_pad_ops,
+};
+
+static int jaguar1_analyze_dts(struct jaguar1 *jaguar1)
+{
+	int ret;
+	int elem_size, elem_index;
+	const char *str = "";
+	struct property *prop;
+	struct jaguar1_regulator *regulator;
+	struct device *dev = &jaguar1->client->dev;
+	struct device_node *np = of_node_get(dev->of_node);
+
+	jaguar1->xvclk = devm_clk_get(dev, "xvclk");
+	if (IS_ERR(jaguar1->xvclk)) {
+		dev_err(dev, "Failed to get xvclk\n");
+		return -EINVAL;
+	}
+	ret = clk_set_rate(jaguar1->xvclk, JAGUAR1_XVCLK_FREQ);
+	if (ret < 0) {
+		dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
+		return ret;
+	}
+	if (clk_get_rate(jaguar1->xvclk) != JAGUAR1_XVCLK_FREQ)
+		dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
+
+	jaguar1->pinctrl = devm_pinctrl_get(dev);
+	if (!IS_ERR(jaguar1->pinctrl)) {
+		jaguar1->pins_default =
+			pinctrl_lookup_state(jaguar1->pinctrl,
+					     OF_CAMERA_PINCTRL_STATE_DEFAULT);
+		if (IS_ERR(jaguar1->pins_default))
+			dev_err(dev, "could not get default pinstate\n");
+
+		jaguar1->pins_sleep =
+			pinctrl_lookup_state(jaguar1->pinctrl,
+					     OF_CAMERA_PINCTRL_STATE_SLEEP);
+		if (IS_ERR(jaguar1->pins_sleep))
+			dev_err(dev, "could not get sleep pinstate\n");
+	} else {
+		dev_err(dev, "no pinctrl\n");
+	}
+
+	elem_size = of_property_count_elems_of_size(
+		np,
+		OF_CAMERA_MODULE_REGULATOR_VOLTAGES,
+		sizeof(u32));
+	prop = of_find_property(
+		np,
+		OF_CAMERA_MODULE_REGULATORS,
+		NULL);
+	if (elem_size > 0 && !IS_ERR_OR_NULL(prop)) {
+		jaguar1->regulators.regulator =
+			devm_kzalloc(&jaguar1->client->dev,
+				     elem_size * sizeof(struct jaguar1_regulator),
+				     GFP_KERNEL);
+		if (!jaguar1->regulators.regulator)
+			dev_err(dev, "could not malloc jaguar1_regulator\n");
+
+		jaguar1->regulators.cnt = elem_size;
+
+		str = NULL;
+		elem_index = 0;
+		regulator = jaguar1->regulators.regulator;
+		if (regulator) {
+			do {
+				str = of_prop_next_string(prop, str);
+				if (!str) {
+					dev_err(dev, "%s is not match %s in dts\n",
+						OF_CAMERA_MODULE_REGULATORS,
+						OF_CAMERA_MODULE_REGULATOR_VOLTAGES);
+					break;
+				}
+				regulator->regulator =
+					devm_regulator_get_optional(dev, str);
+				if (IS_ERR(regulator->regulator))
+					dev_err(dev, "devm_regulator_get %s failed\n",
+						str);
+				of_property_read_u32_index(
+					np,
+					OF_CAMERA_MODULE_REGULATOR_VOLTAGES,
+					elem_index++,
+					&regulator->min_uV);
+				regulator->max_uV = regulator->min_uV;
+				regulator++;
+			} while (--elem_size);
+		}
+	}
+
+	jaguar1->pd_gpio = devm_gpiod_get(dev, "pd", GPIOD_OUT_LOW);
+	if (IS_ERR(jaguar1->pd_gpio))
+		dev_warn(dev, "can not find pd-gpios, error %ld\n",
+			 PTR_ERR(jaguar1->pd_gpio));
+
+	jaguar1->pd2_gpio = devm_gpiod_get(dev, "pd2", GPIOD_OUT_LOW);
+	if (IS_ERR(jaguar1->pd2_gpio))
+		dev_warn(dev, "can not find pd2-gpios, error %ld\n",
+			 PTR_ERR(jaguar1->pd2_gpio));
+
+	jaguar1->rst_gpio = devm_gpiod_get(dev, "rst", GPIOD_OUT_LOW);
+	if (IS_ERR(jaguar1->rst_gpio))
+		dev_warn(dev, "can not find rst-gpios, error %ld\n",
+			 PTR_ERR(jaguar1->rst_gpio));
+
+	jaguar1->rst2_gpio = devm_gpiod_get(dev, "rst2", GPIOD_OUT_LOW);
+	if (IS_ERR(jaguar1->rst2_gpio))
+		dev_warn(dev, "can not find rst2-gpios, error %ld\n",
+			 PTR_ERR(jaguar1->rst2_gpio));
+
+	jaguar1->pwd_gpio = devm_gpiod_get(dev, "pwd", GPIOD_OUT_HIGH);
+	if (IS_ERR(jaguar1->pwd_gpio))
+		dev_warn(dev, "can not find pwd-gpios, error %ld\n",
+			 PTR_ERR(jaguar1->pwd_gpio));
+
+	jaguar1->pwd2_gpio = devm_gpiod_get(dev, "pwd2", GPIOD_OUT_HIGH);
+	if (IS_ERR(jaguar1->pwd2_gpio))
+		dev_warn(dev, "can not find pwd2-gpios, error %ld\n",
+			 PTR_ERR(jaguar1->pwd2_gpio));
+
+	return 0;
+}
+
+static int jaguar1_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	struct device *dev = &client->dev;
+	struct device_node *node = dev->of_node;
+	struct jaguar1 *jaguar1;
+	struct v4l2_subdev *sd;
+	__maybe_unused char facing[2];
+	int ret;
+
+	dev_info(dev, "driver version: %02x.%02x.%02x",
+		 DRIVER_VERSION >> 16,
+		 (DRIVER_VERSION & 0xff00) >> 8,
+		 DRIVER_VERSION & 0x00ff);
+
+	jaguar1 = devm_kzalloc(dev, sizeof(*jaguar1), GFP_KERNEL);
+	if (!jaguar1)
+		return -ENOMEM;
+
+	ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
+				   &jaguar1->module_index);
+	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
+				       &jaguar1->module_facing);
+	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
+				       &jaguar1->module_name);
+	ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
+				       &jaguar1->len_name);
+	if (ret) {
+		dev_err(dev, "could not get %s!\n", RKMODULE_CAMERA_LENS_NAME);
+		return -EINVAL;
+	}
+
+	jaguar1->client = client;
+
+	ret = jaguar1_analyze_dts(jaguar1);
+	if (ret) {
+		dev_err(dev, "Failed to analyze dts\n");
+		return ret;
+	}
+
+	mutex_init(&jaguar1->mutex);
+	jaguar1_get_default_format(&jaguar1->format);
+	jaguar1->frame_size = &jaguar1_framesizes[0];
+
+	sd = &jaguar1->subdev;
+	v4l2_i2c_subdev_init(sd, client, &jaguar1_subdev_ops);
+	ret = jaguar1_initialize_controls(jaguar1);
+
+	__jaguar1_power_on(jaguar1);
+	ret = jaguar1_init(i2c_adapter_id(client->adapter));
+	if (ret) {
+		dev_err(dev, "Failed to init jaguar1\n");
+		__jaguar1_power_off(jaguar1);
+		mutex_destroy(&jaguar1->mutex);
+
+		return ret;
+	}
+
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+#endif
+
+#if defined(CONFIG_VIDEO_ROCKCHIP_USBACM_CONTROL)
+	__jaguar1_power_off(jaguar1);
+	mutex_destroy(&jaguar1->mutex);
+
+	return 0;
+#endif
+
+#if defined(CONFIG_MEDIA_CONTROLLER)
+	jaguar1->pad.flags = MEDIA_PAD_FL_SOURCE;
+	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
+	ret = media_entity_pads_init(&sd->entity, 1, &jaguar1->pad);
+	if (ret < 0)
+		goto err_power_off;
+#endif
+
+	memset(facing, 0, sizeof(facing));
+	if (strcmp(jaguar1->module_facing, "back") == 0)
+		facing[0] = 'b';
+	else
+		facing[0] = 'f';
+
+	snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
+		 jaguar1->module_index, facing,
+		 JAGUAR1_NAME, dev_name(sd->dev));
+
+	ret = v4l2_async_register_subdev_sensor_common(sd);
+	if (ret) {
+		dev_err(dev, "v4l2 async register subdev failed\n");
+		goto err_clean_entity;
+	}
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
+	pm_runtime_idle(dev);
+
+	return 0;
+
+err_power_off:
+	__jaguar1_power_off(jaguar1);
+err_clean_entity:
+#if defined(CONFIG_MEDIA_CONTROLLER)
+	media_entity_cleanup(&sd->entity);
+#endif
+	mutex_destroy(&jaguar1->mutex);
+
+	return ret;
+}
+
+static int jaguar1_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct jaguar1 *jaguar1 = to_jaguar1(sd);
+
+	jaguar1_exit();
+	v4l2_ctrl_handler_free(&jaguar1->ctrl_handler);
+	mutex_destroy(&jaguar1->mutex);
+
+	pm_runtime_disable(&client->dev);
+	if (!pm_runtime_status_suspended(&client->dev))
+		__jaguar1_power_off(jaguar1);
+	pm_runtime_set_suspended(&client->dev);
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_OF)
+static const struct of_device_id jaguar1_of_match[] = {
+	{ .compatible = "jaguar1-v4l2" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, jaguar1_of_match);
+#endif
+
+static const struct i2c_device_id jaguar1_match_id[] = {
+	{ "jaguar1-v4l2", 0 },
+	{ },
+};
+
+static struct i2c_driver jaguar1_i2c_driver = {
+	.driver = {
+		.name = JAGUAR1_NAME,
+		.pm = &jaguar1_pm_ops,
+		.of_match_table = of_match_ptr(jaguar1_of_match),
+	},
+	.probe		= &jaguar1_probe,
+	.remove		= &jaguar1_remove,
+	.id_table	= jaguar1_match_id,
+};
+
+static int __init sensor_mod_init(void)
+{
+	return i2c_add_driver(&jaguar1_i2c_driver);
+}
+
+static void __exit sensor_mod_exit(void)
+{
+	i2c_del_driver(&jaguar1_i2c_driver);
+}
+
+device_initcall_sync(sensor_mod_init);
+module_exit(sensor_mod_exit);
+
+MODULE_DESCRIPTION("jaguar1 sensor driver");
+MODULE_LICENSE("GPL v2");

drivers/media/i2c/jaguar1_drv/jaguar1_video.c

@@ -0,0 +1,945 @@
+// SPDX-License-Identifier: GPL-2.0
+/********************************************************************************
+ *
+ *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
+ *  Module		: video_input.c
+ *  Description	:
+ *  Author		:
+ *  Date         :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History      :
+ *
+ *
+ ********************************************************************************/
+#include <linux/string.h>
+#include <linux/delay.h>
+#include "jaguar1_common.h"
+#include "jaguar1_video.h"
+#include "jaguar1_video_eq.h"
+#include "jaguar1_video_table.h"
+#include "jaguar1_coax_protocol.h"
+#include "jaguar1_reg_set_def.h"
+
+
+static unsigned char cur_bank = 0xff;
+static int print_flag = 0;
+
+/**************************************************************************************
+ * Jaguar1 Video Input initialize value get from table
+ ***************************************************************************************/
+static NC_VD_VI_Init_STR *__NC_VD_VI_Init_Val_Get( NC_VIVO_CH_FORMATDEF def )
+{
+	NC_VD_VI_Init_STR *pRet = &vd_vi_init_list[def];
+	if( pRet == NULL )
+	{
+		printk("[DRV]vd_vi_init_list Not Supported format Yet!!!(%d)\n",def);
+	}
+	return  pRet;
+}
+
+static NC_VD_VO_Init_STR *__NC_VD_VO_Init_Val_Get( NC_VIVO_CH_FORMATDEF def )
+{
+	NC_VD_VO_Init_STR *pRet = &vd_vo_init_list[def];
+	if( pRet == NULL )
+	{
+		printk("[DRV]vd_vo_init_list Not Supported format Yet!!!(%d)\n",def);
+	}
+	return  pRet;
+}
+
+/**************************************************************************************
+ * Jaguar1 Register Setting Function
+ *
+ *
+ ***************************************************************************************/
+void reg_val_print_flag_set( int set )
+{
+	print_flag = set;
+}
+
+static int reg_val_print_flag_get( void )
+{
+	return print_flag;
+}
+
+void current_bank_set( unsigned char bank )
+{
+	cur_bank = bank;
+}
+
+unsigned char current_bank_get( void )
+{
+	return cur_bank;
+}
+
+void vd_register_set( int dev, unsigned char bank, unsigned char addr, unsigned char val, int pos, int size )
+{
+	unsigned char ReadVal = 0x00;
+	unsigned char Mask = 0x00;
+	unsigned char rstbit = 0x01;
+	unsigned char WriteVal = val;
+	unsigned char cur_bank = 0x00;
+	int ii =0;
+
+	if( 8 < (pos + size) )
+	{
+		printk("vd_register_set Error!!dev[%d] Bank[0x%02X] Addr[0x%02X] pos[%d] size[%d]\n", dev, bank, addr, pos, size);
+	}
+
+	// Current Bank Get
+	cur_bank = current_bank_get();
+	if( cur_bank != bank )
+	{
+		JAGUAR1_BANK_CHANGE(bank);
+		current_bank_set(bank);
+	}
+
+	// If Data Size 8 Bit, Register Read Skip
+	if( !(pos == 0 && size == 8) )
+	{
+		for(ii=0; ii<size; ii++)
+		{
+			Mask = Mask|(rstbit<<(pos+ii));
+		}
+		Mask = ~Mask;
+		WriteVal = WriteVal<<pos;
+
+		ReadVal = gpio_i2c_read(jaguar1_i2c_addr[dev], addr);
+		ReadVal = ReadVal & Mask;
+		WriteVal = WriteVal | ReadVal;
+	}
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev], addr, WriteVal);
+
+	if( reg_val_print_flag_get() )
+		printk("[DRV]%Xx%02X > 0x%02X\n", current_bank_get(), addr, WriteVal);
+
+}
+
+/**************************************************************************************
+ * Jaguar1 Video Input Setting Function
+ *
+ *
+ ***************************************************************************************/
+static void vd_vi_manual_set_seq1( unsigned char dev, unsigned char ch, void *p_param )
+{
+	/*====================================================================
+	 * Bank 1x7c
+	 *|   7   |   6   |   5   |    4   |   3        |   2        |   1        |   0        |
+	 *|       |       |       |        | CLK_AUTO_4 | CLK_AUTO_3 | CLK_AUTO_2 | CLK_AUTO_1 |
+	 *====================================================================*/
+	/*====================================================================
+	 * Bank 0x14
+	 *|   7   |   6   |   5   |    4      |   3   |   2  |   1  |   0  |
+	 *|       |       |       | FLD_INV_x |         CHID_VIN_x         |
+	 *====================================================================*/
+	/*====================================================================
+	 * Bank 0x14
+	 *|   7   |   6   |   5   |    4      |   3   |   2  |   1  |   0  |
+	 *|       |       |       | FLD_INV_x |         CHID_VIN_x         |
+	 *====================================================================*/
+	/*====================================================================
+	 * Bank 5x32
+	 *|   7   |   6   |   5   |    4   |   3  |   2  |   1   |   0   |
+	 *|       |       |  FLD_DET_MODE  |      |      |   NOVID_DET_A |
+	 *====================================================================*/
+	/*====================================================================
+	 * Bank 13x30 ~ 33  - SK_ing
+	 *|   7   |   6   |   5   |   4   |   3   |   2   |   1   |   0   |
+	 *|       |       |det_en |det_en |det_en |det_en |det_en |det_en |
+	 *====================================================================*/
+	/*====================================================================
+	 * Bank 9x44
+	 *|   7   |   6   |   5   |   4   |   3   |   2   |   1   |   0   		|
+	 *|       |       | 	  |		  |		  |		  |		  |FSC_EXT_EN_1 |
+	 *====================================================================*/
+	NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
+	unsigned char val_13x30;
+	unsigned char val_13x31;
+	unsigned char val_13x32;
+
+	if(ch == 0)
+		REG_SET_1x7C_0_1_clk_auto_1( ch, 0x0 );
+	else if(ch ==1)
+		REG_SET_1x7C_1_1_clk_auto_2( ch, 0x0 );
+	else if(ch ==2)
+		REG_SET_1x7C_2_1_clk_auto_3( ch, 0x0 );
+	else if(ch ==3)
+		REG_SET_1x7C_3_1_clk_auto_4( ch, 0x0 );
+	else
+		printk("[DRV]Clock Auto Set Fail!!:: %x\n", ch);
+
+	REG_SET_5x32_0_8_NOVIDEO_DET_A( ch, 0x10 );
+	REG_SET_5xB9_0_8_HAFC_LPF_SEL( ch, 0xb2 );
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x13);
+	val_13x30 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x30);
+	val_13x31 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x31);
+	val_13x32 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x32);
+
+	val_13x30 &= (~(1 << (ch + 4)) & (~(1 << ch)));
+	val_13x31 &= (~(1 << (ch + 4)) & (~(1 << ch)));
+	val_13x32 &= (~(1 << ch));
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x30, val_13x30);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x31, val_13x31);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x32, val_13x32);
+
+	REG_SET_9x44_0_8_FSC_EXT_EN( ch, 0x00 );
+	REG_SET_5x6E_0_8_VBLK_END_SEL( ch, param->vblk_end_sel );
+	REG_SET_5x6F_0_8_VBLK_END_EXT( ch, param->vblk_end_ext );
+
+}
+
+static void vd_vi_vafe_set_seq2( unsigned char dev, unsigned char ch )
+{
+	REG_SET_5x00_0_8_A_CMP_PW_MODE( ch, 0xd0 );
+	REG_SET_5x02_0_8_A_CMP_TIMEUNIT( ch, 0x0c );
+	REG_SET_5x1E_0_8_VAFEMD( ch, 0x00 );
+	REG_SET_5x58_0_8_VAFE1_EQ_BAND_SEL( ch, 0x00 );
+	REG_SET_5x59_0_8_LPF_BYPASS( ch, 0x00 );
+	REG_SET_5x5A_0_8_VAFE_IMP_CNT( ch, 0x00 );
+	REG_SET_5x5B_0_8_VAFE_DUTY( ch, 0x41 );
+	REG_SET_5x5C_0_8_VAFE_B_LPF_SEL( ch, 0x78 );
+	REG_SET_5x94_0_8_PWM_DELAY_H( ch, 0x00 );
+	REG_SET_5x95_0_8_PWM_DELAY_L( ch, 0x00 );
+	REG_SET_5x65_0_8_VAFE_CML_SPEED( ch, 0x80 );
+
+}
+
+static void vd_vi_format_set_seq3( unsigned char dev, unsigned char ch, void *p_param )
+{
+	/*============================================================================================
+	 * Bank 0x10
+	 *|   7   |   6   |   5   |   4   |   3  |  2  |   1  |  0  |
+	 *|       |   BSF_MODE_1  |           VIDEO_FORMAT_1        |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 0x0c
+	 *|   7   |   6   |   5   |   4   |   3  |  2  |   1  |  0  |
+	 *|       |       |       |       |     SPECIAL_MODE        |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 0x04
+	 *|   7   |   6   |   5   |   4   |   3  |  2  |   1  |  0  |
+	 *|       |       |       |       |           SD_MD         |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 0x08
+	 *|   7   |   6   |   5   |   4   |   3  |  2  |   1  |  0  |
+	 *|       |       |       |       |           AHD_MD        |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 5x69
+	 *|   7          |   6   |         5         |   4    |   3  |  2  |   1  |      0      |
+	 *| NO_VIDEO_OFF |       | OUTPUT PATTERN_ON | MEM_EN |      |     |      | SD_FREQ_SEL |
+	 *============================================================================================*/
+	NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
+
+	if(ch>3)
+	{
+		printk("[DRV] %s CHID Error\n", __func__);
+		return;
+	}
+
+	REG_SET_0x10_0_8_VD_FMT( ch, param->video_format );
+	REG_SET_0x0C_0_8_SPL_MODE( ch, param->spl_mode );
+	REG_SET_0x04_0_8_SD_MODE( ch, param->sd_mode );
+	REG_SET_0x08_0_8_AHD_MODE( ch, param->ahd_mode );
+	REG_SET_5x69_0_1_SD_FREQ_SEL( ch, param->sd_freq_sel );
+	REG_SET_5x62_0_8_SYNC_SEL( ch, param->sync_sel );
+
+}
+
+static void vd_vi_chroma_set_seq4( unsigned char dev, unsigned char ch, void *p_param )
+{
+	/*============================================================================================
+	 * Bank 0x5c
+	 *|   7        |   6   |   5   |     4    |  3  |  2  |   1  |  0  |
+	 *| PAL_CM_OFF |       |       | COLOROFF |           C_KILL       |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 5x28
+	 *|      7        |    6    |   5    |    4   |  3  |  2  |   1  |  0  |
+	 *| CTI_CORE_MODE | S_POINT |   CTI_DELAY_SEL |     |     |      |     |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 5x25
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |   1  |  0  |
+	 *|      FSC_LOCK_MODE    |      FSC_LOCK_SPD      |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 5x90
+	 *|     7      |  6  |   5   |   4   |  3  |  2  |  1  |  0  |
+	 *| C_LH_SEL_1 |     |    YL_SEL_1   |      COMB_MODE_1      |
+	 *============================================================================================*/
+	NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
+
+	if(ch>3)
+	{
+		printk("[DRV] %s CHID Error\n", __func__);
+		return;
+	}
+
+	REG_SET_0x5C_0_8_PAL_CM_OFF( ch, param->pal_cm_off );
+	REG_SET_5x28_0_8_S_POINT( ch, param->s_point );
+	REG_SET_5x25_0_8_FSC_LOCK_MODE( ch, param->fsc_lock_mode );
+	REG_SET_5x90_0_8_COMB_MODE( ch, param->comb_mode );
+
+}
+
+static void vd_vi_h_timing_set_seq5( unsigned char dev, unsigned char ch, void *p_param )
+{
+	/*============================================================================================
+	 * Bank 0x68
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |   1  |  0  |
+	 *|                     H_DELAY                    |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 0x60
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |   1  |  0  |
+	 *|                 |            Y_DELAY           |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 0x78
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |   1  |  0  |
+	 *|                      VBLK_END                  |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 5x38
+	 *|  7  |  6  |  5  |    4    |  3   |   2  |    1  |  0   |
+	 *|                 | MASK_ON | MASK_SEL1 (Bank0 0x8E[3:0) |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 0x64
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
+	 *|       DF_CDELAY       |       DF_YDELAY       |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 0x14
+	 *|  7  |  6  |  5  |  4      |  3  |  2  |  1  |  0  |
+	 *|                 | FLD_INV |       CHID_VIN        |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 5x64
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
+	 *|     |     |     |     |       MEM_RDP_01      |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 5x47
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
+	 *|                 CONTROL_MODES                 |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 5xa9
+	 *|  7                    |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
+	 *| SIGNED_ADV_STP_DELAY1 |             ADV_STP_DELAY1              |
+	 *============================================================================================*/
+	NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
+
+	if(ch>3)
+	{
+		printk("[DRV] %s CHID Error\n", __func__);
+		return;
+	}
+
+	REG_SET_0x68_0_8_H_DLY_LSB( ch, param->h_delay_lsb );
+	REG_SET_0x6c_0_8_H_DLY_MSB( ch, param->h_dly_msb);
+	REG_SET_0x60_0_8_Y_DLY( ch, param->y_delay );
+	REG_SET_0x78_0_8_V_BLK_END_A( ch, param->v_blk_end_a );
+
+	REG_SET_5x38_4_1_H_MASK_ON( ch, param->h_mask_on );
+	REG_SET_5x38_0_4_H_MASK_SEL( ch, param->h_mask_sel );
+
+	REG_SET_0x64_0_8_V_BLK_END_B( ch, param->v_blk_end_b );
+	REG_SET_0x14_4_1_FLD_INV( ch, param->fld_inv );
+
+	REG_SET_5x64_0_8_MEM_RDP( ch, param->mem_rdp );
+	REG_SET_5x47_0_8_SYNC_RS( ch, param->sync_rs );
+	REG_SET_5xA9_0_8_V_BLK_END_B( ch, param->v_blk_end_b );
+
+}
+
+static void vd_vi_h_scaler_mode_set_seq6( unsigned char dev, unsigned char ch, void *p_param )
+{
+	/*============================================================================================
+	 * Bank 5x53
+	 *|  7  |  6  |  5             |  4         |  3  |  2   |  1  |  0          |
+	 *|     |     | PROTECTION_OFF | BT_601_SEL | LINEMEM_MD |     | C_DITHER_ON |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 9x96
+	 *|  7  |  6  |  5  |  4                    |  3  |  2  |  1                   |  0                  |
+	 *|     |     |     | CH1_H_DOWN_SCALER_EN  |     |     | CH1_H_SCALER_TRS_SEL | CH1_H_SCALER_ENABLE |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 9x97
+	 *|  7  |  6  |  5  |  4   |  3       |  2        |  1                      |  0                |
+	 *|     CH1_H_SCALER_MODE  | CH1_H_SCALER_RD_MODE | CH1_H_SCALER_AUTO_H_REF | CH1_H_SCALER_AUTO |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 9x98
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
+	 *|          CH1_H_SCALER_H_REF_BASE[7:0]         |
+	 * Bank 9x99
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
+	 *|          CH1_H_SCALER_H_REF_BASE[15:8]        |
+	 *============================================================================================*/
+
+	NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
+
+	if(ch>3)
+	{
+		printk("[DRV] %s CHID Error\n", __func__);
+		return;
+	}
+
+	REG_SET_5x53_2_2_LINEMEM_MD( ch, param->line_mem_mode );
+
+	REG_SET_9x96_0_8_H_DOWN_SCALER( ch, param->h_down_scaler );
+	REG_SET_9x97_0_8_H_SCALER_MODE( ch, param->h_scaler_mode );
+	REG_SET_9x98_0_8_REF_BASE_LSB( ch, param->ref_base_lsb );
+	REG_SET_9x99_0_8_REF_BASE_MSB( ch, param->ref_base_msb );
+	REG_SET_9x9E_0_8_H_SCALER_OUTPUT_H_ACTIVE( ch, param->h_scaler_active );
+}
+
+static void vd_vi_hpll_set_seq7( unsigned char dev, unsigned char ch, void *p_param )
+{
+	/*============================================================================================
+	 * Bank 5x50
+	 *|  7  |  6               |  5  |  4                |  3      |  2       |  1           |  0       |
+	 *|     | NCO_GDF_COEFF_IV |     | NCO_GDF_COEFF_OFF | Y_TEMP_SEL(5T,15T) | HPLL_MASK_ON | CONT_SUB |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 5xb8
+	 *|  7          |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
+	 *| HAFC_BYPASS | HAFC_HCOEFF_SEL |       HAFC_OP_MD      |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 5xbb
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
+	 *|                 HPLL_MASK_END                 |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 5xbb
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
+	 *|            HAFC_BYP_TH_S(write)               |
+	 *============================================================================================*/
+	NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
+
+	if(ch>3)
+	{
+		printk("[DRV] %s CHID Error\n", __func__);
+		return;
+	}
+
+	REG_SET_5x50_0_8_HPLL_MASK_ON( ch, param->hpll_mask_on );
+	REG_SET_5xB8_0_8_HAFC_OP_MD( ch, param->hafc_op_md );
+	REG_SET_5xBB_0_8_HAFC_BYP_TH_E( ch, param->hafc_byp_th_e );
+	REG_SET_5xB7_0_8_HAFC_BYP_TH_S( ch, param->hafc_byp_th_s );
+
+}
+
+static void vd_vi_color_set_seq8( unsigned char dev, unsigned char ch, void *p_param, NC_VIVO_CH_FORMATDEF fmt )
+{
+	/*============================================================================================
+	 * gpio_i2c_write(jaguar1_i2c_addr[dev], 0x22 + (ch*4), 0x0B ); // Raptor3
+	 * Bank 0x5c
+	 *|  7         |  6  |  5  |   4      |  3  |  2  |  1  |  0  |
+	 *| PAL_CM_OFF |     |     | COLOROFF |         C_KILL        |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 5x26
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
+	 *|                 FSC_LOCK_SENSE                |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 5xb8
+	 *|  7          |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
+	 *| HAFC_BYPASS | HAFC_HCOEFF_SEL |       HAFC_OP_MD      |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 9x40
+	 *|  7        |   6      |  5       |    4     |    3     |     2       |  1  |  0       |
+	 *| FSC_DET_  | FSC_DET_ | FSC_DET_ | FSC_DET_ | FSC_DET_ |   FSC_DET_  |     | FSC_RST_ |
+	 *| AUTO_RST1 | UNLIM1   | AUTO1    | PRESET1  | MODE1    | REFER_AUTO1 |     | STRB1    |
+	 *============================================================================================*/
+
+	NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
+
+	REG_SET_0x20_0_8_BRIGHTNESS( ch, param->brightnees );
+	REG_SET_0x24_0_8_CONTARST( ch, param->contrast );
+	REG_SET_0x28_0_8_BLACK_LEVEL( ch, param->black_level );
+	REG_SET_0x58_0_8_SATURATION_A( ch, param->saturation_a );
+	REG_SET_0x40_0_8_HUE( ch, param->hue );
+	REG_SET_0x44_0_8_U_GAIN( ch, param->u_gain );
+	REG_SET_0x48_0_8_V_GAIN( ch, param->v_gain );
+	REG_SET_0x4C_0_8_U_OFFSET( ch, param->u_offset );
+	REG_SET_0x50_0_8_V_OFFSET( ch, param->v_offset );
+	REG_SET_5x2B_0_8_SATURATION_B( ch, param->saturation_b );
+	REG_SET_5x24_0_8_BURSET_DEC_A( ch, param->burst_dec_a );
+	REG_SET_5x5F_0_8_BURSET_DEC_B( ch, param->burst_dec_b );
+	REG_SET_5xD1_0_8_BURSET_DEC_C( ch, param->burst_dec_c );
+
+	REG_SET_9x44_0_8_FSC_EXT_EN( ch, 0x00 );
+	REG_SET_9x50_0_8_FSC_EXT_VAL_7_0( ch, 0x30 );
+	REG_SET_9x51_0_8_FSC_EXT_VAL_15_8( ch, 0x6f );
+	REG_SET_9x52_0_8_FSC_EXT_VAL_23_16( ch, 0x67 );
+	REG_SET_9x53_0_8_FSC_EXT_VAL_31_24( ch, 0x48 );
+
+	if(fmt == TVI_5M_12_5P)
+	{
+		REG_SET_5x26_0_8_FSC_LOCK_SENSE( ch, 0x20 );
+	}
+	else
+		REG_SET_5x26_0_8_FSC_LOCK_SENSE( ch, 0x40 );
+
+	if(fmt == AHD20_SD_H960_2EX_Btype_NT || fmt == AHD20_SD_H960_2EX_Btype_PAL)
+	{
+		REG_SET_5xB8_0_8_HPLL_MASK_END( ch, 0xb8 );
+		REG_SET_9x40_0_8_FSC_DET_MODE( ch, 0x00);
+	}
+	else
+	{
+		REG_SET_5xB8_0_8_HPLL_MASK_END( ch, 0x39 );
+		REG_SET_9x40_0_8_FSC_DET_MODE( ch, 0x00 );
+
+		gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x05 + ch);
+		gpio_i2c_write(jaguar1_i2c_addr[dev], 0xb5, 0x80);  // HPLL Locking Ref. Range
+	}
+
+}
+
+static void vd_vi_clock_set_seq9( unsigned char dev, unsigned char ch, void *p_param )
+{
+	/*============================================================================================
+	 * Bank 1x84
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
+	 *|   VADC_CLK1_DLY_SEL   |     VADC_CLK1_SEL     |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Bank 1x88
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |   1   |   0   |
+	 *|     |     |     |     |     |     |  DEC_PRECLK   |
+	 * Bank 1x8c
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |   1   |   0   |
+	 *|     |     |     |     |     |     |  DEC_POSTCLK  |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * ADC -> PRE -> POST -> VCLK
+	 * ADC_CLK 1x84[3:0]
+	 * 0 ~ 3 : 37.125 MHz
+	 * 4 ~ 5 : 74.25 MHz
+	 * 8 ~ 9 : 148.5 MHz
+	 * Pre_Clock 1x88 / Post Clock 1x8C
+	 * 0 : 37.125
+	 * 1 : 74.25
+	 * 2 : 148.5
+	 * VCLK 1xCC[7:4]
+	 * 4 ~ 5 : 74.25 MHz
+	 * 6 ~ 7 : 148.5 MHz
+	 *============================================================================================*/
+
+	NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
+
+	REG_SET_1x84_0_8_CLK_ADC( ch, param->clk_adc );
+	REG_SET_1x88_0_8_CLK_PRE( ch, param->clk_pre );
+	REG_SET_1x8c_0_8_CLK_POST( ch, param->clk_post );
+
+	REG_SET_5x01_0_8_CML_MODE( ch, param->cml_mode );
+	REG_SET_5x05_0_8_AGC_OP( ch, param->agc_op );
+	REG_SET_5x1D_0_8_G_SEL( ch, param->g_sel );
+
+}
+
+//==================================================================================================================
+
+/**************************************************************************************
+ * Jaguar1 Video Output Setting Function
+ *
+ *
+ ***************************************************************************************/
+void vd_vo_seq_set( unsigned char dev, unsigned char ch, void *p_param )
+{
+	/*
+	 * BT656 or BT1120 Set????...
+	 * */
+	NC_VD_VO_Init_STR *param = (NC_VD_VO_Init_STR*)p_param;
+
+	// BANK 1
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x01);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xc0 + (ch * 0x02), param->port_seq_ch01[ch]);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xc1 + (ch * 0x02), param->port_seq_ch23[ch]);
+
+}
+
+static void vd_vo_output_seq_set( unsigned char dev, unsigned char port, unsigned char out_ch )
+{
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x01);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xc0 + (port * 0x02), out_ch);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xc1 + (port * 0x02), out_ch);
+}
+
+static void vd_vo_port_y_c_merge_set( unsigned char dev, unsigned char ch, void *p_param)
+{
+	NC_VD_VO_Init_STR *param = (NC_VD_VO_Init_STR*)p_param;
+
+	/*============================================================================================
+	 * Address: 1xec
+	 *|  7  |  6  |  5  |  4  |  3  |  2  |  1  |        0      |
+	 *|     |     |     |     |     |     |     | MUX_YC_MERGE1 |
+	 *============================================================================================*/
+	REG_SET_1xEC_0_8_yc_merge( ch, param->mux_yc_merge );
+
+}
+
+static void vd_vo_port_ch_id_set( unsigned char dev, unsigned char ch, void *p_param )
+{
+	NC_VD_VO_Init_STR *param = (NC_VD_VO_Init_STR*)p_param;
+	unsigned char val_0x14 = 0x00;
+
+	/*============================================================================================
+	 * Address: 0x14
+	 *|  7  |  6  |  5  |      4    |  3  |  2  |  1  |  0  |
+	 *|     |     |     | FLD_INV_1 |       CHID_VIN1       |
+	 *============================================================================================*/
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x00);
+	val_0x14 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x14 + ch);
+	val_0x14 = val_0x14 & 0x10;
+	val_0x14 = val_0x14 | param->chid_vin;
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x14 + ch, val_0x14);
+
+}
+
+static void vd_vo_mux_mode_set( unsigned char dev, unsigned char ch, void *p_param )
+{
+	NC_VD_VO_Init_STR *param = (NC_VD_VO_Init_STR*)p_param;
+
+	/*============================================================================================
+	 * Address: 1xc8
+	 *|  7  |  6  |     5     |     4    |  3  |  2  |  1  |  0  |
+	 *|     |     | VCLK_1_EN | VDO_1_EN |   VPORT_1_CH_OUT_SEL  |
+	 *============================================================================================*/
+	REG_SET_1xC8_0_8_out_sel( ch , param->vport_out_sel );
+
+}
+
+static void vd_vo_manual_mode_set(unsigned char dev, unsigned char ch, void *p_param )
+{
+	//NC_VD_VO_Init_STR *param = (NC_VD_VO_Init_STR*)p_param;
+
+	unsigned char val_0x30;
+	unsigned char val_0x31;
+	unsigned char val_0x32;
+
+	/*============================================================================================
+	 * Address: 13x30
+	 *|  7  |  6  |  5  |  4  |             3            |  2  |  1  |  0  |
+	 *|     |     |     |     | NOVIDEO_VFC_INIT_EN[3:0] |     |     |     |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Address: 13x31
+	 *|  7  |  6  |       5       |        4      |       3       |       2       |       1       |        0      |
+	 *|     |     | AHD_8M_det_en | AHD_5M_det_en | AHD_4M_det_en | AHD_3M_det_en | AHD_2M_det_en | AHD_1M_det_en |
+	 *============================================================================================*/
+	/*============================================================================================
+	 * Address: 13x32
+	 *|  7  |  6  |       5       |        4      |       3       |       2       |       1       |        0      |
+	 *|     |     | CVI_8M_det_en | CVI_5M_det_en | CVI_4M_det_en | CVI_3M_det_en | CVI_2M_det_en | CVI_1M_det_en |
+	 *============================================================================================*/
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x13);
+	val_0x30 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x30);
+	val_0x31 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x31);
+	val_0x32 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x32);
+
+	val_0x30 &= (~(1 << (ch + 4)) & (~(1 << ch)));
+	val_0x31 &= (~(1 << (ch + 4)) & (~(1 << ch)));
+	val_0x32 &= (~(1 << ch));
+
+	// 0x00 Set Test
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x30, val_0x30);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x31, val_0x31);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x32, val_0x32);
+
+}
+
+static void vd_jaguar1_single_differ_set( unsigned char dev, unsigned char ch, int input )
+{
+	REG_SET_0x18_0_8_EX_CBAR_ON( ch, 0x13 );
+
+	if( input == DIFFERENTIAL )
+	{
+		REG_SET_5x00_0_8_CMP( ch, 0xd0 );
+		REG_SET_5x01_0_8_CML( ch, 0x2c );
+		REG_SET_5x1D_0_8_AFE( ch, 0x8c );
+		REG_SET_5x92_0_8_PWM( ch, 0x00 );
+	}
+	else if( input == SINGLE_ENDED )
+	{
+		REG_SET_5x00_0_8_CMP( ch, 0xd0 );
+		REG_SET_5x01_0_8_CML( ch, 0xa2 );
+		//REG_SET_5x1D_0_8_AFE( ch, 0x00 );
+		REG_SET_5x92_0_8_PWM( ch, 0x00 );
+	}
+	else
+	{
+		printk("Jaguar1 Analog Input Setting Fail !!!\n");
+	}
+
+}
+
+static void vd_jaguar1_960p_30P_test_set( unsigned char dev, unsigned char ch )
+{
+	printk("[drv]vd_jaguar1_960p_30P_test_set >>> ch%d!!\n", ch);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x68 + ch, 0x4E);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x69 + ch, 0x80);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6a + ch, 0x80);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6b + ch, 0x80);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x04 + ch, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x08 + ch, 0x02);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0c + ch, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x18 + ch, 0x01);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x64 + ch, 0x06);
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x01);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x84 + ch, 0x04);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x88 + ch, 0x01);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x8c + ch, 0x02);
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x05 + ch);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6e, 0x10);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6f, 0x82);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x76, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x77, 0x80);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x78, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x79, 0x11);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xB5, 0x80);
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x11);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x00 + ( ch * 0x20 ), 0x0f);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x01 + ( ch * 0x20 ), 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x02 + ( ch * 0x20 ), 0x9d);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x03 + ( ch * 0x20 ), 0x05);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x04 + ( ch * 0x20 ), 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x05 + ( ch * 0x20 ), 0x08);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x06 + ( ch * 0x20 ), 0xca);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0a + ( ch * 0x20 ), 0x03);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0b + ( ch * 0x20 ), 0xc0);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0c + ( ch * 0x20 ), 0x04);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0d + ( ch * 0x20 ), 0x4b);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x10 + ( ch * 0x20 ), 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x11 + ( ch * 0x20 ), 0x96);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x12 + ( ch * 0x20 ), 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x13 + ( ch * 0x20 ), 0x82);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x14 + ( ch * 0x20 ), 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x15 + ( ch * 0x20 ), 0x30);
+
+}
+
+static void vd_jaguar1_960p_25P_test_set( unsigned char dev, unsigned char ch )
+{
+	printk("[drv]vd_jaguar1_960p_25P_test_set >>> ch%d!!\n", ch);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x68 + ch, 0x59);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x69 + ch, 0x80);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6a + ch, 0x80);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6b + ch, 0x80);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x04 + ch, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x08 + ch, 0x03);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0c + ch, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x18 + ch, 0x01);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x64 + ch, 0x06);
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x01);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x84 + ch, 0x04);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x88 + ch, 0x01);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x8c + ch, 0x02);
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x05 + ch);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6e, 0x10);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6f, 0x82);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x76, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x77, 0x80);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x78, 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x79, 0x11);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xB5, 0x80);
+
+	// Only AHD20_720P_960P_25P
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x09);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x53 + (ch * 0x04), 0x52);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x52 + (ch * 0x04), 0xd2);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x51 + (ch * 0x04), 0x1c);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x50 + (ch * 0x04), 0x10);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x44 + ch, 0x01);
+
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x11);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x00 + ( ch * 0x20 ), 0x0f);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x01 + ( ch * 0x20 ), 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x02 + ( ch * 0x20 ), 0x97);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x03 + ( ch * 0x20 ), 0x05);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x04 + ( ch * 0x20 ), 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x05 + ( ch * 0x20 ), 0x0a);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x06 + ( ch * 0x20 ), 0x8c);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0a + ( ch * 0x20 ), 0x03);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0b + ( ch * 0x20 ), 0xc0);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0c + ( ch * 0x20 ), 0x04);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0d + ( ch * 0x20 ), 0x4c);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x10 + ( ch * 0x20 ), 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x11 + ( ch * 0x20 ), 0x96);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x12 + ( ch * 0x20 ), 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x13 + ( ch * 0x20 ), 0x82);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x14 + ( ch * 0x20 ), 0x00);
+	gpio_i2c_write(jaguar1_i2c_addr[dev], 0x15 + ( ch * 0x20 ), 0x30);
+
+}
+
+/*****************************************************************************************************************************************
+ * Jaguar1 Video ioctl function
+ * video vi_vo initialize
+ *
+ ******************************************************************************************************************************************/
+void vd_jaguar1_vo_ch_seq_set( void *p_param)
+{
+	video_output_init *vo_seq = (video_output_init*)p_param;
+	unsigned char dev = 0;
+	unsigned char port   = vo_seq->port;
+	unsigned char out_ch = vo_seq->out_ch;
+
+	vd_vo_output_seq_set( dev, port, out_ch );
+}
+
+void vd_jaguar1_init_set( void *p_param )
+{
+	video_input_init *video_init = (video_input_init*)p_param;
+	unsigned char ch  = video_init->ch % 4;
+	unsigned char fmt = video_init->format;
+	int analog_input  = video_init->input;
+
+	video_equalizer_info_s eq_set;
+	NC_VD_COAX_STR coax_init;
+	NC_VD_VI_Init_STR *vi_param;
+	NC_VD_VO_Init_STR *vo_param;
+
+	int dev =  ch / 4 ; //{0x64, 0x60, 0x62, 0x66}//
+
+	vi_param = __NC_VD_VI_Init_Val_Get(fmt);
+	vo_param = __NC_VD_VO_Init_Val_Get(AHD20_1080P_30P);
+
+	// Each_Mode_Set
+	REG_SET_0x00_0_8_EACH_SET(ch, 0x10);
+	/*=====================================================
+	 * vd_Analog Input Setting
+	 *=====================================================*/
+	vd_jaguar1_single_differ_set(dev, ch, analog_input);
+
+	/*=====================================================
+	 * vd_vo Setting
+	 *=====================================================*/
+	vd_vo_port_y_c_merge_set( dev, ch, vo_param );
+	vd_vo_mux_mode_set( dev, ch, vo_param );
+	vd_vo_manual_mode_set(dev, ch, vo_param);
+
+	/*=====================================================
+	 * vd_vi Setting
+	 *=====================================================*/
+
+	vd_vi_manual_set_seq1( dev, ch, vi_param );
+	vd_vi_vafe_set_seq2( dev, ch );
+	vd_vi_format_set_seq3( dev, ch, vi_param );
+	vd_vi_chroma_set_seq4( dev, ch, vi_param );
+	vd_vi_h_timing_set_seq5( dev, ch, vi_param );
+	vd_vi_h_scaler_mode_set_seq6( dev, ch, vi_param );
+
+	vd_vi_hpll_set_seq7( dev, ch, vi_param );
+	vd_vi_color_set_seq8( dev, ch, vi_param, fmt);
+	vd_vo_port_ch_id_set( dev, ch, vo_param );
+	vd_vi_clock_set_seq9( dev, ch, vi_param );
+
+	/*=====================================================
+	 * AHD 1280x960P Test
+	 *
+	 *=====================================================*/
+	if( fmt == AHD20_720P_960P_30P )
+	{
+		vd_jaguar1_960p_30P_test_set( 0, ch);
+		current_bank_set(0xFF);
+	}
+	else if( fmt == AHD20_720P_960P_25P)
+	{
+		vd_jaguar1_960p_25P_test_set( 0, ch);
+		current_bank_set(0xFF);
+	}
+	else if( fmt == AHD20_SD_H960_2EX_Btype_PAL )
+	{
+		REG_SET_0x70_0_8_V_DELAY( ch, 0x3F );
+	}
+	else if( fmt == AHD20_SD_SH720_PAL || fmt == AHD20_SD_SH720_NT || fmt == AHD20_SD_H1440_PAL || fmt == AHD20_SD_H1440_NT )
+	{
+		REG_SET_0x14_0_8_FLD_INV_CHID(ch, 0x00);
+		REG_SET_0x34_0_8_Y_FIR_MODE(ch, 0x00);
+		REG_SET_1xCC_0_8_VPORT_OCLK_SEL_VPORT_OVCLK_DLY_SEL(ch, 0x40);
+		REG_SET_1xA0_0_8_TM_CLK_EN_SET(ch, 0x10);
+		REG_SET_5x21_0_8_CONT_SUB(ch, 0x24);
+		REG_SET_5x55_0_8_C_MEM_CLK_SEL(ch, 0x00);
+		REG_SET_5x56_0_8_FREQ_MEM_CLK_SEL(ch, 0x00);
+		REG_SET_5x57_0_8_LINE_MEM_CLK_INV(ch, 0x00);
+		REG_SET_5xB5_0_8_HAFC_MASK_SEL(ch, 0x00);
+		REG_SET_5xB8_0_8_HAFC_HCOEFF_SEL(ch, 0x39);
+		REG_SET_0x7C_0_8_HZOOM(ch, 0x8F);
+	}
+	else
+		printk("\n");
+
+	printk("[drv_vi]ch::%d >>> fmt::%s\n", ch, vi_param->name);
+
+	/*=====================================================
+	 * EQ Stage 0 Setting
+	 *
+	 *=====================================================*/
+#if 1
+	eq_set.Ch     = ch;
+	eq_set.FmtDef = fmt;
+	eq_set.Cable  = CABLE_A;
+	eq_set.Input  = SINGLE_ENDED;
+	eq_set.stage  = STAGE_0;
+	video_input_eq_val_set( &eq_set );
+#endif
+
+	printk("[drv_vi]ch::%d >>> fmt::%s\n", ch, vi_param->name);
+	current_bank_set(0xFF);
+
+	/*=====================================================
+	 * Coaxial Initialize
+	 *
+	 *=====================================================*/
+	coax_init.ch       = ch;
+	coax_init.vivo_fmt = fmt;
+	coax_init.vd_dev   = dev;
+	coax_tx_init( &coax_init );
+	if(acp_mode_enable == 0)
+		coax_tx_16bit_init( &coax_init );
+	coax_rx_init( &coax_init );
+
+}
+
+void vd_jaguar1_get_novideo( video_video_loss_s *vidloss )
+{
+	gpio_i2c_write(jaguar1_i2c_addr[vidloss->devnum], 0xFF, 0x00);
+	vidloss->videoloss = gpio_i2c_read(jaguar1_i2c_addr[vidloss->devnum], 0xA0);
+}
+
+void vd_jaguar1_sw_reset( void *p_param )
+{
+	//video_input_init *sw_rst = (video_input_init*)p_param;
+
+	REG_SET_1x81_0_1_VPLL_RST( 0, 0x1 );
+	REG_SET_1x80_0_1_VPLL_C( 0, 0x1 );
+	REG_SET_1x80_0_1_VPLL_C( 0, 0x0 );
+	REG_SET_1x81_0_1_VPLL_RST( 0, 0x0 );
+	printk("[drv]jaguar1_sw_reset complete!!\n");
+}
+

drivers/media/i2c/jaguar1_drv/jaguar1_video.h

@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/********************************************************************************
+ *
+ *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
+ *  Module		: video_input.c
+ *  Description	:
+ *  Author		:
+ *  Date         :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History      :
+ *
+ *
+ ********************************************************************************/
+#ifndef _JAGUAR1_VIDEO_
+#define _JAGUAR1_VIDEO_
+
+#include "jaguar1_common.h"
+
+
+/* ===============================================
+ * APP -> DRV
+ * =============================================== */
+typedef struct _video_input_init{
+	unsigned char ch;
+	unsigned char format;
+	unsigned char dist;
+	unsigned char input;
+	unsigned char val;
+	unsigned char interface;
+}video_input_init;
+
+typedef struct _video_init_all{
+	video_input_init ch_param[4];
+}video_init_all;
+
+typedef struct _video_output_init{
+	unsigned char format;
+	unsigned char port;
+	unsigned char out_ch;
+	unsigned char interface;
+}video_output_init;
+
+typedef struct _video_video_loss_s{
+	unsigned char devnum;
+	unsigned char videoloss;
+	unsigned char reserve2;
+} video_video_loss_s;
+
+extern unsigned int acp_mode_enable;
+
+void vd_jaguar1_init_set( void *p_param);
+void vd_jaguar1_vo_ch_seq_set( void *p_param);
+void vd_jaguar1_eq_set( void *p_param );
+void vd_jaguar1_sw_reset( void *p_param );
+void vd_jaguar1_get_novideo( video_video_loss_s *vidloss );
+
+void current_bank_set( unsigned char bank );
+unsigned char current_bank_get( void );
+void vd_register_set( int dev, unsigned char bank, unsigned char addr, unsigned char val, int pos, int size );
+void reg_val_print_flag_set( int set );
+
+void vd_vo_seq_set( unsigned char dev, unsigned char ch, void *p_param );
+#endif
+/********************************************************************
+ *  End of file
+ ********************************************************************/

drivers/media/i2c/jaguar1_drv/jaguar1_video_eq.c

@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0
+/********************************************************************************
+ *
+ *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
+ *  Module		: video_auto_detect.c
+ *  Description	:
+ *  Author		:
+ *  Date         :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History      :
+ *
+ *
+ ********************************************************************************/
+#include <linux/string.h>
+#include <linux/delay.h>
+
+#include "jaguar1_common.h"
+#include "jaguar1_video_eq.h"
+#include "jaguar1_cableA_video_eq_table.h"
+#include "jaguar1_reg_set_def.h"
+#include "jaguar1_video.h"
+
+//extern unsigned int jaguar1_i2c_addr[4];
+
+
+static NC_JAGUAR1_EQ NC_VD_EQ_FindFormatDef( NC_VIVO_CH_FORMATDEF format_standard, NC_ANALOG_INPUT analog_input  )
+{
+	int ii;
+
+	for(ii=0;ii<NC_EQ_SETTING_FMT_MAX;ii++)
+	{
+		_jaguar1_video_eq_value_table_s *pFmt = &equalizer_value_fmtdef_cableA[ ii ];
+
+		if( pFmt->video_fmt == format_standard )
+			if( pFmt->analog_input == analog_input )
+				return ii;
+	}
+
+	printk("NC_VD_EQ_FindFormatDef UNKNOWN format!!!\n");
+
+	return NC_EQ_SETTING_FMT_UNKNOWN;
+}
+
+static void __eq_base_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_base_s *pbase )
+{
+	unsigned char ch = pvin_eq_set->Ch;
+	unsigned char dist = pvin_eq_set->stage;
+
+	REG_SET_5x65_0_8_EQ_BYPASS( ch, pbase->eq_bypass[dist] );
+	REG_SET_5x58_0_8_EQ_BAND_SEL( ch, pbase->eq_band_sel[dist] );
+	REG_SET_5x5C_0_8_EQ_GAIN_SEL( ch, pbase->eq_gain_sel[dist] );
+	REG_SET_Ax3D_0_8_EQ_DEQ_A_ON( ch, pbase->deq_a_on[dist] );
+	REG_SET_Ax3C_0_8_EQ_DEQ_A_SEL( ch, pbase->deq_a_sel[dist] );
+
+}
+
+static void __eq_coeff_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_coeff_s *pcoeff )
+{
+
+	unsigned char ch = pvin_eq_set->Ch;
+	unsigned char dist = pvin_eq_set->stage;
+
+	REG_SET_Ax30_0_8_EQ_DEQ_A_01( ch, pcoeff->deqA_01[dist] );
+	REG_SET_Ax31_0_8_EQ_DEQ_A_02( ch, pcoeff->deqA_02[dist] );
+	REG_SET_Ax32_0_8_EQ_DEQ_A_03( ch, pcoeff->deqA_03[dist] );
+	REG_SET_Ax33_0_8_EQ_DEQ_A_04( ch, pcoeff->deqA_04[dist] );
+	REG_SET_Ax34_0_8_EQ_DEQ_A_05( ch, pcoeff->deqA_05[dist] );
+	REG_SET_Ax35_0_8_EQ_DEQ_A_06( ch, pcoeff->deqA_06[dist] );
+	REG_SET_Ax36_0_8_EQ_DEQ_A_07( ch, pcoeff->deqA_07[dist] );
+	REG_SET_Ax37_0_8_EQ_DEQ_A_08( ch, pcoeff->deqA_08[dist] );
+	REG_SET_Ax38_0_8_EQ_DEQ_A_09( ch, pcoeff->deqA_09[dist] );
+	REG_SET_Ax39_0_8_EQ_DEQ_A_10( ch, pcoeff->deqA_10[dist] );
+	REG_SET_Ax3A_0_8_EQ_DEQ_A_11( ch, pcoeff->deqA_11[dist] );
+	REG_SET_Ax3B_0_8_EQ_DEQ_A_12( ch, pcoeff->deqA_12[dist] );
+
+}
+
+static void __eq_color_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_color_s *pcolor )
+{
+	unsigned char ch = pvin_eq_set->Ch;
+	unsigned char dist = pvin_eq_set->stage;
+
+	REG_SET_0x24_0_8_EQ_COLOR_CONTRAST( ch, pcolor->contrast[dist] );
+	REG_SET_0x30_0_8_EQ_COLOR_H_PEAKING_1( ch, pcolor->y_peaking_mode[dist] );
+	REG_SET_0x34_0_8_EQ_COLOR_H_PEAKING_2( ch, pcolor->y_fir_mode[dist] );
+
+
+	REG_SET_5x31_0_8_EQ_COLOR_C_FILTER( ch, pcolor->c_filter[dist] );
+
+
+	REG_SET_0x5c_0_8_EQ_PAL_CM_OFF( ch, pcolor->pal_cm_off[dist] );
+
+	REG_SET_0x40_0_8_EQ_COLOR_HUE( ch, pcolor->hue[dist] );
+	REG_SET_0x44_0_8_EQ_COLOR_U_GAIN( ch, pcolor->u_gain[dist] );
+	REG_SET_0x48_0_8_EQ_COLOR_V_GAIN( ch, pcolor->v_gain[dist] );
+	REG_SET_0x4C_0_8_EQ_COLOR_U_OFFSET( ch, pcolor->u_offset[dist] );
+	REG_SET_0x50_0_8_EQ_COLOR_V_OFFSET( ch, pcolor->v_offset[dist] );
+	REG_SET_0x28_0_8_EQ_COLOR_BLACK_LEVEL( ch, pcolor->black_level[dist] );
+
+	REG_SET_5x27_0_8_EQ_COLOR_ACC_REF( ch, pcolor->acc_ref[dist] );
+	REG_SET_5x28_0_8_EQ_COLOR_CTI_DELAY( ch, pcolor->cti_delay[dist] );
+	REG_SET_5x2b_0_8_EQ_COLOR_SUB_SATURATION( ch, pcolor->saturation_b[dist] );
+	REG_SET_5x24_0_8_EQ_COLOR_BURST_DEC_A( ch, pcolor->burst_dec_a[dist] );
+	REG_SET_5x5F_0_8_EQ_COLOR_BURST_DEC_B( ch, pcolor->burst_dec_b[dist] );
+	REG_SET_5xD1_0_8_EQ_COLOR_BURST_DEC_C( ch, pcolor->burst_dec_c[dist] );
+	REG_SET_5xD5_0_8_EQ_COLOR_C_OPTION( ch, pcolor->c_option[dist] );
+	REG_SET_Ax25_0_8_EQ_COLOR_Y_FILTER_B( ch, pcolor->y_filter_b[dist] );
+	REG_SET_Ax27_0_8_EQ_COLOR_Y_FILTER_B_SEL( ch, pcolor->y_filter_b_sel[dist] );
+
+}
+
+static void __eq_timing_a_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_timing_a_s *ptiming_a )
+{
+	unsigned char ch = pvin_eq_set->Ch;
+	unsigned char dist = pvin_eq_set->stage;
+
+	REG_SET_0x68_0_8_EQ_TIMING_A_H_DELAY_A(ch, ptiming_a->h_delay_a[dist] );
+	REG_SET_5x38_0_8_EQ_TIMING_A_H_DELAY_B(ch, ptiming_a->h_delay_b[dist] );
+	REG_SET_0x6C_0_4_EQ_TIMING_A_H_DELAY_C(ch, ptiming_a->h_delay_c[dist] );
+
+	REG_SET_0x64_0_8_EQ_TIMING_A_Y_DELAY(ch ,  ptiming_a->y_delay[dist] );
+
+}
+
+static void __eq_clk_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_clk_s *pclk )
+{
+	unsigned char ch = pvin_eq_set->Ch;
+	unsigned char dist = pvin_eq_set->stage;
+
+	REG_SET_1x84_0_8_EQ_CLOCK_ADC_CLK( ch, pclk->clk_adc[dist] );
+	REG_SET_1x88_0_8_EQ_CLOCK_PRE_CLK( ch, pclk->clk_adc_pre[dist] );
+	REG_SET_1x8C_0_8_EQ_CLOCK_POST_CLK( ch, pclk->clk_adc_post[dist] );
+
+}
+static void __eq_timing_b_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_timing_b_s *ptiming_b )
+{
+	unsigned char ch = pvin_eq_set->Ch;
+	unsigned char dist = pvin_eq_set->stage;
+
+	REG_SET_9x96_0_8_EQ_TIMING_B_HSCALER_1( ch, ptiming_b->h_scaler1[dist] );
+	REG_SET_9x97_0_8_EQ_TIMING_B_HSCALER_2( ch, ptiming_b->h_scaler2[dist] );
+	REG_SET_9x98_0_8_EQ_TIMING_B_HSCALER_3( ch, ptiming_b->h_scaler3[dist] );
+	REG_SET_9x99_0_8_EQ_TIMING_B_HSCALER_4( ch, ptiming_b->h_scaler4[dist] );
+	REG_SET_9x9A_0_8_EQ_TIMING_B_HSCALER_5( ch, ptiming_b->h_scaler5[dist] );
+	REG_SET_9x9B_0_8_EQ_TIMING_B_HSCALER_6( ch, ptiming_b->h_scaler6[dist] );
+	REG_SET_9x9C_0_8_EQ_TIMING_B_HSCALER_7( ch, ptiming_b->h_scaler7[dist] );
+	REG_SET_9x9D_0_8_EQ_TIMING_B_HSCALER_8( ch, ptiming_b->h_scaler8[dist] );
+	REG_SET_9x9E_0_8_EQ_TIMING_B_HSCALER_9( ch, ptiming_b->h_scaler9[dist] );
+	REG_SET_9x40_0_8_EQ_TIMING_B_PN_AUTO( ch, ptiming_b->pn_auto[dist] );
+	REG_SET_5x90_0_8_EQ_TIMINING_B_COMB_MODE( ch, ptiming_b->comb_mode[dist] );
+	REG_SET_5xB9_0_8_EQ_TIMING_B_HPLL_OP_A( ch, ptiming_b->h_pll_op_a[dist] );
+	REG_SET_5x57_0_8_EQ_TIMING_B_MEM_PATH( ch, ptiming_b->mem_path[dist] );
+	REG_SET_5x25_0_8_EQ_TIMING_B_FSC_LOCK_SPD( ch, ptiming_b->fsc_lock_speed[dist] );
+
+	REG_SET_0x04_0_8_EQ_TIMING_B_SD_MD( ch, ptiming_b->sd_mode[dist] );
+	REG_SET_0x08_0_8_EQ_TIMING_B_AHD_MD( ch, ptiming_b->ahd_mode[dist] );
+	REG_SET_0x0C_0_8_EQ_TIMING_B_SPECIAL_MD( ch, ptiming_b->spl_mode[dist] );
+	REG_SET_0x78_0_8_EQ_TIMING_B_VBLK_END( ch, ptiming_b->vblk_end[dist] );
+
+	REG_SET_5x1D_0_8_EQ_AFE_G_SEL( ch, ptiming_b->afe_g_sel[dist] );
+	REG_SET_5x01_0_8_EQ_AFE_CTR_CLP( ch, ptiming_b->afe_ctr_clp[dist] );
+	REG_SET_5x05_0_8_EQ_D_AGC_OPTION( ch, ptiming_b->d_agc_option[dist] );
+
+}
+
+void video_input_eq_val_set(video_equalizer_info_s *pvin_eq_set)
+{
+	NC_JAGUAR1_EQ eq_fmt;
+	unsigned char ch = pvin_eq_set->Ch;
+	int fmt = pvin_eq_set->FmtDef;
+	int input = pvin_eq_set->Input;
+	int cable = pvin_eq_set->Cable;
+	/* int stage = pvin_eq_set->stage; */
+	_jaguar1_video_eq_value_table_s eq_value;
+
+	//	printk("[drv_eq]ch%d >> fmt(%d) cable(%d) stage(%d) input(%d)\n", ch, fmt, cable, stage, input);
+	eq_fmt = NC_VD_EQ_FindFormatDef( fmt, input );
+
+	if( cable == CABLE_A )
+		eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
+	else if( cable == CABLE_B )
+		eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
+	else if( cable == CABLE_C )
+		eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
+	else if( cable == CABLE_D )
+		eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
+	else
+		eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
+
+	if( eq_value.name == NULL )
+	{
+		printk("[drv_eq]Error - Unknown EQ Table!!\n");
+		return;
+	}
+	else
+	{
+		/* set_eq_value */
+		__eq_base_set_value( pvin_eq_set, &eq_value.eq_base );
+		__eq_coeff_set_value( pvin_eq_set, &eq_value.eq_coeff );
+		__eq_color_set_value( pvin_eq_set, &eq_value.eq_color);
+		__eq_timing_a_set_value( pvin_eq_set, &eq_value.eq_timing_a );
+		__eq_clk_set_value( pvin_eq_set, &eq_value.eq_clk );
+		__eq_timing_b_set_value( pvin_eq_set, &eq_value.eq_timing_b );
+
+		if( AHD20_SD_H960_2EX_Btype_NT_SINGLE_ENDED || AHD20_SD_H960_2EX_Btype_NT_DIFFERENTIAL )
+		{
+
+		}
+		else if( AHD20_SD_H960_2EX_Btype_PAL_SINGLE_ENDED || AHD20_SD_H960_2EX_Btype_PAL_DIFFERENTIAL )
+		{
+
+		}
+		else
+		{
+
+		}
+		printk("[drv_eq]ch::%d >>> fmt::%s\n", ch, eq_value.name);
+	}
+}
+
+
+void video_input_eq_cable_set(video_equalizer_info_s *pvin_eq_set)
+{
+	unsigned char ch = pvin_eq_set->Ch;
+	int cable = pvin_eq_set->Cable;
+
+	printk("[DRV]video_input_eq_cable_set::ch(%d) cable(%d)\n", ch, cable );
+}
+
+void video_input_eq_analog_input_set(video_equalizer_info_s *pvin_eq_set)
+{
+	unsigned char ch = pvin_eq_set->Ch;
+	int input = pvin_eq_set->Input;
+
+	REG_SET_0x18_0_8_EX_CBAR_ON( ch, 0x13 );
+
+	if( input == DIFFERENTIAL )
+	{
+		REG_SET_5x00_0_8_CMP( ch, 0xd0 );
+		REG_SET_5x01_0_8_CML( ch, 0x2c );
+		REG_SET_5x1D_0_8_AFE( ch, 0x8c );
+		REG_SET_5x92_0_8_PWM( ch, 0x00 );
+	}
+	else if( input == SINGLE_ENDED )
+	{
+		REG_SET_5x00_0_8_CMP( ch, 0xd0 );
+		REG_SET_5x01_0_8_CML( ch, 0xa2 );
+		//		REG_SET_5x1D_0_8_AFE( ch, 0x00 );
+		REG_SET_5x92_0_8_PWM( ch, 0x00 );
+	}
+	else
+	{
+		printk("Jaguar1 Analog Input Setting Fail !!!\n");
+	}
+
+	printk("[DRV]video_input_eq_analog_input_set::ch(%d) input(%d)\n", ch, input );
+}
+

drivers/media/i2c/jaguar1_drv/jaguar1_video_eq.h

@@ -0,0 +1,170 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/********************************************************************************
+ *
+ *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
+ *  Module		: video_eq.h
+ *  Description	:
+ *  Author		:
+ *  Date         :
+ *  Version		: Version 1.0
+ *
+ ********************************************************************************
+ *  History      :
+ *
+ *
+ ********************************************************************************/
+#ifndef _JAGUAR1_VIDEO_EQ_H_
+#define _JAGUAR1_VIDEO_EQ_H_
+
+#include "jaguar1_common.h"
+
+typedef struct _video_equalizer_hsync_stage_s{
+	unsigned int hsync_stage[6];
+}video_equalizer_hsync_stage_s;
+
+typedef struct _video_equalizer_agc_stage_s{
+	unsigned int agc_stage[6];
+}video_equalizer_agc_stage_s;
+
+typedef struct _video_equalizer_distance_table_s{
+	video_equalizer_hsync_stage_s hsync_stage;
+	video_equalizer_agc_stage_s   agc_stage;
+} video_equalizer_distance_table_s;
+
+
+typedef struct _video_equalizer_base_s{
+	unsigned char eq_bypass[11];			// B5x01
+	unsigned char eq_band_sel[11];		// B5x58
+	unsigned char eq_gain_sel[11];		// B5x5C
+
+	unsigned char deq_a_on[11];			// BAx3d
+	unsigned char deq_a_sel[11];			// BAx3C
+
+} video_equalizer_base_s;
+
+typedef struct _video_equalizer_coeff_s{
+
+	unsigned char deqA_01[11];	// BankA 0x30
+	unsigned char deqA_02[11];	// BankA 0x31
+	unsigned char deqA_03[11];   // BankA 0x32
+	unsigned char deqA_04[11];   // BankA 0x33
+	unsigned char deqA_05[11];   // BankA 0x34
+	unsigned char deqA_06[11];   // BankA 0x35
+	unsigned char deqA_07[11];   // BankA 0x36
+	unsigned char deqA_08[11];   // BankA 0x37
+	unsigned char deqA_09[11];   // BankA 0x38
+	unsigned char deqA_10[11];   // BankA 0x39
+	unsigned char deqA_11[11];   // BankA 0x3A
+	unsigned char deqA_12[11];   // BankA 0x3B
+
+} video_equalizer_coeff_s;
+
+typedef struct _video_equalizer_color_s{
+	unsigned char contrast[11];			// Bank0 0x10
+	unsigned char y_peaking_mode[11];			// Bank0 0x18
+	unsigned char y_fir_mode [11];
+	unsigned char c_filter[11];			// Bank0 0x21
+	unsigned char pal_cm_off[11];			// Bank0 0x21
+	unsigned char hue[11];				// Bank0 0x40
+	unsigned char u_gain[11];			// Bank0 0x44
+	unsigned char v_gain[11];			// Bank0 0x48
+	unsigned char u_offset[11];			// Bank0 0x4c
+	unsigned char v_offset[11];			// Bank0 0x50
+
+	unsigned char black_level[11];		// Bank5 0x20
+	unsigned char acc_ref[11];			// Bank5 0x27
+
+	unsigned char cti_delay[11];			// Bank5 0x28
+	unsigned char saturation_b[11];    // Bank5 0x2B
+	unsigned char burst_dec_a[11];       // Bank5 0x24
+	unsigned char burst_dec_b[11];       // Bank5 0x5F
+	unsigned char burst_dec_c[11];       // Bank5 0xD1
+	unsigned char c_option[11];          // Bank5 0xD5
+
+	unsigned char y_filter_b[11];		// BankA 0x25
+	unsigned char y_filter_b_sel[11];	// BankA 0x27
+
+} video_equalizer_color_s;
+
+typedef struct _video_equalizer_timing_a_s{
+	unsigned char h_delay_a[11];			// Bank0 0x58
+	unsigned char h_delay_b[11];			// Bank0 0x89
+	unsigned char h_delay_c[11];			// Bank0 0x8E
+	unsigned char y_delay[11];			// Bank0 0xA0
+
+} video_equalizer_timing_a_s;
+
+typedef struct _video_equalizer_clk_s{
+	unsigned char clk_adc_pre[11];			// Bank1 0x84
+	unsigned char clk_adc_post[11];			// Bank1 0x8C
+	unsigned char clk_adc[11];			// Bank1 0x8C
+
+} video_equalizer_clk_s;
+
+typedef struct _video_equalizer_timing_b_s{
+	unsigned char h_scaler1[11];		// B9x96 + ch*0x20
+	unsigned char h_scaler2[11];		// B9x97 + ch*0x20
+	unsigned char h_scaler3[11];		// B9x98 + ch*0x20
+	unsigned char h_scaler4[11];		// B9x99 + ch*0x20
+	unsigned char h_scaler5[11];		// B9x9a + ch*0x20
+	unsigned char h_scaler6[11];		// B9x9b + ch*0x20
+	unsigned char h_scaler7[11];		// B9x9c + ch*0x20
+	unsigned char h_scaler8[11];		// B9x9d + ch*0x20
+	unsigned char h_scaler9[11];		// B9x9e + ch*0x20
+
+	unsigned char pn_auto[11];		// B9x40 + ch
+
+	unsigned char comb_mode[11];		// B5x90
+	unsigned char h_pll_op_a[11];	// B5xB9
+	unsigned char mem_path[11];		// B5x57
+	unsigned char fsc_lock_speed[11]; //B5x25
+
+	unsigned char ahd_mode[11];
+	unsigned char sd_mode[11];
+	unsigned char spl_mode[11];
+	unsigned char vblk_end[11];
+	unsigned char afe_g_sel[11];
+	unsigned char afe_ctr_clp[11];
+	unsigned char d_agc_option[11];
+} video_equalizer_timing_b_s;
+
+
+typedef struct _video_equalizer_value_table_s{
+	video_equalizer_base_s		eq_base;
+	video_equalizer_coeff_s 	eq_coeff;
+	video_equalizer_color_s 	eq_color;
+
+	video_equalizer_timing_a_s 	eq_timing_a;
+	video_equalizer_clk_s		eq_clk;
+	video_equalizer_timing_b_s	eq_timing_b;
+
+} video_equalizer_value_table_s;
+
+typedef struct _jaguar1_video_eq_value_table_s{
+	char *name;
+	NC_VIVO_CH_FORMATDEF		video_fmt;
+	NC_ANALOG_INPUT 			analog_input;
+	video_equalizer_base_s		eq_base;
+	video_equalizer_coeff_s 	eq_coeff;
+	video_equalizer_color_s 	eq_color;
+
+	video_equalizer_timing_a_s 	eq_timing_a;
+	video_equalizer_clk_s		eq_clk;
+	video_equalizer_timing_b_s	eq_timing_b;
+
+} _jaguar1_video_eq_value_table_s;
+
+typedef struct _video_equalizer_info{
+	unsigned char Ch;
+	unsigned char devnum;
+	unsigned char stage;
+	unsigned char FmtDef;
+	unsigned char Cable;
+	unsigned char Input;
+} video_equalizer_info_s;
+
+void video_input_eq_val_set(video_equalizer_info_s *pvin_eq_set);
+void video_input_eq_cable_set(video_equalizer_info_s *pvin_eq_set);
+void video_input_eq_analog_input_set(video_equalizer_info_s *pvin_eq_set);
+
+#endif /* _JAGUAR1_VIDEO_EQ_H_ */