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drm/amdgpu: move amdgpu_acpi helpers into new header
Move struct amdgpu_uma_carveout_option, struct amdgpu_uma_carveout_info, struct amdgpu_numa_info, and relevant acpi helpers from the monolithic amdgpu.h header file into a new amdgpu_acpi.h file. This is part of the ongoing effort to reduce the size of amdgpu.h into their own respective separate headers. Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Shahyan Soltani
Alex Deucher
parent
a733b7bee1
commit
45c0a9ee90
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@ -115,6 +115,7 @@
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#include "amdgpu_ip.h"
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#include "amdgpu_mes.h"
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#include "amdgpu_sa.h"
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#include "amdgpu_acpi.h"
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#include "amdgpu_video_codecs.h"
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#if defined(CONFIG_DRM_AMD_ISP)
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#include "amdgpu_isp.h"
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@ -137,13 +138,6 @@ struct amdgpu_mgpu_info {
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uint32_t num_apu;
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};
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enum amdgpu_ss {
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AMDGPU_SS_DRV_LOAD,
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AMDGPU_SS_DEV_D0,
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AMDGPU_SS_DEV_D3,
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AMDGPU_SS_DRV_UNLOAD
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};
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struct amdgpu_hwip_reg_entry {
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u32 hwip;
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u32 inst;
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@ -547,38 +541,6 @@ struct amdgpu_uid {
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struct amdgpu_device *adev;
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};
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#define MAX_UMA_OPTION_NAME 28
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#define MAX_UMA_OPTION_ENTRIES 19
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#define AMDGPU_UMA_FLAG_AUTO BIT(1)
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#define AMDGPU_UMA_FLAG_CUSTOM BIT(0)
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/**
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* struct amdgpu_uma_carveout_option - single UMA carveout option
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* @name: Name of the carveout option
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* @memory_carved_mb: Amount of memory carved in MB
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* @flags: ATCS flags supported by this option
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*/
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struct amdgpu_uma_carveout_option {
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char name[MAX_UMA_OPTION_NAME];
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uint32_t memory_carved_mb;
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uint8_t flags;
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};
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/**
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* struct amdgpu_uma_carveout_info - table of available UMA carveout options
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* @num_entries: Number of available options
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* @uma_option_index: The index of the option currently applied
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* @update_lock: Lock to serialize changes to the option
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* @entries: The array of carveout options
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*/
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struct amdgpu_uma_carveout_info {
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uint8_t num_entries;
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uint8_t uma_option_index;
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struct mutex update_lock;
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struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES];
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};
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struct amd_powerplay {
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void *pp_handle;
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const struct amd_pm_funcs *pp_funcs;
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@ -1325,88 +1287,6 @@ struct amdgpu_afmt_acr {
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struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
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/* amdgpu_acpi.c */
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struct amdgpu_numa_info {
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uint64_t size;
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int pxm;
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int nid;
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};
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/* ATCS Device/Driver State */
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#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
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#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
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#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
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#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
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#if defined(CONFIG_ACPI)
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int amdgpu_acpi_init(struct amdgpu_device *adev);
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void amdgpu_acpi_fini(struct amdgpu_device *adev);
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bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
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bool amdgpu_acpi_is_power_shift_control_supported(void);
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bool amdgpu_acpi_is_set_uma_allocation_size_supported(void);
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int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
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u8 perf_req, bool advertise);
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int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
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u8 dev_state, bool drv_state);
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int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,
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enum amdgpu_ss ss_state);
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int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type);
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int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
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int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
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u64 *tmr_size);
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int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
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struct amdgpu_numa_info *numa_info);
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void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
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bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
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void amdgpu_acpi_detect(void);
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void amdgpu_acpi_release(void);
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#else
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static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
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static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
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u64 *tmr_offset, u64 *tmr_size)
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{
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return -EINVAL;
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}
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static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
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int xcc_id,
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struct amdgpu_numa_info *numa_info)
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{
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return -EINVAL;
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}
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static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
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static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
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static inline void amdgpu_acpi_detect(void) { }
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static inline void amdgpu_acpi_release(void) { }
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static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
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static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; }
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static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
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u8 dev_state, bool drv_state) { return 0; }
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static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,
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enum amdgpu_ss ss_state)
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{
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return 0;
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}
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static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type)
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{
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return -EINVAL;
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}
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static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { }
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#endif
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#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
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bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
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bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
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#else
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static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
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static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
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#endif
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#if defined(CONFIG_DRM_AMD_ISP)
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int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev);
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#endif
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void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
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void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
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151
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h
Normal file
151
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h
Normal file
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@ -0,0 +1,151 @@
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/* SPDX-License-Identifier: GPL-2.0 OR MIT
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*
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* Copyright 2026 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMDGPU_ACPI_H__
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#define __AMDGPU_ACPI_H__
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#include <linux/types.h>
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#include <linux/mutex_types.h>
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struct amdgpu_device;
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struct acpi_device;
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struct amdgpu_dm_backlight_caps;
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#define MAX_UMA_OPTION_NAME 28
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#define MAX_UMA_OPTION_ENTRIES 19
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#define AMDGPU_UMA_FLAG_AUTO BIT(1)
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#define AMDGPU_UMA_FLAG_CUSTOM BIT(0)
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/* ATCS Device/Driver State */
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#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
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#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
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#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
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#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
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enum amdgpu_ss {
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AMDGPU_SS_DRV_LOAD,
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AMDGPU_SS_DEV_D0,
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AMDGPU_SS_DEV_D3,
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AMDGPU_SS_DRV_UNLOAD
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};
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/**
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* struct amdgpu_uma_carveout_option - single UMA carveout option
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* @name: Name of the carveout option
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* @memory_carved_mb: Amount of memory carved in MB
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* @flags: ATCS flags supported by this option
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*/
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struct amdgpu_uma_carveout_option {
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char name[MAX_UMA_OPTION_NAME];
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uint32_t memory_carved_mb;
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uint8_t flags;
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};
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/**
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* struct amdgpu_uma_carveout_info - table of available UMA carveout options
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* @num_entries: Number of available options
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* @uma_option_index: The index of the option currently applied
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* @update_lock: Lock to serialize changes to the option
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* @entries: The array of carveout options
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*/
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struct amdgpu_uma_carveout_info {
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uint8_t num_entries;
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uint8_t uma_option_index;
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struct mutex update_lock;
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struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES];
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};
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struct amdgpu_numa_info {
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uint64_t size;
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int pxm;
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int nid;
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};
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#if defined(CONFIG_ACPI)
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int amdgpu_acpi_init(struct amdgpu_device *adev);
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void amdgpu_acpi_fini(struct amdgpu_device *adev);
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bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
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bool amdgpu_acpi_is_power_shift_control_supported(void);
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bool amdgpu_acpi_is_set_uma_allocation_size_supported(void);
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int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
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u8 perf_req, bool advertise);
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int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
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u8 dev_state, bool drv_state);
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int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,
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enum amdgpu_ss ss_state);
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int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type);
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int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
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int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
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u64 *tmr_size);
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int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
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struct amdgpu_numa_info *numa_info);
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void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
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bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
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void amdgpu_acpi_detect(void);
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void amdgpu_acpi_release(void);
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#else
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static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
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static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
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u64 *tmr_offset, u64 *tmr_size)
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{
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return -EINVAL;
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}
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static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
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int xcc_id,
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struct amdgpu_numa_info *numa_info)
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{
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return -EINVAL;
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}
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static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
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static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
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static inline void amdgpu_acpi_detect(void) { }
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static inline void amdgpu_acpi_release(void) { }
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static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
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static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; }
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static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
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u8 dev_state, bool drv_state) { return 0; }
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static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,
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enum amdgpu_ss ss_state)
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{
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return 0;
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}
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static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type)
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{
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return -EINVAL;
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}
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static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { }
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#endif
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#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
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bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
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bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
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#else
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static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
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static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
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#endif
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#if defined(CONFIG_DRM_AMD_ISP)
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int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev);
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#endif
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#endif /* __AMDGPU_ACPI_H__ */
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