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drm/amd/display: Ensure link output is disabled in backend reset for PLL_ON
[Why] We're missing the code to actually disable the link output when we have to leave the SYMCLK_ON but the TX remains OFF. [How] Port the code from DCN401 that detects SYMCLK_ON_TX_OFF and disable the link output when the backend is reset. Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -546,8 +546,22 @@ static void dcn31_reset_back_end_for_pipe(
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if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
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pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
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pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
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/*
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* TODO - convert symclk_ref_cnts for otg to a bit map to solve
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* the case where the same symclk is shared across multiple otg
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* instances
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*/
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if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
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pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
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link->phy_state.symclk_ref_cnts.otg = 0;
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if (pipe_ctx->top_pipe == NULL) {
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if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
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const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
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link_hwss->disable_link_output(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
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link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
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}
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}
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set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);
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