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crypto: drivers - fix typos in comments

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Fix typos in comments, reported by scripts/checkpatch.pl using the
misspelling list in scripts/spelling.txt.  Only touches comments, no code
changes.

Assisted-by: Cursor:claude-opus-5
Signed-off-by: Hemanth Selam <hemanth.selam@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Hemanth Selam 2026-09-04 17:13:39 +05:30 committed by Herbert Xu
parent f69442515f
commit 45889add0c
12 changed files with 23 additions and 23 deletions
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4
drivers/crypto/atmel-sha.c
View File

@ -1203,7 +1203,7 @@ static int atmel_sha_finup(struct ahash_request *req)
/*
* final() has to be always called to cleanup resources
* even if udpate() failed, except EINPROGRESS
* even if update() failed, except EINPROGRESS
*/
err2 = atmel_sha_final(req);
@ -1338,7 +1338,7 @@ static int atmel_sha_done(struct atmel_sha_dev *dd)
return err;
finish:
/* finish curent request */
/* finish current request */
atmel_sha_finish_req(dd->req, err);
return err;

12
drivers/crypto/cavium/cpt/cptpf_main.c
View File

@ -90,19 +90,19 @@ static void cpt_configure_group(struct cpt_device *cpt, u8 grp,
static void cpt_disable_mbox_interrupts(struct cpt_device *cpt)
{
/* Clear mbox(0) interupts for all vfs */
/* Clear mbox(0) interrupts for all vfs */
cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1CX(0, 0), ~0ull);
}
static void cpt_disable_ecc_interrupts(struct cpt_device *cpt)
{
/* Clear ecc(0) interupts for all vfs */
/* Clear ecc(0) interrupts for all vfs */
cpt_write_csr64(cpt->reg_base, CPTX_PF_ECC0_ENA_W1C(0), ~0ull);
}
static void cpt_disable_exec_interrupts(struct cpt_device *cpt)
{
/* Clear exec interupts for all vfs */
/* Clear exec interrupts for all vfs */
cpt_write_csr64(cpt->reg_base, CPTX_PF_EXEC_ENA_W1C(0), ~0ull);
}
@ -115,7 +115,7 @@ static void cpt_disable_all_interrupts(struct cpt_device *cpt)
static void cpt_enable_mbox_interrupts(struct cpt_device *cpt)
{
/* Set mbox(0) interupts for all vfs */
/* Set mbox(0) interrupts for all vfs */
cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1SX(0, 0), ~0ull);
}
@ -140,10 +140,10 @@ static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode)
*/
if (mcode->is_ae) {
core = CPT_MAX_SE_CORES; /* start couting from 10 */
total_cores = CPT_MAX_TOTAL_CORES; /* upto 15 */
total_cores = CPT_MAX_TOTAL_CORES; /* up to 15 */
} else {
core = 0; /* start couting from 0 */
total_cores = CPT_MAX_SE_CORES; /* upto 9 */
total_cores = CPT_MAX_SE_CORES; /* up to 9 */
}
/* Point to microcode for each core of the group */

4
drivers/crypto/cavium/cpt/cptvf_main.c
View File

@ -417,7 +417,7 @@ static void cptvf_enable_swerr_interrupts(struct cpt_vf *cptvf)
vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base,
CPTX_VQX_MISC_ENA_W1S(0, 0));
/* Set mbox(0) interupts for the requested vf */
/* Set mbox(0) interrupts for the requested vf */
vqx_misc_ena.s.swerr = 1;
cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0),
vqx_misc_ena.u);
@ -429,7 +429,7 @@ static void cptvf_enable_mbox_interrupts(struct cpt_vf *cptvf)
vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base,
CPTX_VQX_MISC_ENA_W1S(0, 0));
/* Set mbox(0) interupts for the requested vf */
/* Set mbox(0) interrupts for the requested vf */
vqx_misc_ena.s.mbox = 1;
cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0),
vqx_misc_ena.u);

4
drivers/crypto/cavium/cpt/cptvf_mbox.c
View File

@ -120,7 +120,7 @@ int cptvf_send_vq_size_msg(struct cpt_vf *cptvf)
}
/*
* Communicate VF group required to PF and get the VQ binded to that group
* Communicate VF group required to PF and get the VQ bound to that group
*/
int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf)
{
@ -139,7 +139,7 @@ int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf)
}
/*
* Communicate VF group required to PF and get the VQ binded to that group
* Communicate VF group required to PF and get the VQ bound to that group
*/
int cptvf_send_vf_priority_msg(struct cpt_vf *cptvf)
{

2
drivers/crypto/cavium/nitrox/nitrox_main.c
View File

@ -468,7 +468,7 @@ static int nitrox_probe(struct pci_dev *pdev,
err = -EIO;
goto ioremap_err;
}
/* allocate command queus based on cpus, max queues are 64 */
/* allocate command queues based on cpus, max queues are 64 */
ndev->nr_queues = min_t(u32, MAX_PF_QUEUES, num_online_cpus());
ndev->qlen = qlen;

2
drivers/crypto/ccp/ccp-dev.c
View File

@ -30,7 +30,7 @@
#define MAX_CCPS 32
/* Limit CCP use to a specifed number of queues per device */
/* Limit CCP use to a specified number of queues per device */
static unsigned int nqueues;
module_param(nqueues, uint, 0444);
MODULE_PARM_DESC(nqueues, "Number of queues per CCP (minimum 1; default: all available)");

4
drivers/crypto/ccree/cc_buffer_mgr.c
View File

@ -717,7 +717,7 @@ static void cc_prepare_aead_data_mlli(struct cc_drvdata *drvdata,
}
} else { /* Contig. ICV */
sg = &areq_ctx->src_sgl[areq_ctx->src.nents - 1];
/*Should hanlde if the sg is not contig.*/
/*Should handle if the sg is not contig.*/
areq_ctx->icv_dma_addr = sg_dma_address(sg) +
(*src_last_bytes - authsize);
areq_ctx->icv_virt_addr = sg_virt(sg) +
@ -749,7 +749,7 @@ static void cc_prepare_aead_data_mlli(struct cc_drvdata *drvdata,
} else { /* Contig. ICV */
sg = &areq_ctx->src_sgl[areq_ctx->src.nents - 1];
/*Should hanlde if the sg is not contig.*/
/*Should handle if the sg is not contig.*/
areq_ctx->icv_dma_addr = sg_dma_address(sg) +
(*src_last_bytes - authsize);
areq_ctx->icv_virt_addr = sg_virt(sg) +

2
drivers/crypto/chelsio/chcr_algo.c
View File

@ -1605,7 +1605,7 @@ static struct sk_buff *create_hash_wr(struct ahash_request *req,
req_ctx->hctx_wr.dma_addr = 0;
}
chcr_add_hash_src_ent(req, ulptx, param);
/* Request upto max wr size */
/* Request up to max wr size */
temp = param->kctx_len + DUMMY_BYTES + (req_ctx->hctx_wr.imm ?
(param->sg_len + param->bfr_len) : 0);
atomic_inc(&adap->chcr_stats.digest_rqst);

4
drivers/crypto/marvell/octeontx/otx_cptvf_mbox.c
View File

@ -180,7 +180,7 @@ int otx_cptvf_send_vq_size_msg(struct otx_cptvf *cptvf)
}
/*
* Communicate VF group required to PF and get the VQ binded to that group
* Communicate VF group required to PF and get the VQ bound to that group
*/
int otx_cptvf_send_vf_to_grp_msg(struct otx_cptvf *cptvf, int group)
{
@ -199,7 +199,7 @@ int otx_cptvf_send_vf_to_grp_msg(struct otx_cptvf *cptvf, int group)
}
/*
* Communicate VF group required to PF and get the VQ binded to that group
* Communicate VF group required to PF and get the VQ bound to that group
*/
int otx_cptvf_send_vf_priority_msg(struct otx_cptvf *cptvf)
{

4
drivers/crypto/omap-sham.c
View File

@ -1265,7 +1265,7 @@ static int omap_sham_finup(struct ahash_request *req)
return err1;
/*
* final() has to be always called to cleanup resources
* even if udpate() failed, except EINPROGRESS
* even if update() failed, except EINPROGRESS
*/
err2 = omap_sham_final(req);
@ -1732,7 +1732,7 @@ static void omap_sham_done_task(struct work_struct *t)
finish:
dev_dbg(dd->dev, "update done: err: %d\n", err);
/* finish curent request */
/* finish current request */
omap_sham_finish_req(dd->req, err);
}

2
drivers/crypto/qce/aead.c
View File

@ -379,7 +379,7 @@ static int qce_aead_create_ccm_nonce(struct qce_aead_reqctx *rctx, struct qce_ae
/*
* The crypto framework encodes cryptlen as unsigned int. Thus, even though
* spec allows for upto 8 bytes to encode msg_len only 4 bytes are needed.
* spec allows for up to 8 bytes to encode msg_len only 4 bytes are needed.
*/
if (msglen_size > 4)
msglen_size = 4;

2
drivers/crypto/s5p-sss.c
View File

@ -1445,7 +1445,7 @@ static void s5p_hash_tasklet_cb(unsigned long data)
return;
finish:
/* finish curent request */
/* finish current request */
s5p_hash_finish_req(dd->hash_req, 0);
/* If we are not busy, process next req */