From 456027325c9cd2be94229687f2c412ae6f351bd8 Mon Sep 17 00:00:00 2001 From: Ivan Vecera Date: Sun, 11 Oct 2026 08:12:09 +0200 Subject: [PATCH] dpll: zl3073x: reject output frequencies with too small divisor The output divisor has to be at least 2: a divisor of 1 bypasses the divider and the hardware then ignores the pulse width and eSync registers. For the N-pin of an N-divided output the N divider (>= 2) applies on top, so its effective divisor has to be at least 4. zl3073x_pin_check_freq() only checked that the frequency divides the synth frequency. Require also the minimum divisor. For N-divided outputs this is necessary but not sufficient, the rest is checked by the frequency set callback. Hit during development: an N-pin frequency that needs an N divider of 1 was accepted, and with esync_n_period = 1 the N-pin produced no output on an oscilloscope. Fixes: a99a9f0ebdaa ("dpll: zl3073x: Read DPLL types and pin properties from system firmware") Reviewed-by: Petr Oros Signed-off-by: Ivan Vecera Link: https://patch.msgid.link/20261011061211.448373-4-ivecera@redhat.com Signed-off-by: Jakub Kicinski --- drivers/dpll/zl3073x/prop.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/dpll/zl3073x/prop.c b/drivers/dpll/zl3073x/prop.c index 768e5424de2d..4e006ed5950a 100644 --- a/drivers/dpll/zl3073x/prop.c +++ b/drivers/dpll/zl3073x/prop.c @@ -22,7 +22,8 @@ * The function checks the given frequency is valid for the device. For input * pins it checks that the frequency can be factorized using supported base * frequencies. For output pins it checks that the frequency divides connected - * synth frequency without remainder. + * synth frequency without remainder and that the resulting divisor is not + * below the minimum the driver supports. * * Return: true if the frequency is valid, false if not. */ @@ -41,18 +42,38 @@ zl3073x_pin_check_freq(struct zl3073x_dev *zldev, enum dpll_pin_direction dir, if (rc) goto err_inv_freq; } else { - u32 synth_freq; - u8 out, synth; + u32 synth_freq, div, min_div, rem; + const struct zl3073x_out *out; + u8 out_id, synth; /* Get output pin synthesizer */ - out = zl3073x_output_pin_out_get(id); - synth = zl3073x_dev_out_synth_get(zldev, out); + out_id = zl3073x_output_pin_out_get(id); + synth = zl3073x_dev_out_synth_get(zldev, out_id); /* Get synth frequency */ synth_freq = zl3073x_dev_synth_freq_get(zldev, synth); /* Check the frequency divides synth frequency */ - if (synth_freq % (u32)freq) + div = div_u64_rem(synth_freq, freq, &rem); + if (rem) + goto err_inv_freq; + + /* The driver requires an output divisor of at least 2 - + * below that the hardware bypasses the divider and ignores + * the pulse width and eSync registers the driver programs. + * For the N-pin of an N-divided output the effective divisor + * also includes the N divider (>= 2), so the minimum is 4. + * For N-divided outputs this is only a necessary condition - + * whether the frequency can be set also depends on the output + * divisor shared by both pins, which is checked when the + * frequency is set. + */ + out = zl3073x_out_state_get(zldev, out_id); + if (zl3073x_out_is_ndiv(out) && zl3073x_is_n_pin(id)) + min_div = 4; + else + min_div = 2; + if (div < min_div) goto err_inv_freq; }