ARM: dts: qcom: msm8960: Add GSBI2 & GSBI7

Add the GSBI2 & GSBI7 Node, which is similar to the
other GSBI nodes in this file.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Rudraksha Gupta <guptarud@gmail.com>
Link: https://lore.kernel.org/r/20251124-expressatt_nfc_accel_magn_light-v4-1-9c5686ad67e2@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Rudraksha Gupta 2025-11-24 15:35:22 -08:00 committed by Bjorn Andersson
parent df7c440c90
commit 4535af3dc9

View File

@ -149,6 +149,24 @@ i2c1-pins {
};
};
i2c2_default_state: i2c2-default-state {
i2c2-pins {
pins = "gpio12", "gpio13";
function = "gsbi2";
drive-strength = <8>;
bias-disable;
};
};
i2c2_sleep_state: i2c2-sleep-state {
i2c2-pins {
pins = "gpio12", "gpio13";
function = "gpio";
drive-strength = <2>;
bias-bus-hold;
};
};
i2c3_default_state: i2c3-default-state {
i2c3-pins {
pins = "gpio16", "gpio17";
@ -167,6 +185,24 @@ i2c3-pins {
};
};
i2c7_default_state: i2c7-default-state {
i2c7-pins {
pins = "gpio32", "gpio33";
function = "gsbi7";
drive-strength = <8>;
bias-disable;
};
};
i2c7_sleep_state: i2c7-sleep-state {
i2c7-pins {
pins = "gpio32", "gpio33";
function = "gpio";
drive-strength = <2>;
bias-bus-hold;
};
};
i2c8_default_state: i2c8-default-state {
i2c8-pins {
pins = "gpio36", "gpio37";
@ -543,6 +579,36 @@ gsbi1_spi: spi@16080000 {
};
};
gsbi2: gsbi@16100000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x16100000 0x100>;
ranges;
cell-index = <2>;
clocks = <&gcc GSBI2_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
gsbi2_i2c: i2c@16180000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x16180000 0x1000>;
pinctrl-0 = <&i2c2_default_state>;
pinctrl-1 = <&i2c2_sleep_state>;
pinctrl-names = "default", "sleep";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI2_QUP_CLK>,
<&gcc GSBI2_H_CLK>;
clock-names = "core",
"iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gsbi3: gsbi@16200000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x16200000 0x100>;
@ -600,6 +666,36 @@ gsbi5_serial: serial@16440000 {
};
};
gsbi7: gsbi@16600000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x16600000 0x100>;
ranges;
cell-index = <7>;
clocks = <&gcc GSBI7_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
gsbi7_i2c: i2c@16680000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x16680000 0x1000>;
pinctrl-0 = <&i2c7_default_state>;
pinctrl-1 = <&i2c7_sleep_state>;
pinctrl-names = "default", "sleep";
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI7_QUP_CLK>,
<&gcc GSBI7_H_CLK>;
clock-names = "core",
"iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gsbi8: gsbi@1a000000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x1a000000 0x100>;