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drm/nouveau/ltc: split color vs depth/stencil zbc counts

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These differ on Ampere.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2022-06-01 20:48:03 +10:00
parent 1ed02c3f2d
commit 4500031f86
13 changed files with 42 additions and 27 deletions
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15
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
View File

@ -4,7 +4,8 @@
#include <core/subdev.h>
#include <core/mm.h>
#define NVKM_LTC_MAX_ZBC_CNT 16
#define NVKM_LTC_MAX_ZBC_COLOR_CNT 16
#define NVKM_LTC_MAX_ZBC_DEPTH_CNT 16
struct nvkm_ltc {
const struct nvkm_ltc_func *func;
@ -18,11 +19,13 @@ struct nvkm_ltc {
u32 tag_base;
struct nvkm_memory *tag_ram;
int zbc_min;
int zbc_max;
u32 zbc_color[NVKM_LTC_MAX_ZBC_CNT][4];
u32 zbc_depth[NVKM_LTC_MAX_ZBC_CNT];
u32 zbc_stencil[NVKM_LTC_MAX_ZBC_CNT];
int zbc_color_min;
int zbc_color_max;
u32 zbc_color[NVKM_LTC_MAX_ZBC_COLOR_CNT][4];
int zbc_depth_min;
int zbc_depth_max;
u32 zbc_depth[NVKM_LTC_MAX_ZBC_DEPTH_CNT];
u32 zbc_stencil[NVKM_LTC_MAX_ZBC_DEPTH_CNT];
};
void nvkm_ltc_tags_clear(struct nvkm_device *, u32 first, u32 count);

12
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View File

@ -67,7 +67,7 @@ gf100_gr_zbc_color_get(struct gf100_gr *gr, int format,
struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
for (i = ltc->zbc_color_min; i <= ltc->zbc_color_max; i++) {
if (gr->zbc_color[i].format) {
if (gr->zbc_color[i].format != format)
continue;
@ -114,7 +114,7 @@ gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
for (i = ltc->zbc_depth_min; i <= ltc->zbc_depth_max; i++) {
if (gr->zbc_depth[i].format) {
if (gr->zbc_depth[i].format != format)
continue;
@ -955,7 +955,7 @@ gf100_gr_zbc_init(struct gf100_gr *gr)
const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
int index, c = ltc->zbc_min, d = ltc->zbc_min, s = ltc->zbc_min;
int index, c = ltc->zbc_color_min, d = ltc->zbc_depth_min, s = ltc->zbc_depth_min;
if (!gr->zbc_color[0].format) {
gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); c++;
@ -971,13 +971,13 @@ gf100_gr_zbc_init(struct gf100_gr *gr)
}
}
for (index = c; index <= ltc->zbc_max; index++)
for (index = c; index <= ltc->zbc_color_max; index++)
gr->func->zbc->clear_color(gr, index);
for (index = d; index <= ltc->zbc_max; index++)
for (index = d; index <= ltc->zbc_depth_max; index++)
gr->func->zbc->clear_depth(gr, index);
if (gr->func->zbc->clear_stencil) {
for (index = s; index <= ltc->zbc_max; index++)
for (index = s; index <= ltc->zbc_depth_max; index++)
gr->func->zbc->clear_stencil(gr, index);
}
}

6
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View File

@ -105,9 +105,9 @@ struct gf100_gr {
struct gf100_gr_pack *bundle;
struct gf100_gr_pack *method;
struct gf100_gr_zbc_color zbc_color[NVKM_LTC_MAX_ZBC_CNT];
struct gf100_gr_zbc_depth zbc_depth[NVKM_LTC_MAX_ZBC_CNT];
struct gf100_gr_zbc_stencil zbc_stencil[NVKM_LTC_MAX_ZBC_CNT];
struct gf100_gr_zbc_color zbc_color[NVKM_LTC_MAX_ZBC_COLOR_CNT];
struct gf100_gr_zbc_depth zbc_depth[NVKM_LTC_MAX_ZBC_DEPTH_CNT];
struct gf100_gr_zbc_stencil zbc_stencil[NVKM_LTC_MAX_ZBC_DEPTH_CNT];
u8 rop_nr;
u8 gpc_nr;

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c
View File

@ -47,7 +47,7 @@ gp102_gr_zbc_stencil_get(struct gf100_gr *gr, int format,
struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
for (i = ltc->zbc_depth_min; i <= ltc->zbc_depth_max; i++) {
if (gr->zbc_stencil[i].format) {
if (gr->zbc_stencil[i].format != format)
continue;

10
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c
View File

@ -97,8 +97,10 @@ nvkm_ltc_init(struct nvkm_subdev *subdev)
struct nvkm_ltc *ltc = nvkm_ltc(subdev);
int i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
for (i = ltc->zbc_color_min; i <= ltc->zbc_color_max; i++)
ltc->func->zbc_clear_color(ltc, i, ltc->zbc_color[i]);
for (i = ltc->zbc_depth_min; i <= ltc->zbc_depth_max; i++) {
ltc->func->zbc_clear_depth(ltc, i, ltc->zbc_depth[i]);
if (ltc->func->zbc_clear_stencil)
ltc->func->zbc_clear_stencil(ltc, i, ltc->zbc_stencil[i]);
@ -137,7 +139,9 @@ nvkm_ltc_new_(const struct nvkm_ltc_func *func, struct nvkm_device *device,
nvkm_subdev_ctor(&nvkm_ltc, device, type, inst, &ltc->subdev);
ltc->func = func;
mutex_init(&ltc->mutex);
ltc->zbc_min = 1; /* reserve 0 for disabled */
ltc->zbc_max = min(func->zbc, NVKM_LTC_MAX_ZBC_CNT) - 1;
ltc->zbc_color_min = 1; /* reserve 0 for disabled */
ltc->zbc_color_max = min(func->zbc_color, NVKM_LTC_MAX_ZBC_COLOR_CNT) - 1;
ltc->zbc_depth_min = 1; /* reserve 0 for disabled */
ltc->zbc_depth_max = min(func->zbc_depth, NVKM_LTC_MAX_ZBC_DEPTH_CNT) - 1;
return 0;
}

3
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c
View File

@ -241,7 +241,8 @@ gf100_ltc = {
.intr = gf100_ltc_intr,
.cbc_clear = gf100_ltc_cbc_clear,
.cbc_wait = gf100_ltc_cbc_wait,
.zbc = 16,
.zbc_color = 16,
.zbc_depth = 16,
.zbc_clear_color = gf100_ltc_zbc_clear_color,
.zbc_clear_depth = gf100_ltc_zbc_clear_depth,
.invalidate = gf100_ltc_invalidate,

3
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c
View File

@ -42,7 +42,8 @@ gk104_ltc = {
.intr = gf100_ltc_intr,
.cbc_clear = gf100_ltc_cbc_clear,
.cbc_wait = gf100_ltc_cbc_wait,
.zbc = 16,
.zbc_color = 16,
.zbc_depth = 16,
.zbc_clear_color = gf100_ltc_zbc_clear_color,
.zbc_clear_depth = gf100_ltc_zbc_clear_depth,
.invalidate = gf100_ltc_invalidate,

3
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c
View File

@ -137,7 +137,8 @@ gm107_ltc = {
.intr = gm107_ltc_intr,
.cbc_clear = gm107_ltc_cbc_clear,
.cbc_wait = gm107_ltc_cbc_wait,
.zbc = 16,
.zbc_color = 16,
.zbc_depth = 16,
.zbc_clear_color = gm107_ltc_zbc_clear_color,
.zbc_clear_depth = gm107_ltc_zbc_clear_depth,
.invalidate = gf100_ltc_invalidate,

3
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c
View File

@ -49,7 +49,8 @@ gm200_ltc = {
.intr = gm107_ltc_intr,
.cbc_clear = gm107_ltc_cbc_clear,
.cbc_wait = gm107_ltc_cbc_wait,
.zbc = 16,
.zbc_color = 16,
.zbc_depth = 16,
.zbc_clear_color = gm107_ltc_zbc_clear_color,
.zbc_clear_depth = gm107_ltc_zbc_clear_depth,
.invalidate = gf100_ltc_invalidate,

3
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c
View File

@ -61,7 +61,8 @@ gp100_ltc = {
.intr = gp100_ltc_intr,
.cbc_clear = gm107_ltc_cbc_clear,
.cbc_wait = gm107_ltc_cbc_wait,
.zbc = 16,
.zbc_color = 16,
.zbc_depth = 16,
.zbc_clear_color = gm107_ltc_zbc_clear_color,
.zbc_clear_depth = gm107_ltc_zbc_clear_depth,
.invalidate = gf100_ltc_invalidate,

3
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.c
View File

@ -36,7 +36,8 @@ gp102_ltc = {
.intr = gp100_ltc_intr,
.cbc_clear = gm107_ltc_cbc_clear,
.cbc_wait = gm107_ltc_cbc_wait,
.zbc = 16,
.zbc_color = 16,
.zbc_depth = 16,
.zbc_clear_color = gm107_ltc_zbc_clear_color,
.zbc_clear_depth = gm107_ltc_zbc_clear_depth,
.zbc_clear_stencil = gp102_ltc_zbc_clear_stencil,

3
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
View File

@ -50,7 +50,8 @@ gp10b_ltc = {
.intr = gp100_ltc_intr,
.cbc_clear = gm107_ltc_cbc_clear,
.cbc_wait = gm107_ltc_cbc_wait,
.zbc = 16,
.zbc_color = 16,
.zbc_depth = 16,
.zbc_clear_color = gm107_ltc_zbc_clear_color,
.zbc_clear_depth = gm107_ltc_zbc_clear_depth,
.zbc_clear_stencil = gp102_ltc_zbc_clear_stencil,

3
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h
View File

@ -16,7 +16,8 @@ struct nvkm_ltc_func {
void (*cbc_clear)(struct nvkm_ltc *, u32 start, u32 limit);
void (*cbc_wait)(struct nvkm_ltc *);
int zbc;
int zbc_color;
int zbc_depth;
void (*zbc_clear_color)(struct nvkm_ltc *, int, const u32[4]);
void (*zbc_clear_depth)(struct nvkm_ltc *, int, const u32);
void (*zbc_clear_stencil)(struct nvkm_ltc *, int, const u32);