github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-09-28 20:12:01 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

MHI Host

Browse Source 
========
 
 - Free the "img_info::mhi_buf" in the error path of mhi_alloc_bhie_table() to
   avoid memory leak.
 
 - Add support for Qualcomm X100 5G RAN Accelerator card with relevant channel
   and event config.
 
 - Enable MSI-X if the endpoint supports.
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEEZ6VDKoFIy9ikWCeXVZ8R5v6RzvUFAmeDQNIACgkQVZ8R5v6R
 zvWhbwf/fGgfkXamkShATibCIPn0aL8kCA67OUmdxo6wVSdv3/EX/1xF7Be2fwGG
 1uyMFQdt/CpD8bo3I4YfNgUFG3F2VkwnPoYUXMlSpyyres6vCawW99gM3PqU6XZF
 zk3vDcofWHgevHAe5GEU0ntIOwg/orTZJsTVN75EME2qVjpVrEiRE/hqjXfWd1s+
 1H1e+9KIn3r2Vg6q2JH0+/i4OUwtUNteUPdERWRl4T0pKiiu7e0ZxAnybiD3oP5z
 zTQY5zzQFUpgS0Nzka18+h42emSW12CyC7kTz39XHoFQgUEL1hD0e91/sWy7n66W
 paVDtFEBwt5xFMexaJfkI+T83MelPg==
 =D+sS
 -----END PGP SIGNATURE-----

Merge tag 'mhi-for-v6.14' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mani/mhi into char-misc-next

Pull MHI update from Manivannan:

MHI Host
========

- Free the "img_info::mhi_buf" in the error path of mhi_alloc_bhie_table() to
  avoid memory leak.

- Add support for Qualcomm X100 5G RAN Accelerator card with relevant channel
  and event config.

- Enable MSI-X if the endpoint supports.

* tag 'mhi-for-v6.14' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mani/mhi:
  bus: mhi: host: pci_generic: Enable MSI-X if the endpoint supports
  bus: mhi: host: pci_generic: Add support for QDU100 device
  bus: mhi: host: Free mhi_buf vector inside mhi_alloc_bhie_table()
This commit is contained in:
Greg Kroah-Hartman 2025-01-12 13:57:24 +01:00
commit 44cefdf1cc
2 changed files with 57 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/bus/mhi/host/boot.c
View File

@ -357,6 +357,7 @@ int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl,
for (--i, --mhi_buf; i >= 0; i--, mhi_buf--)
dma_free_coherent(mhi_cntrl->cntrl_dev, mhi_buf->len,
mhi_buf->buf, mhi_buf->dma_addr);
kfree(img_info->mhi_buf);
error_alloc_mhi_buf:
kfree(img_info);

57
drivers/bus/mhi/host/pci_generic.c
View File

@ -245,6 +245,58 @@ struct mhi_pci_dev_info {
.channel = ch_num, \
}
static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = {
MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2),
MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2),
MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1),
MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1),
MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3),
MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3),
MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3),
MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4),
MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4),
MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4),
MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4),
MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4),
MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4),
MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5),
MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5),
};
static struct mhi_event_config mhi_qcom_qdu100_events[] = {
/* first ring is control+data ring */
MHI_EVENT_CONFIG_CTRL(0, 64),
/* SAHARA dedicated event ring */
MHI_EVENT_CONFIG_SW_DATA(1, 256),
/* Software channels dedicated event ring */
MHI_EVENT_CONFIG_SW_DATA(2, 64),
MHI_EVENT_CONFIG_SW_DATA(3, 256),
MHI_EVENT_CONFIG_SW_DATA(4, 256),
/* Software IP channels dedicated event ring */
MHI_EVENT_CONFIG_SW_DATA(5, 512),
MHI_EVENT_CONFIG_SW_DATA(6, 512),
MHI_EVENT_CONFIG_SW_DATA(7, 512),
};
static const struct mhi_controller_config mhi_qcom_qdu100_config = {
.max_channels = 128,
.timeout_ms = 120000,
.num_channels = ARRAY_SIZE(mhi_qcom_qdu100_channels),
.ch_cfg = mhi_qcom_qdu100_channels,
.num_events = ARRAY_SIZE(mhi_qcom_qdu100_events),
.event_cfg = mhi_qcom_qdu100_events,
};
static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = {
.name = "qcom-qdu100",
.fw = "qcom/qdu100/xbl_s.melf",
.edl_trigger = true,
.config = &mhi_qcom_qdu100_config,
.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
.dma_data_width = 32,
.sideband_wake = false,
};
static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = {
MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1),
MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1),
@ -742,6 +794,9 @@ static const struct pci_device_id mhi_pci_id_table[] = {
.driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info },
{ PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309),
.driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info },
/* QDU100, x100-DU */
{ PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601),
.driver_data = (kernel_ulong_t) &mhi_qcom_qdu100_info },
{ PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */
.driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
{ PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */
@ -949,7 +1004,7 @@ static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl,
*/
mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events;
nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSI);
nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSIX | PCI_IRQ_MSI);
if (nr_vectors < 0) {
dev_err(&pdev->dev, "Error allocating MSI vectors %d\n",
nr_vectors);