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arm64: dts: S32G3: Introduce device tree for S32G-VNP-RDB3
This commit adds device tree support for the NXP S32G3-based
S32G-VNP-RDB3 Board [1].
The S32G3 features an 8-core ARM Cortex-A53 based SoC developed by NXP.
The device tree files are derived from the official NXP downstream
Linux tree [2].
This addition encompasses a limited selection of peripherals that
are upstream-supported. Apart from the ARM System Modules
(GIC, Generic Timer, etc.), the following IPs have been validated:
* UART: fsl-linflexuart
* SDHC: fsl-imx-esdhc
Clock settings for the chip rely on ATF Firmware [3].
Pin control integration into the device tree is pending and currently
relies on Firmware/U-Boot settings [4].
These changes were validated using BSP39 Firmware/U-Boot from NXP [5].
The modifications enable booting the official Ubuntu 22.04 from NXP on
the RDB3 with default settings from the SD card and eMMC.
[1] https://www.nxp.com/design/design-center/designs/s32g3-vehicle-networking-reference-design:S32G-VNP-RDB3
[2] https://github.com/nxp-auto-linux/linux
[3] https://github.com/nxp-auto-linux/arm-trusted-firmware
[4] https://github.com/nxp-auto-linux/u-boot
[5] https://github.com/nxp-auto-linux/auto_yocto_bsp
Signed-off-by: Wadim Mueller <wafgo01@gmail.com>
Tested-by: Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
Reviewed-by: Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Wadim Mueller
Shawn Guo
parent
b98807c7be
commit
44b305a2de
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@ -259,4 +259,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb
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dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
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dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb
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dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb
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dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
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233
arch/arm64/boot/dts/freescale/s32g3.dtsi
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233
arch/arm64/boot/dts/freescale/s32g3.dtsi
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@ -0,0 +1,233 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright 2021-2023 NXP
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*
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* Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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* Ciprian Costea <ciprianmarian.costea@nxp.com>
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* Andra-Teodora Ilie <andra.ilie@nxp.com>
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "nxp,s32g3";
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interrupt-parent = <&gic>;
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x102>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x103>;
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enable-method = "psci";
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clocks = <&dfs 0>;
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};
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};
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firmware {
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scmi: scmi {
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compatible = "arm,scmi-smc";
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shmem = <&scmi_shmem>;
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arm,smc-id = <0xc20000fe>;
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#address-cells = <1>;
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#size-cells = <0>;
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dfs: protocol@13 {
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reg = <0x13>;
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#clock-cells = <1>;
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};
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clks: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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scmi_shmem: shm@d0000000 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0xd0000000 0x0 0x80>;
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no-map;
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};
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0x80000000>;
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uart0: serial@401c8000 {
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compatible = "nxp,s32g3-linflexuart",
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"fsl,s32v234-linflexuart";
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reg = <0x401c8000 0x3000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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uart1: serial@401cc000 {
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compatible = "nxp,s32g3-linflexuart",
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"fsl,s32v234-linflexuart";
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reg = <0x401cc000 0x3000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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uart2: serial@402bc000 {
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compatible = "nxp,s32g3-linflexuart",
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"fsl,s32v234-linflexuart";
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reg = <0x402bc000 0x3000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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usdhc0: mmc@402f0000 {
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compatible = "nxp,s32g3-usdhc",
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"nxp,s32g2-usdhc";
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reg = <0x402f0000 0x1000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 32>,
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<&clks 31>,
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<&clks 33>;
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clock-names = "ipg", "ahb", "per";
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status = "disabled";
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};
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gic: interrupt-controller@50800000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x50800000 0x10000>,
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<0x50900000 0x200000>,
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<0x50400000 0x2000>,
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<0x50410000 0x2000>,
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<0x50420000 0x2000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* phys */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* virt */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */
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<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */
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arm,no-tick-in-suspend;
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};
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};
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45
arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
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45
arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
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@ -0,0 +1,45 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright 2021-2023 NXP
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*
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* NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)
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*/
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/dts-v1/;
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#include "s32g3.dtsi"
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/ {
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model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";
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compatible = "nxp,s32g399a-rdb3", "nxp,s32g3";
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aliases {
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mmc0 = &usdhc0;
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serial0 = &uart0;
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serial1 = &uart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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/* 4GiB RAM */
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0 0x80000000>,
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<0x8 0x80000000 0 0x80000000>;
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&usdhc0 {
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bus-width = <8>;
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status = "okay";
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};
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