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mailbox: rockchip: code optimization
This change amends the below features. - Checked the mailbox channel status before send message. - Used the con_priv variable to handle the channel private data. - Added the spinlock cfg_lock to protect the register R/W. - Added shared channel irq support. - Optimized the interrupt handler can receive B2A message proactively. Change-Id: If1939e51e821307788ab59dd4ef874a20a6568e2 Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This commit is contained in:
Frank Wang
Tao Huang
parent
641b5aad8b
commit
448b1e499d
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@ -11,6 +11,7 @@
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#define MAILBOX_A2B_INTEN 0x00
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#define MAILBOX_A2B_STATUS 0x04
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@ -24,7 +25,7 @@
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struct rockchip_mbox_msg {
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u32 cmd;
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int rx_size;
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u32 data;
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};
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struct rockchip_mbox_data {
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@ -34,17 +35,13 @@ struct rockchip_mbox_data {
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struct rockchip_mbox_chan {
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int idx;
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int irq;
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struct rockchip_mbox_msg *msg;
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struct rockchip_mbox *mb;
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};
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struct rockchip_mbox {
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struct mbox_controller mbox;
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struct clk *pclk;
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void __iomem *mbox_base;
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/* The maximum size of buf for each channel */
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u32 buf_size;
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spinlock_t cfg_lock; /* Serialise access to the register */
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struct rockchip_mbox_chan *chans;
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};
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@ -53,24 +50,23 @@ static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data)
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{
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struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
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struct rockchip_mbox_msg *msg = data;
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struct rockchip_mbox_chan *chans = mb->chans;
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struct rockchip_mbox_chan *chans = chan->con_priv;
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u32 status;
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if (!msg)
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return -EINVAL;
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if (msg->rx_size > mb->buf_size) {
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dev_err(mb->mbox.dev, "Transmit size over buf size(%d)\n",
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mb->buf_size);
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return -EINVAL;
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status = readl_relaxed(mb->mbox_base + MAILBOX_A2B_STATUS);
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if (status & (1U << chans->idx)) {
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dev_err(mb->mbox.dev, "The mailbox channel is busy\n");
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return -EBUSY;
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}
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dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x\n",
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chans->idx, msg->cmd);
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mb->chans[chans->idx].msg = msg;
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dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x, data 0x%08x\n",
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chans->idx, msg->cmd, msg->data);
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writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(chans->idx));
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writel_relaxed(msg->rx_size, mb->mbox_base +
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writel_relaxed(msg->data, mb->mbox_base +
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MAILBOX_A2B_DAT(chans->idx));
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return 0;
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@ -79,10 +75,15 @@ static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data)
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static int rockchip_mbox_startup(struct mbox_chan *chan)
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{
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struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
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struct rockchip_mbox_chan *chans = chan->con_priv;
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u32 val = 0U;
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/* Enable all B2A interrupts */
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writel_relaxed((1 << mb->mbox.num_chans) - 1,
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mb->mbox_base + MAILBOX_B2A_INTEN);
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/* Enable the corresponding B2A interrupt */
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spin_lock(&mb->cfg_lock);
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val = readl_relaxed(mb->mbox_base + MAILBOX_B2A_INTEN) |
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(1U << chans->idx);
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writel_relaxed(val, mb->mbox_base + MAILBOX_B2A_INTEN);
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spin_unlock(&mb->cfg_lock);
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return 0;
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}
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@ -90,12 +91,15 @@ static int rockchip_mbox_startup(struct mbox_chan *chan)
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static void rockchip_mbox_shutdown(struct mbox_chan *chan)
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{
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struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
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struct rockchip_mbox_chan *chans = mb->chans;
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struct rockchip_mbox_chan *chans = chan->con_priv;
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u32 val = 0U;
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/* Disable all B2A interrupts */
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writel_relaxed(0, mb->mbox_base + MAILBOX_B2A_INTEN);
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mb->chans[chans->idx].msg = NULL;
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/* Disable the corresponding B2A interrupt */
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spin_lock(&mb->cfg_lock);
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val = readl_relaxed(mb->mbox_base + MAILBOX_B2A_INTEN) &
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~(1U << chans->idx);
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writel_relaxed(val, mb->mbox_base + MAILBOX_B2A_INTEN);
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spin_unlock(&mb->cfg_lock);
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}
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static const struct mbox_chan_ops rockchip_mbox_chan_ops = {
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@ -107,47 +111,30 @@ static const struct mbox_chan_ops rockchip_mbox_chan_ops = {
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static irqreturn_t rockchip_mbox_irq(int irq, void *dev_id)
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{
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int idx;
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struct rockchip_mbox_msg msg;
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struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;
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u32 status = readl_relaxed(mb->mbox_base + MAILBOX_B2A_STATUS);
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for (idx = 0; idx < mb->mbox.num_chans; idx++) {
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if ((status & (1 << idx)) && (irq == mb->chans[idx].irq)) {
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if ((status & (1U << idx)) && irq == mb->chans[idx].irq) {
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/* Get cmd/data from the channel of B2A */
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msg.cmd = readl_relaxed(mb->mbox_base +
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MAILBOX_B2A_CMD(idx));
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msg.data = readl_relaxed(mb->mbox_base +
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MAILBOX_B2A_DAT(idx));
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dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x, data 0x%08x\n",
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idx, msg.cmd, msg.data);
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if (mb->mbox.chans[idx].cl)
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mbox_chan_received_data(&mb->mbox.chans[idx],
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&msg);
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/* Clear mbox interrupt */
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writel_relaxed(1 << idx,
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writel_relaxed(1U << idx,
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mb->mbox_base + MAILBOX_B2A_STATUS);
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return IRQ_WAKE_THREAD;
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}
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}
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return IRQ_NONE;
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}
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static irqreturn_t rockchip_mbox_isr(int irq, void *dev_id)
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{
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int idx;
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struct rockchip_mbox_msg *msg = NULL;
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struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;
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for (idx = 0; idx < mb->mbox.num_chans; idx++) {
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if (irq != mb->chans[idx].irq)
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continue;
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msg = mb->chans[idx].msg;
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if (!msg) {
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dev_err(mb->mbox.dev,
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"Chan[%d]: B2A message is NULL\n", idx);
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break; /* spurious */
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}
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mbox_chan_received_data(&mb->mbox.chans[idx], msg);
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mb->chans[idx].msg = NULL;
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dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x\n",
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idx, msg->cmd);
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break;
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}
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return IRQ_HANDLED;
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}
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@ -195,6 +182,7 @@ static int rockchip_mbox_probe(struct platform_device *pdev)
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mb->mbox.num_chans = drv_data->num_chans;
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mb->mbox.ops = &rockchip_mbox_chan_ops;
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mb->mbox.txdone_irq = true;
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spin_lock_init(&mb->cfg_lock);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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@ -204,9 +192,6 @@ static int rockchip_mbox_probe(struct platform_device *pdev)
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if (IS_ERR(mb->mbox_base))
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return PTR_ERR(mb->mbox_base);
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/* Each channel has two buffers for A2B and B2A */
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mb->buf_size = (size_t)resource_size(res) / (drv_data->num_chans * 2);
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mb->pclk = devm_clk_get(&pdev->dev, "pclk_mailbox");
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if (IS_ERR(mb->pclk)) {
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ret = PTR_ERR(mb->pclk);
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@ -223,20 +208,26 @@ static int rockchip_mbox_probe(struct platform_device *pdev)
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for (i = 0; i < mb->mbox.num_chans; i++) {
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irq = platform_get_irq(pdev, i);
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if (irq < 0)
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return irq;
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ret = devm_request_threaded_irq(&pdev->dev, irq,
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rockchip_mbox_irq,
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rockchip_mbox_isr, IRQF_ONESHOT,
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dev_name(&pdev->dev), mb);
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if (ret < 0)
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return ret;
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if (irq < 0) {
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/* For shared irq case, only could be got one time */
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if (i > 0 && irq == -ENXIO)
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mb->chans[i].irq = mb->chans[0].irq;
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else
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return irq;
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} else {
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mb->chans[i].irq = irq;
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ret = devm_request_threaded_irq(&pdev->dev, irq,
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NULL,
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rockchip_mbox_irq,
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IRQF_ONESHOT,
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dev_name(&pdev->dev),
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mb);
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if (ret < 0)
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return ret;
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}
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mb->chans[i].idx = i;
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mb->chans[i].irq = irq;
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mb->chans[i].mb = mb;
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mb->chans[i].msg = NULL;
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mb->mbox.chans[i].con_priv = &mb->chans[i];
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}
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ret = devm_mbox_controller_register(&pdev->dev, &mb->mbox);
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