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arm64: dts: fvp: Add CPU idle states for Rev C model

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Add CPU idle state definitions to the FVP Rev C device tree to enable
support for CPU lower power modes. This allows the system to properly
enter low power states during idle. It is disabled by default as it is
know to impact performance on the models.

Note that the power_state parameter(arm,psci-suspend-param) doesn't use
the Extended StateID format for compatibility reasons on FVP.

Tested on the FVP Rev C model with PSCI support enabled firmware.

Tested-by: Leo Yan <leo.yan@arm.com>
Message-Id: <20250509154640.836093-2-sudeep.holla@arm.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This commit is contained in:
Sudeep Holla 2025-05-09 16:46:39 +01:00
parent 7556a55b07
commit 44845ea83d
1 changed files with 32 additions and 0 deletions
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32
arch/arm64/boot/dts/arm/fvp-base-revc.dts
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@ -44,6 +44,30 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <40>;
exit-latency-us = <100>;
min-residency-us = <150>;
status = "disabled";
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x1010000>;
entry-latency-us = <500>;
exit-latency-us = <1000>;
min-residency-us = <2500>;
status = "disabled";
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
@ -56,6 +80,7 @@ cpu0: cpu@0 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C0_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu1: cpu@100 {
device_type = "cpu";
@ -69,6 +94,7 @@ cpu1: cpu@100 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C0_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu2: cpu@200 {
device_type = "cpu";
@ -82,6 +108,7 @@ cpu2: cpu@200 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C0_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu3: cpu@300 {
device_type = "cpu";
@ -95,6 +122,7 @@ cpu3: cpu@300 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C0_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu4: cpu@10000 {
device_type = "cpu";
@ -108,6 +136,7 @@ cpu4: cpu@10000 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C1_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu5: cpu@10100 {
device_type = "cpu";
@ -121,6 +150,7 @@ cpu5: cpu@10100 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C1_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu6: cpu@10200 {
device_type = "cpu";
@ -134,6 +164,7 @@ cpu6: cpu@10200 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C1_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu7: cpu@10300 {
device_type = "cpu";
@ -147,6 +178,7 @@ cpu7: cpu@10300 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C1_L2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
C0_L2: l2-cache0 {
compatible = "cache";