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Merge "drivers: llcc_perfmon: Add llcc_perfmon support"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
442f291a5c
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@ -93,6 +93,16 @@ config QCOM_KRYO_L2_ACCESSORS
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bool
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depends on ARCH_QCOM && ARM64 || COMPILE_TEST
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config QCOM_LLCC_PERFMON
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tristate "Qualcomm Technologies, Inc. LLCC Perfmon driver"
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depends on QCOM_LLCC
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help
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This option enables driver for LLCC Performance monitor block. Using
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this various events in different LLCC sub ports can be monitored.
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This is used for performance and debug activity and exports sysfs
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interface. sysfs interface is used to configure and dump the LLCC
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performance events.
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config QCOM_MDT_LOADER
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tristate
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select QCOM_SCM
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|
|
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@ -36,6 +36,7 @@ obj-$(CONFIG_QCOM_MSM_IPCC) += qcom_ipcc.o
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obj-$(CONFIG_QCOM_APR) += apr.o
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obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
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obj-$(CONFIG_QCOM_MEMORY_DUMP_V2) += memory_dump_v2.o
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obj-$(CONFIG_QCOM_LLCC_PERFMON) += llcc_perfmon.o
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obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
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obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
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obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o
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|
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301
drivers/soc/qcom/llcc_events.h
Normal file
301
drivers/soc/qcom/llcc_events.h
Normal file
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@ -0,0 +1,301 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _SOC_QCOM_LLCC_EVENTS_H_
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#define _SOC_QCOM_LLCC_EVENTS_H_
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enum event_port_select {
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EVENT_PORT_FEAC,
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EVENT_PORT_FERC,
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EVENT_PORT_FEWC,
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EVENT_PORT_BEAC,
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EVENT_PORT_BERC,
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EVENT_PORT_TRP,
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EVENT_PORT_DRP,
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EVENT_PORT_PMGR,
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EVENT_PORT_BEAC1,
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EVENT_PORT_TENURE,
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EVENT_PORT_TLAT,
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};
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enum feac_events {
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FEAC_ANY_ACCESS,
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FEAC_READ_INCR,
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FEAC_WRITE_INCR,
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FEAC_WRITE_ORDERED,
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FEAC_READE_EXCL,
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FEAC_WRITE_EXCL,
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FEAC_CMO,
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FEAC_CMO_CLEAN,
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FEAC_CMO_INVAL,
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FEAC_CMO_CLEANINVAL,
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FEAC_CMO_DCPLD,
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FEAC_READ_NOALLOC,
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FEAC_WRITE_NOALLOC,
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FEAC_PREFETCH,
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FEAC_RD_BYTES,
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FEAC_RD_BEATS,
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FEAC_WR_BYTES,
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FEAC_WR_BEATS,
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FEAC_FC_READ,
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FEAC_EWD_ACCESS,
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FEAC_TCM_ACCESS,
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FEAC_GM_HIT,
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FEAC_GM_MISS,
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FEAC_GM_UNAVAILABLE,
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FEAC_XPU_ERROR,
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FEAC_READ_HAZARD,
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FEAC_WRITE_HAZARD,
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FEAC_GRANULE_READ,
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FEAC_GRANULE_WRITE,
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FEAC_RIFB_ALLOC,
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FEAC_WIFB_ALLOC,
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FEAC_RIFB_DEALLOC,
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FEAC_WIFB_DEALLOC,
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FEAC_RESERVED,
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FEAC_RESERVED1,
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FEAC_FEAC2TRP_LP_TX,
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FEAC_TRP_LP_BUSY,
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FEAC_FEAC2TRP_HP_TX,
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FEAC_TRP_HP_BUSY,
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FEAC_FEAC2FEWC_TX,
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FEAC_BEAC_LP_BUSY,
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FEAC_BEAC_HP_BUSY,
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FEAC_RIFB_FULL,
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FEAC_WIFB_FULL,
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FEAC_RD_CRDT_TX,
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FEAC_WR_CRDT_TX,
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FEAC_PROMOTION,
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FEAC_FEAC2TRP_LP_PRESSURE,
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FEAC_FEAC2TRP_HP_PRESSURE,
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FEAC_FEAC2FEWC_PRESSURE,
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FEAC_FEAC2BEAC_LP_PRESSURE,
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FEAC_FEAC2BEAC_HP_PRESSURE,
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FEAC_WR_THROUGH,
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};
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enum ferc_events {
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FERC_BERC_CMD,
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FERC_BERC_BEAT,
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FERC_DRP_CMD,
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FERC_DRP_BEAT,
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FERC_RD_CTRL_RSP_TX,
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FERC_WR_CTRL_RSP_TX,
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FERC_RD_DATA_TX,
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FERC_MISS_TRUMPS_HIT,
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FERC_HIT_TRUMPS_WRSP,
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FERC_RD_INTRA_RSP_IDLE,
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};
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enum fewc_events {
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FEWC_WR_CMD,
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FEWC_WR_DATA_BEAT,
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FEWC_WR_LAST,
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FEWC_WBUF_DEALLOC,
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FEWC_WR_HIT,
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FEWC_WR_MISS,
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FEWC_NC_RMW,
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FEWC_WR_DOWNGRADE,
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FEWC_BEAC_WR_CMD,
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FEWC_BEAC_WR_BEAT,
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FEWC_BEAC_RD_CMD,
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FEWC_BERC_FILL_BEAT,
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FEWC_DRP_WR_CMD,
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FEWC_DRP_WR_BEAT,
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FEWC_DRP_RD_BEAT,
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FEWC_TRP_TAG_LOOKUP,
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FEWC_TRP_TAG_UPDATE,
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FEWC_TRP_UNSTALL,
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FEWC_WBUFFS_FULL,
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FEWC_DRP_BUSY,
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FEWC_BEAC_WR_BUSY,
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FEWC_BEAC_RD_BUSY,
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FEWC_TRP_TAG_LOOKUP_BUSY,
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FEWC_TRP_TAG_UPDATE_BUSY,
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FEWC_C_RMW,
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FEWC_NC_ALLOC_RMW,
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FEWC_NC_NO_ALLOC_RMW,
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FEWC_NC_RMW_DEALLOC,
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FEWC_C_RMW_DEALLOC,
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FEWC_STALLED_BY_EVICT,
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};
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enum beac_events {
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BEAC_RD_TX,
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BEAC_WR_TX,
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BEAC_RD_GRANULE,
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BEAC_WR_GRANULE,
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BEAC_WR_BEAT_TX,
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BEAC_RD_CRDT_ZERO,
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BEAC_WR_CRDT_ZERO,
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BEAC_WDATA_CRDT_ZERO,
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BEAC_IFCMD_CRDT_ZERO,
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BEAC_IFWDATA_CRDT_ZERO,
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BEAC_PCT_ENTRY_ALLOC,
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BEAC_PCT_ENTRY_FREE,
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BEAC_PCT_FULL,
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BEAC_RD_PROMOTION_TX,
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BEAC_WR_PROMOTION_TX,
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BEAC_RD_PRESSURE_TX,
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BEAC_WR_PRESSURE_TX,
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};
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enum berc_events {
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BERC_RD_CMD,
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BERC_ERROR_CMD,
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BERC_PCT_ENTRY_DEALLOC,
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BERC_RD_RSP_RX,
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BERC_RD_RSP_BEAT_RX,
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BERC_RD_LA_RX,
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BERC_UNSTALL_RX,
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BERC_TX_RD_CMD,
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BERC_TX_ERR_CMD,
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BERC_TX_RD_BEAT,
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BERC_TX_ERR_BEAT,
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BERC_RESERVED,
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BERC_RESERVED1,
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BERC_CMO_RX,
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BERC_CMO_TX,
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BERC_DRP_WR_TX,
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BERC_DRP_WR_BEAT_TX,
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BERC_FEWC_WR_TX,
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BERC_FEWC_WR_BEAT_TX,
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BERC_LBUFFS_FULL,
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BERC_DRP_BUSY,
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BERC_FEWC_BUSY,
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BERC_LBUFF_STALLED,
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};
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enum trp_events {
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TRP_ANY_ACCESS,
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TRP_INCR_RD,
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TRP_INCR_WR,
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TRP_ANY_HIT,
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TRP_RD_HIT,
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TRP_WR_HIT,
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TRP_RD_MISS,
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TRP_WR_MISS,
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TRP_RD_HIT_MISS,
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TRP_WR_HIT_MISS,
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TRP_EVICT,
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TRP_GRANULE_EVICT,
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TRP_RD_EVICT,
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TRP_WR_EVICT,
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TRP_LINE_FILL,
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TRP_GRANULE_FILL,
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TRP_WSC_WRITE,
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TRP_WSC_EVICT,
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TRP_SUBCACHE_ACT,
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TRP_SUBCACHE_DEACT,
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TRP_RD_DEACTIVE_SUBCACHE,
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TRP_WR_DEACTIVE_SUBCACHE,
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TRP_INVALID_LINE_ALLOC,
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TRP_DEACTIVE_LINE_ALLOC,
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TRP_SELF_EVICTION_ALLOC,
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TRP_UC_SUBCACHE_ALLOC,
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TRP_FC_SELF_EVICTION_ALLOC,
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TRP_LP_SUBCACHE_VICTIM,
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TRP_OC_SUBCACHE_VICTIM,
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TRP_MRU_ROLLOVER,
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TRP_NC_DOWNGRADE,
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TRP_TAGRAM_CORR_ERR,
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TRP_TAGRAM_UNCORR_ERR,
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TRP_RD_MISS_FC,
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TRP_CPU_WRITE_EWD_LINE,
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TRP_CLIENT_WRITE_EWD_LINE,
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TRP_CLIENT_READ_EWD_LINE,
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TRP_CMO_I_EWD_LINE,
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TRP_CMO_I_DIRTY_LINE,
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TRP_DRP_RD_NOTIFICATION,
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TRP_DRP_WR_NOTIFICATION,
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TRP_LINEFILL_TAG_UPDATE,
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TRP_FEWC_TAG_UPDATE,
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TRP_ET_FULL,
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TRP_NAWT_FULL,
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TRP_HITQ_FULL,
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TRP_ET_ALLOC,
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TRP_ET_DEALLOC,
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TRP_NAWT_ALLOC,
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TRP_NAWT_DEALLOC,
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TRP_RD_REPLAY,
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TRP_WR_ECC_RD,
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TRP_ET_LP_FULL,
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TRP_ET_HP_FULL,
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TRP_SOEH,
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};
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enum drp_events {
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DRP_TRP_RD_NOTIFICATION,
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DRP_TRP_WR_NOTIFICATION,
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DRP_BIST_WR_NOTIFICATION,
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DRP_DRIE_WR_NOTIFICATION,
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DRP_ECC_CORR_ERR,
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DRP_ECC_UNCORR_ERR,
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DRP_FERC_RD_TX,
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DRP_FEWC_RD_TX,
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DRP_EVICT_LINE_TX,
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DRP_EVICT_GRANULE_TX,
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DRP_BIST_TX,
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DRP_FERC_RD_BEAT,
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DRP_FEWC_RD_BEAT,
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DRP_BIST_RD_BEAT,
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DRP_EVICT_RD_BEAT,
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DRP_BERC_WR_BEAT,
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DRP_FEWC_WR_BEAT,
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DRP_BIST_WR_BEAT,
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DRP_DRIE_WR_BEAT,
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DRP_BERC_UNSTALL,
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DRP_FEWC_UNSTALL,
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DRP_LB_RD,
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DRP_LB_WR,
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DRP_BANK_CONFLICT,
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DRP_FILL_TRUMPS_RD,
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DRP_RD_TRUMPS_WR,
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DRP_LB_SLP_RET,
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DRP_LB_SLP_NRET,
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DRP_LB_WAKEUP,
|
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DRP_TRP_EARLY_WAKEUP,
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DRP_PCB_IDLE,
|
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DRP_EVICT_RDFIFO_FULL,
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DRP_FEWC_RDFIFO_FULL,
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DRP_FERC_RDFIFO_FULL,
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DRP_FERC_RD,
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DRP_FEWC_RD,
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DRP_LINE_EVICT,
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DRP_GRANULE_EVICT,
|
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DRP_BIST_RD,
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DRP_FEWC_WR,
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DRP_LINE_FILL,
|
||||
DRP_GRANULE_FILL,
|
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DRP_BIST_WR,
|
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DRP_DRIE_WR,
|
||||
};
|
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|
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enum pmgr_events {
|
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PMGR_Q_RUN_STATE,
|
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PMGR_Q_DENIED_STATE,
|
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PMGR_Q_STOPEED_TO_Q_RUN,
|
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PMGR_Q_RUN_TO_Q_FENCED,
|
||||
PMGR_Q_RUN_TO_Q_DENIED,
|
||||
PMGR_Q_DENIED_TO_Q_RUN,
|
||||
PMGR_Q_FENCED_TO_Q_STOPPED,
|
||||
PMGR_Q_FENCED_TO_Q_DENIED,
|
||||
};
|
||||
|
||||
enum filter_type {
|
||||
SCID,
|
||||
MID,
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||||
PROFILING_TAG,
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||||
WAY_ID,
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OPCODE,
|
||||
CACHEALLOC,
|
||||
MEMTAGOPS,
|
||||
MULTISCID,
|
||||
DIRTYINFO,
|
||||
UNKNOWN,
|
||||
};
|
||||
|
||||
#endif /* _SOC_QCOM_LLCC_EVENTS_H_ */
|
||||
1456
drivers/soc/qcom/llcc_perfmon.c
Normal file
1456
drivers/soc/qcom/llcc_perfmon.c
Normal file
File diff suppressed because it is too large
Load Diff
319
drivers/soc/qcom/llcc_perfmon.h
Normal file
319
drivers/soc/qcom/llcc_perfmon.h
Normal file
|
|
@ -0,0 +1,319 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_QCOM_LLCC_PERFMON_H_
|
||||
#define _SOC_QCOM_LLCC_PERFMON_H_
|
||||
|
||||
#define LLCC_VER4 (41)
|
||||
#define LLCC_VER2 (21)
|
||||
#define VER_CHK(v) (v >= LLCC_VER2) //check LLCC version 2
|
||||
#define VER_CHK4(v) (v == LLCC_VER4) //check LLCC version 4
|
||||
|
||||
/* COMMON */
|
||||
#define LLCC_COMMON_HW_INFO(v) (VER_CHK(v) ? 0x34000 : 0x30000)
|
||||
#define LLCC_COMMON_STATUS0(v) (VER_CHK(v) ? 0x3400C : 0x3000C)
|
||||
|
||||
/* FEAC */
|
||||
#define FEAC_PROF_FILTER_0_CFG3(v) (VER_CHK(v) ? 0x4300C : 0x03700C)
|
||||
#define FEAC_PROF_FILTER_0_CFG5(v) (VER_CHK(v) ? 0x43014 : 0x037014)
|
||||
#define FEAC_PROF_FILTER_0_CFG6(v) (VER_CHK(v) ? 0x43018 : 0x037018)
|
||||
#define FEAC_PROF_FILTER_0_CFG7(v) (VER_CHK(v) ? 0x4301C : 0x03701C)
|
||||
#define FEAC_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x43060 : 0x037060) \
|
||||
+ 4 * (n))
|
||||
#define FEAC_PROF_CFG(v) (VER_CHK(v) ? 0x430A0 : 0x0370A0)
|
||||
|
||||
/* FERC */
|
||||
#define FERC_PROF_FILTER_0_CFG0(v) (VER_CHK(v) ? 0x49000 : 0x03B000)
|
||||
#define FERC_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x49020 : 0x03B020) \
|
||||
+ 4 * (n))
|
||||
#define FERC_PROF_CFG(v) (VER_CHK(v) ? 0x49060 : 0x03B060)
|
||||
|
||||
/* FEWC */
|
||||
#define FEWC_PROF_FILTER_0_CFG0(v) (VER_CHK(v) ? 0x39000 : 0x033000)
|
||||
#define FEWC_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x39020 : 0x033020) \
|
||||
+ 4 * (n))
|
||||
|
||||
/* BEAC */
|
||||
#define BEAC0_PROF_FILTER_0_CFG5(v) (VER_CHK(v) ? 0x61014 : 0x049014)
|
||||
#define BEAC0_PROF_FILTER_0_CFG2(v) (VER_CHK(v) ? 0x61008 : 0x049008)
|
||||
#define BEAC0_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x61040 : 0x049040) \
|
||||
+ 4 * (n))
|
||||
#define BEAC0_PROF_CFG(v) (VER_CHK(v) ? 0x61080 : 0x049080)
|
||||
#define BEAC_INST_OFF (0x4000)
|
||||
|
||||
/* BERC */
|
||||
#define BERC_PROF_FILTER_0_CFG0(v) (VER_CHK(v) ? 0x3D000 : 0x039000)
|
||||
#define BERC_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x3D020 : 0x039020) \
|
||||
+ 4 * (n))
|
||||
#define BERC_PROF_CFG(v) (VER_CHK(v) ? 0x3D060 : 0x039060)
|
||||
|
||||
/* TRP */
|
||||
#define TRP_PROF_FILTER_0_CFG1 (0x024004)
|
||||
#define TRP_PROF_FILTER_0_CFG2 (0x024008)
|
||||
#define TRP_PROF_EVENT_n_CFG(n) (0x024020 + 4 * (n))
|
||||
#define TRP_SCID_n_STATUS(n) (0x000004 + 0x1000 * (n))
|
||||
|
||||
/* DRP */
|
||||
#define DRP_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x51010 : 0x044010) \
|
||||
+ 4 * (n))
|
||||
#define DRP_PROF_CFG(v) (VER_CHK(v) ? 0x51050 : 0x044050)
|
||||
|
||||
/* PMGR */
|
||||
#define PMGR_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x4D000 : 0x03F000) \
|
||||
+ 4 * (n))
|
||||
|
||||
#define PERFMON_COUNTER_n_CONFIG(v, n) ((VER_CHK(v) ? 0x36020 : 0x031020) \
|
||||
+ 4 * (n))
|
||||
#define PERFMON_MODE(v) (VER_CHK(v) ? 0x3600C : 0x03100C)
|
||||
#define PERFMON_DUMP(v) (VER_CHK4(v) ? 0x37000 : VER_CHK(v) ? \
|
||||
0x36010 : 0x031010)
|
||||
|
||||
#define LLCC_COUNTER_n_VALUE(v, n) ((VER_CHK4(v) ? 0x37008 : VER_CHK(v) ?\
|
||||
0x36060 : 0x31060) + 4 * (n))
|
||||
|
||||
#define EVENT_NUM_MAX (128)
|
||||
#define SCID_MAX (32)
|
||||
|
||||
/* Perfmon */
|
||||
#define CLEAR_ON_ENABLE BIT(31)
|
||||
#define CLEAR_ON_DUMP BIT(30)
|
||||
#define FREEZE_ON_SATURATE BIT(29)
|
||||
#define CHAINING_EN BIT(28)
|
||||
#define COUNT_CLOCK_EVENT BIT(24)
|
||||
|
||||
#define EVENT_SELECT_SHIFT (16)
|
||||
#define PERFMON_EVENT_SELECT_MASK GENMASK(EVENT_SELECT_SHIFT + 4,\
|
||||
EVENT_SELECT_SHIFT)
|
||||
#define PORT_SELECT_SHIFT (0)
|
||||
#define PERFMON_PORT_SELECT_MASK GENMASK(PORT_SELECT_SHIFT + 3,\
|
||||
PORT_SELECT_SHIFT)
|
||||
|
||||
#define MANUAL_MODE (0)
|
||||
#define TIMED_MODE (1)
|
||||
#define TRIGGER_MODE (2)
|
||||
#define MONITOR_EN_SHIFT (15)
|
||||
#define MONITOR_EN BIT(MONITOR_EN_SHIFT)
|
||||
#define PERFMON_MODE_MONITOR_EN_MASK GENMASK(MONITOR_EN_SHIFT + 0,\
|
||||
MONITOR_EN_SHIFT)
|
||||
#define MONITOR_MODE_SHIFT (0)
|
||||
#define PERFMON_MODE_MONITOR_MODE_MASK GENMASK(MONITOR_MODE_SHIFT + 0,\
|
||||
MONITOR_MODE_SHIFT)
|
||||
|
||||
#define MONITOR_DUMP BIT(0)
|
||||
|
||||
/* COMMON */
|
||||
#define BYTE_SCALING (1024)
|
||||
#define BEAT_SCALING (32)
|
||||
#define LB_CNT_SHIFT (28)
|
||||
#define LB_CNT_MASK GENMASK(LB_CNT_SHIFT + 3, \
|
||||
LB_CNT_SHIFT)
|
||||
#define NUM_MC_SHIFT (10)
|
||||
#define NUM_MC_MASK GENMASK(NUM_MC_SHIFT + 1, \
|
||||
NUM_MC_SHIFT)
|
||||
|
||||
#define BYTE_SCALING_SHIFT (16)
|
||||
#define PROF_CFG_BYTE_SCALING_MASK GENMASK(BYTE_SCALING_SHIFT + 11,\
|
||||
BYTE_SCALING_SHIFT)
|
||||
#define BEAT_SCALING_SHIFT (8)
|
||||
#define PROF_CFG_BEAT_SCALING_MASK GENMASK(BEAT_SCALING_SHIFT + 7,\
|
||||
BEAT_SCALING_SHIFT)
|
||||
#define PROF_EN_SHIFT (0)
|
||||
#define PROF_EN BIT(PROF_EN_SHIFT)
|
||||
#define PROF_CFG_EN_MASK GENMASK(PROF_EN_SHIFT + 0,\
|
||||
PROF_EN_SHIFT)
|
||||
|
||||
#define FILTER_EN_SHIFT (31)
|
||||
#define FILTER_EN BIT(FILTER_EN_SHIFT)
|
||||
#define FILTER_EN_MASK GENMASK(FILTER_EN_SHIFT + 0,\
|
||||
FILTER_EN_SHIFT)
|
||||
#define FILTER_0 (0)
|
||||
#define FILTER_0_MASK GENMASK(FILTER_0 + 0, \
|
||||
FILTER_0)
|
||||
#define FILTER_1 (1)
|
||||
#define FILTER_1_MASK GENMASK(FILTER_1 + 0, \
|
||||
FILTER_1)
|
||||
|
||||
#define FILTER_SEL_SHIFT (16)
|
||||
#define FILTER_SEL_MASK GENMASK(FILTER_SEL_SHIFT + 0,\
|
||||
FILTER_SEL_SHIFT)
|
||||
#define EVENT_SEL_SHIFT (0)
|
||||
#define EVENT_SEL_MASK GENMASK(EVENT_SEL_SHIFT + 5,\
|
||||
EVENT_SEL_SHIFT)
|
||||
#define EVENT_SEL_MASK7 GENMASK(EVENT_SEL_SHIFT + 6,\
|
||||
EVENT_SEL_SHIFT)
|
||||
|
||||
#define MEMTAGOPS_MASK_SHIFT (12)
|
||||
#define MEMTAGOPS_MASK_MASK GENMASK(MEMTAGOPS_MASK_SHIFT + 2, \
|
||||
MEMTAGOPS_MASK_SHIFT)
|
||||
|
||||
#define MEMTAGOPS_MATCH_SHIFT (10)
|
||||
#define MEMTAGOPS_MATCH_MASK GENMASK(MEMTAGOPS_MATCH_SHIFT + 2, \
|
||||
MEMTAGOPS_MATCH_SHIFT)
|
||||
|
||||
#define DIRTYINFO_MASK_SHIFT (1)
|
||||
#define DIRTYINFO_MASK_MASK GENMASK(DIRTYINFO_MASK_SHIFT + 1, \
|
||||
DIRTYINFO_MASK_SHIFT)
|
||||
|
||||
#define DIRTYINFO_MATCH_SHIFT (0)
|
||||
#define DIRTYINFO_MATCH_MASK GENMASK(DIRTYINFO_MATCH_SHIFT + 1, \
|
||||
DIRTYINFO_MATCH_SHIFT)
|
||||
|
||||
#define CACHEALLOC_MASK_SHIFT (16)
|
||||
#define CACHEALLOC_MASK_MASK GENMASK(CACHEALLOC_MASK_SHIFT + 3, \
|
||||
CACHEALLOC_MASK_SHIFT)
|
||||
#define CACHEALLOC_MATCH_SHIFT (12)
|
||||
#define CACHEALLOC_MATCH_MASK GENMASK(CACHEALLOC_MATCH_SHIFT + 3, \
|
||||
CACHEALLOC_MATCH_SHIFT)
|
||||
#define OPCODE_MASK_SHIFT (28)
|
||||
#define OPCODE_MASK_MASK GENMASK(OPCODE_MASK_SHIFT + 3, \
|
||||
OPCODE_MASK_SHIFT)
|
||||
#define OPCODE_MATCH_SHIFT (24)
|
||||
#define OPCODE_MATCH_MASK GENMASK(OPCODE_MATCH_SHIFT + 3, \
|
||||
OPCODE_MATCH_SHIFT)
|
||||
#define MID_MASK_SHIFT (16)
|
||||
#define MID_MASK_MASK GENMASK(MID_MASK_SHIFT + 15, \
|
||||
MID_MASK_SHIFT)
|
||||
#define MID_MATCH_SHIFT (0)
|
||||
#define MID_MATCH_MASK GENMASK(MID_MATCH_SHIFT + 15, \
|
||||
MID_MATCH_SHIFT)
|
||||
#define SCID_MASK_SHIFT (16)
|
||||
#define SCID_MASK_MASK GENMASK(SCID_MASK_SHIFT + 15, \
|
||||
SCID_MASK_SHIFT)
|
||||
#define SCID_MATCH_SHIFT (0)
|
||||
#define SCID_MATCH_MASK GENMASK(SCID_MATCH_SHIFT + 15, \
|
||||
SCID_MATCH_SHIFT)
|
||||
#define SCID_MULTI_MATCH_SHIFT (0)
|
||||
#define SCID_MULTI_MATCH_MASK GENMASK(SCID_MULTI_MATCH_SHIFT + 31, \
|
||||
SCID_MULTI_MATCH_SHIFT)
|
||||
#define PROFTAG_MASK_SHIFT (2)
|
||||
#define PROFTAG_MASK_MASK GENMASK(PROFTAG_MASK_SHIFT + 1,\
|
||||
PROFTAG_MASK_SHIFT)
|
||||
#define PROFTAG_MATCH_SHIFT (0)
|
||||
#define PROFTAG_MATCH_MASK GENMASK(PROFTAG_MATCH_SHIFT + 1,\
|
||||
PROFTAG_MATCH_SHIFT)
|
||||
/* FEAC */
|
||||
#define FEAC_SCALING_FILTER_SEL_SHIFT (2)
|
||||
#define FEAC_SCALING_FILTER_SEL_MASK GENMASK(FEAC_SCALING_FILTER_SEL_SHIFT \
|
||||
+ 0, \
|
||||
FEAC_SCALING_FILTER_SEL_SHIFT)
|
||||
#define FEAC_SCALING_FILTER_EN_SHIFT (1)
|
||||
#define FEAC_SCALING_FILTER_EN BIT(FEAC_SCALING_FILTER_EN_SHIFT)
|
||||
#define FEAC_SCALING_FILTER_EN_MASK GENMASK(FEAC_SCALING_FILTER_EN_SHIFT \
|
||||
+ 0, \
|
||||
FEAC_SCALING_FILTER_EN_SHIFT)
|
||||
|
||||
#define FEAC_WR_BEAT_FILTER_SEL_SHIFT (29)
|
||||
#define FEAC_WR_BEAT_FILTER_SEL_MASK GENMASK(FEAC_WR_BEAT_FILTER_SEL_SHIFT \
|
||||
+ 0, \
|
||||
FEAC_WR_BEAT_FILTER_SEL_SHIFT)
|
||||
#define FEAC_WR_BEAT_FILTER_EN_SHIFT (28)
|
||||
#define FEAC_WR_BEAT_FILTER_EN_MASK GENMASK(FEAC_WR_BEAT_FILTER_EN_SHIFT \
|
||||
+ 0, \
|
||||
FEAC_WR_BEAT_FILTER_EN_SHIFT)
|
||||
#define FEAC_WR_BEAT_FILTER_EN BIT(FEAC_WR_BEAT_FILTER_EN_SHIFT)
|
||||
#define FEAC_WR_BYTE_FILTER_SEL_SHIFT (6)
|
||||
#define FEAC_WR_BYTE_FILTER_SEL_MASK GENMASK(FEAC_WR_BYTE_FILTER_SEL_SHIFT \
|
||||
+ 0, \
|
||||
FEAC_WR_BYTE_FILTER_SEL_SHIFT)
|
||||
#define FEAC_WR_BYTE_FILTER_EN_SHIFT (5)
|
||||
#define FEAC_WR_BYTE_FILTER_EN_MASK GENMASK(FEAC_WR_BYTE_FILTER_EN_SHIFT \
|
||||
+ 0, \
|
||||
FEAC_WR_BYTE_FILTER_EN_SHIFT)
|
||||
#define FEAC_WR_BYTE_FILTER_EN BIT(FEAC_WR_BYTE_FILTER_EN_SHIFT)
|
||||
#define FEAC_RD_BEAT_FILTER_SEL_SHIFT (4)
|
||||
#define FEAC_RD_BEAT_FILTER_SEL_MASK GENMASK(FEAC_RD_BEAT_FILTER_SEL_SHIFT \
|
||||
+ 0, \
|
||||
FEAC_RD_BEAT_FILTER_SEL_SHIFT)
|
||||
#define FEAC_RD_BEAT_FILTER_EN_SHIFT (3)
|
||||
#define FEAC_RD_BEAT_FILTER_EN_MASK GENMASK(FEAC_RD_BEAT_FILTER_EN_SHIFT \
|
||||
+ 0, \
|
||||
FEAC_RD_BEAT_FILTER_EN_SHIFT)
|
||||
#define FEAC_RD_BEAT_FILTER_EN BIT(FEAC_RD_BEAT_FILTER_EN_SHIFT)
|
||||
#define FEAC_RD_BYTE_FILTER_SEL_SHIFT (2)
|
||||
#define FEAC_RD_BYTE_FILTER_SEL_MASK GENMASK(FEAC_RD_BYTE_FILTER_SEL_SHIFT \
|
||||
+ 0, \
|
||||
FEAC_RD_BYTE_FILTER_SEL_SHIFT)
|
||||
#define FEAC_RD_BYTE_FILTER_EN_SHIFT (1)
|
||||
#define FEAC_RD_BYTE_FILTER_EN_MASK GENMASK(FEAC_RD_BYTE_FILTER_EN_SHIFT \
|
||||
+ 0, \
|
||||
FEAC_RD_BYTE_FILTER_EN_SHIFT)
|
||||
#define FEAC_RD_BYTE_FILTER_EN BIT(FEAC_RD_BYTE_FILTER_EN_SHIFT)
|
||||
/* BEAC */
|
||||
#define BEAC_PROFTAG_MASK_SHIFT (14)
|
||||
#define BEAC_PROFTAG_MASK_MASK GENMASK(BEAC_PROFTAG_MASK_SHIFT + 1,\
|
||||
BEAC_PROFTAG_MASK_SHIFT)
|
||||
#define BEAC_PROFTAG_MATCH_SHIFT (12)
|
||||
#define BEAC_PROFTAG_MATCH_MASK GENMASK(BEAC_PROFTAG_MATCH_SHIFT + 1,\
|
||||
BEAC_PROFTAG_MATCH_SHIFT)
|
||||
#define BEAC_MC_PROFTAG_SHIFT (1)
|
||||
#define BEAC_MC_PROFTAG_MASK GENMASK(BEAC_MC_PROFTAG_SHIFT + 1,\
|
||||
BEAC_MC_PROFTAG_SHIFT)
|
||||
#define BEAC_WR_BEAT_FILTER_SEL_SHIFT (6)
|
||||
#define BEAC_WR_BEAT_FILTER_SEL_MASK GENMASK(BEAC_WR_BEAT_FILTER_SEL_SHIFT \
|
||||
+ 0, \
|
||||
BEAC_WR_BEAT_FILTER_SEL_SHIFT)
|
||||
#define BEAC_WR_BEAT_FILTER_EN_SHIFT (5)
|
||||
#define BEAC_WR_BEAT_FILTER_EN_MASK GENMASK(BEAC_WR_BEAT_FILTER_EN_SHIFT \
|
||||
+ 0, \
|
||||
BEAC_WR_BEAT_FILTER_EN_SHIFT)
|
||||
#define BEAC_WR_BEAT_FILTER_EN BIT(BEAC_WR_BEAT_FILTER_EN_SHIFT)
|
||||
#define BEAC_RD_BEAT_FILTER_SEL_SHIFT (4)
|
||||
#define BEAC_RD_BEAT_FILTER_SEL_MASK GENMASK(BEAC_RD_BEAT_FILTER_SEL_SHIFT \
|
||||
+ 0, \
|
||||
BEAC_RD_BEAT_FILTER_SEL_SHIFT)
|
||||
#define BEAC_RD_BEAT_FILTER_EN_SHIFT (3)
|
||||
#define BEAC_RD_BEAT_FILTER_EN_MASK GENMASK(BEAC_RD_BEAT_FILTER_EN_SHIFT \
|
||||
+ 0, \
|
||||
BEAC_RD_BEAT_FILTER_EN_SHIFT)
|
||||
#define BEAC_RD_BEAT_FILTER_EN BIT(BEAC_RD_BEAT_FILTER_EN_SHIFT)
|
||||
/* TRP */
|
||||
#define TRP_SCID_MATCH_SHIFT (0)
|
||||
#define TRP_SCID_MATCH_MASK GENMASK(TRP_SCID_MATCH_SHIFT + 4,\
|
||||
TRP_SCID_MATCH_SHIFT)
|
||||
#define TRP_SCID_MASK_SHIFT (8)
|
||||
#define TRP_SCID_MASK_MASK GENMASK(TRP_SCID_MASK_SHIFT + 4,\
|
||||
TRP_SCID_MASK_SHIFT)
|
||||
#define TRP_WAY_ID_MATCH_SHIFT (16)
|
||||
#define TRP_WAY_ID_MATCH_MASK GENMASK(TRP_WAY_ID_MATCH_SHIFT + 3,\
|
||||
TRP_WAY_ID_MATCH_SHIFT)
|
||||
#define TRP_WAY_ID_MASK_SHIFT (20)
|
||||
#define TRP_WAY_ID_MASK_MASK GENMASK(TRP_WAY_ID_MASK_SHIFT + 3,\
|
||||
TRP_WAY_ID_MASK_SHIFT)
|
||||
#define TRP_PROFTAG_MATCH_SHIFT (24)
|
||||
#define TRP_PROFTAG_MATCH_MASK GENMASK(TRP_PROFTAG_MATCH_SHIFT + 1,\
|
||||
TRP_PROFTAG_MATCH_SHIFT)
|
||||
#define TRP_PROFTAG_MASK_SHIFT (28)
|
||||
#define TRP_PROFTAG_MASK_MASK GENMASK(TRP_PROFTAG_MASK_SHIFT + 1,\
|
||||
TRP_PROFTAG_MASK_SHIFT)
|
||||
|
||||
#define TRP_SCID_STATUS_ACTIVE_SHIFT (0)
|
||||
#define TRP_SCID_STATUS_ACTIVE_MASK GENMASK( \
|
||||
TRP_SCID_STATUS_ACTIVE_SHIFT \
|
||||
+ 0, \
|
||||
TRP_SCID_STATUS_ACTIVE_SHIFT)
|
||||
#define TRP_SCID_STATUS_DEACTIVE_SHIFT (1)
|
||||
#define TRP_SCID_STATUS_CURRENT_CAP_SHIFT (16)
|
||||
#define TRP_SCID_STATUS_CURRENT_CAP_MASK GENMASK( \
|
||||
TRP_SCID_STATUS_CURRENT_CAP_SHIFT \
|
||||
+ 14, \
|
||||
TRP_SCID_STATUS_CURRENT_CAP_SHIFT)
|
||||
|
||||
#define MAJOR_VER_MASK (0xFF000000)
|
||||
#define BRANCH_MASK (0x00FF0000)
|
||||
#define MINOR_MASK (0x0000FF00)
|
||||
#define LLCC_VERSION_1 (0x01010200)
|
||||
#define LLCC_VERSION_2 (0x02000000)
|
||||
#define LLCC_VERSION_3 (0x03000000)
|
||||
#define LLCC_VERSION_4 (0x04000000)
|
||||
#define MAJOR_REV_NO(v) ((v & MAJOR_VER_MASK) >> 24)
|
||||
#define BRANCH_NO(v) ((v & BRANCH_MASK) >> 16)
|
||||
#define MINOR_NO(v) ((v & MINOR_MASK) >> 8)
|
||||
#define REV_0 (0x0)
|
||||
#define REV_1 (0x1)
|
||||
#define REV_2 (0x2)
|
||||
#define BANK_OFFSET (0x80000)
|
||||
|
||||
#endif /* _SOC_QCOM_LLCC_PERFMON_H_ */
|
||||
Loading…
Reference in New Issue
Block a user