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clk: qcom: gcc-sm8750: Use common clock controller probe data

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Move the always-on branch register offsets into a critical_cbcrs array,
describe the DFS RCGs through qcom_cc_driver_data and move the register
programming into the clk_regs_configure callback.

Use qcom_cc_probe() to perform the common initialization instead of
open-coding it in the driver's probe.

Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-34-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Abel Vesa 2026-09-24 15:06:46 +03:00 committed by Bjorn Andersson
parent 58edd47f42
commit 4423afe852
1 changed files with 33 additions and 43 deletions
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76
drivers/clk/qcom/gcc-sm8750.c
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@ -3188,7 +3188,39 @@ static const struct regmap_config gcc_sm8750_regmap_config = {
.fast_io = true,
};
static const u32 gcc_sm8750_critical_cbcrs[] = {
0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */
0x26004, /* GCC_CAMERA_AHB_CLK */
0x26034, /* GCC_CAMERA_XO_CLK */
0x27004, /* GCC_DISP_AHB_CLK */
0x9f004, /* GCC_EVA_AHB_CLK */
0x9f01c, /* GCC_EVA_XO_CLK */
0x71004, /* GCC_GPU_CFG_AHB_CLK */
0x32004, /* GCC_VIDEO_AHB_CLK */
0x32038, /* GCC_VIDEO_XO_CLK */
};
static void gcc_sm8750_regs_configure(struct device *dev, struct regmap *regmap)
{
/* Keep GCC_PCIE_RSCC_CFG_AHB_CLK and GCC_PCIE_RSCC_XO_CLK enabled. */
regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20));
regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21));
/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
}
static const struct qcom_cc_driver_data gcc_sm8750_driver_data = {
.clk_cbcrs = gcc_sm8750_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sm8750_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
.clk_regs_configure = gcc_sm8750_regs_configure,
};
static const struct qcom_cc_desc gcc_sm8750_desc = {
.driver_data = &gcc_sm8750_driver_data,
.config = &gcc_sm8750_regmap_config,
.clks = gcc_sm8750_clocks,
.num_clks = ARRAY_SIZE(gcc_sm8750_clocks),
@ -3207,49 +3239,7 @@ MODULE_DEVICE_TABLE(of, gcc_sm8750_match_table);
static int gcc_sm8750_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm8750_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
/*
* Keep clocks always enabled:
* gcc_cam_bist_mclk_ahb_clk
* gcc_camera_ahb_clk
* gcc_camera_xo_clk
* gcc_disp_ahb_clk
* gcc_eva_ahb_clk
* gcc_eva_xo_clk
* gcc_gpu_cfg_ahb_clk
* gcc_video_ahb_clk
* gcc_video_xo_clk
* gcc_pcie_rscc_cfg_ahb_clk
* gcc_pcie_rscc_xo_clk
*/
qcom_branch_set_clk_en(regmap, 0xa0004);
qcom_branch_set_clk_en(regmap, 0x26004);
qcom_branch_set_clk_en(regmap, 0x26034);
qcom_branch_set_clk_en(regmap, 0x27004);
qcom_branch_set_clk_en(regmap, 0x9f004);
qcom_branch_set_clk_en(regmap, 0x9f01c);
qcom_branch_set_clk_en(regmap, 0x71004);
qcom_branch_set_clk_en(regmap, 0x32004);
qcom_branch_set_clk_en(regmap, 0x32038);
regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20));
regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21));
/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
return qcom_cc_really_probe(&pdev->dev, &gcc_sm8750_desc, regmap);
return qcom_cc_probe(pdev, &gcc_sm8750_desc);
}
static struct platform_driver gcc_sm8750_driver = {