github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-28 17:13:52 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm64: dts: qcom: qcs8300: Add eMMC support

Browse Source 
Add eMMC support for qcs8300 board.

Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250716085125.27169-2-quic_sayalil@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Sayali Lokhande 2025-07-16 14:21:24 +05:30 committed by Bjorn Andersson
parent bae72efa3c
commit 43b8556e82
1 changed files with 113 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

113
arch/arm64/boot/dts/qcom/qcs8300.dtsi
View File

@ -4120,6 +4120,69 @@ cti@6900000 {
clock-names = "apb_pclk";
};
sdhc_1: mmc@87c4000 {
compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5";
reg = <0x0 0x087c4000 0x0 0x1000>,
<0x0 0x087c5000 0x0 0x1000>;
reg-names = "hc",
"cqhci";
interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq",
"pwr_irq";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface",
"core",
"xo";
resets = <&gcc GCC_SDCC1_BCR>;
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&sdhc1_opp_table>;
iommus = <&apps_smmu 0x0 0x0>;
interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "sdhc-ddr",
"cpu-sdhc";
qcom,dll-config = <0x000f64ee>;
qcom,ddr-config = <0x80040868>;
supports-cqe;
dma-coherent;
status = "disabled";
sdhc1_opp_table: opp-table {
compatible = "operating-points-v2";
opp-50000000 {
opp-hz = /bits/ 64 <50000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
usb_1_hsphy: phy@8904000 {
compatible = "qcom,qcs8300-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
@ -5325,6 +5388,56 @@ qup_uart16_rx: qup-uart16-rx-state {
pins = "gpio13";
function = "qup2_se0";
};
sdc1_state_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
drive-strength = <16>;
bias-disable;
};
cmd-pins {
pins = "sdc1_cmd";
drive-strength = <10>;
bias-pull-up;
};
data-pins {
pins = "sdc1_data";
drive-strength = <10>;
bias-pull-up;
};
rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc1_state_off: sdc1-off-state {
clk-pins {
pins = "sdc1_clk";
drive-strength = <2>;
bias-bus-hold;
};
cmd-pins {
pins = "sdc1_cmd";
drive-strength = <2>;
bias-bus-hold;
};
data-pins {
pins = "sdc1_data";
drive-strength = <2>;
bias-bus-hold;
};
rclk-pins {
pins = "sdc1_rclk";
bias-bus-hold;
};
};
};
sram: sram@146d8000 {