mirror of
https://github.com/torvalds/linux.git
synced 2026-05-24 15:12:13 +02:00
Qualcomm Arm64 DeviceTree for v6.20
Introduce the Kaanapali SoC, with the MTP and QRD devices. Introduce support for the Milos SoC (SM7635) and initial support for the Fairphone (Gen 6) device on this platform. Add the QCS6490-based RubikPI3 board, the QRB2210-based Arduino UnoQ, the X Elite-based Medion SPRCHRGD 14 S1 and Surface Pro 11 laptops, and the SDM845-based Pixel 3 and Pixel 3 XL devices. On the Kodiak-based (QCS6490) RB3Gen2 the TC9563 PCIe switch controller is described. On Lemans (SA8775P/QCS9075) the GPU and crypto blocks are added. IO-regions and clocks are added to interconnect nodes to allow QoS configuration. GPU, TPM and USB support are enabled on the evaluation kit (EVK). On Monaco (QCS8300) the two PCIe controllers, the camera subsystem, tsens, display subsystem, crypto, CPUfreq, and coresight are added. On the evaluation kit (EVK) the PCIe busses are enabled, together with an AMC6821-based fan controller and the ST33 TPM chip. On MSM8939 the camera subsystem is described. The Asus ZenFone 2 Laser/Selfie gains battery and hall sensor support. On the Agatti-based RB1 board PM8008 is described and an overlay for the Vision mezzanine is introduced. On SDM630 the compute DSP remoteproc, FastRPC and related entites are described. The LPASS LPI pinctrl node is described. On SDM845-based OnePlus device the bootloader framebuffer and its resources are described, to improve the transition. On the SDM845-based devices from OnePlus, SHIFT, and Xiaomi ath10k calibration variants are specified. The sensor remoteproc is enabled on Xiaomi Pocophone F1. On SM7225-based Fairphone FP4 regulators for the cameras are described, and the camera EEPROM is added. On SM8650 the camera subsystem is described. On the QRD the Samsung S5KJN1 camera sensor is added, and for the HDK an overlay for the "Rear Camera Card" is added. On SM8750 CPUfreq, SDCHCI and Iris (video encode/decode) support are added, and missing - required - properties for the BAM DMA is added. These are then enabled on the MTP. On Talos (SM6150/QCS615) PMU, DisplayPort, and USB/DP combo PHY are added. DisplayPort is enabled on the Talos Ride board. On Hamoa (X Elite) add crypto engine, missing TCSR reference clocks, and random number generator block. The soc bus address width is corrected to match the hardware. On the Lenovo Thinkpad T14s HDMI and audio playback over DisplayPort is introduced. HDMI, Iris (video encode/decode) and PS8830 retimers are described for the ASUS Vivobook S 15. On the Hamoa evaluation kit (EVK) PCIe busses, WiFi, backlight, TPM and RG (red/green) LEDs are described. Enable QSEECOM, and thereby UEFI variable access, on the Medion SPRCHRGD 14 S1 (commit should have been on drivers branch). -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmluY0UACgkQCx85Pw2Z rcULshAA2wZmfS4CeeZjIGUMbZg+ntby1xUJ4cKTeUR9IDd86L57qAkhHCNaP/ST 8ta22+4W9uId2zDTyxxmXbf5rTLIkc+t0dLjkl48HHmu6Kmxc2qALwcW7m2Cw/AI 3MAXUxVMmTM8BKvxSqW4lzNtQehxMXuErxXzVyUdzHMyiard25HUmXuMTsbIcteK yXr+SsAfisSjLTYAYhXkRihPK6OqYO9LkO1pah1Uf1pFY4FtJCbCEQR3a4uSTaQf u/NMQAc83LcboM2al1eHVU9fCeoA/oH/i6VZfpEAQLFf7cvsDP6f8CZF8RDWs1NE CdISQQdZxmgIfCawq5yt2765NR91Q8E64e49GSi56FWTEX+WBdohLR1qRLl7OrNM /rlvB29GhFTpxCjV5JwoAGacS3dn2MScNSXQSQNMRZBpDgGMM2PtnyOc+IhjMb+2 vOZrU+RS7eph6d9++yrIAMZfnEo8NtwVo0Eu3n0LmPmn4PK/2Kc+OS0Vc8r7IwBI qrAj4kkFGsMkfTEH2m4OO3lFH/Dw04E/YX1bSx3uFBkf8oQZrzmQJmn6kUT2MY0a 9rIJgnoo1R8d6MRAFkEKQqaRisWqEhnN3EZvn1bQj+0HlC5o3AHgjZQhwuZ/y/3B DvD7sSV1qSkbF/Dxcy4VRXZI+T6PgybrbL/yF+CD6cZiR4Grw8w= =qT6q -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml3gp8ACgkQmmx57+YA GNmhbA//bKzmRMoV1kx7czXgCfAbSq0SAUNbHs294Zkog/8ILBWnSYiS1smMlKfe W7c9x/7QT1myy2TiEZ2wDGzGWC/7benTu5HHGSL+UTSc3vVfKb3wpN021kuhxfhW fNpATd6oiOtuGfURgaZlXHaJlDS8TDXr+jJ8lgDKUuMmyJPpBf265/eyS8pSCoVR l6ImLT3Im2G4qXhYV7LzApTqe3wu6H6AW2EGPrAHWz4WrebTOzAr2yEY0CPOsPqA EnF2slYnPsRYz7RwkBwXM8gSX7711iGwOp/xQWIqmZxHaQa915w816bnPLzWxJTg j384ly4sJw/C047iLQdZBaqgGGU9Pu8/3iK1K0mlnfc3NmF1KeaSu3KKB4XxLkF/ +zw1gFjU6xCbfphHk44f8+hQdsIDa6wpL2jV4VdAE989wtOH2pIPS1WRboZCcvLz LummFnQigACAfwKygnmHGIEtVA1rw0U5wfRdvVq2slv2Kfrye5x92QgY/euuR2wW 7XWIubZESPHqvBPSa2bG7XNcd5gG+EaSZg0apJ6s9JbMm1PHjtKbnEqmv2E5GYUE bO3/XPrAalQ+bpN7TvCPkoFgD3Qr6SPK1Du/zQgIf0i5L/CGKKdaE/EVcmXSOOPR 4MH7kQQx7zcQ6i2OUOfDuGZemGGLOXXRZmGsJpY686gsLg6FYN8= =3Isi -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm Arm64 DeviceTree for v6.20 Introduce the Kaanapali SoC, with the MTP and QRD devices. Introduce support for the Milos SoC (SM7635) and initial support for the Fairphone (Gen 6) device on this platform. Add the QCS6490-based RubikPI3 board, the QRB2210-based Arduino UnoQ, the X Elite-based Medion SPRCHRGD 14 S1 and Surface Pro 11 laptops, and the SDM845-based Pixel 3 and Pixel 3 XL devices. On the Kodiak-based (QCS6490) RB3Gen2 the TC9563 PCIe switch controller is described. On Lemans (SA8775P/QCS9075) the GPU and crypto blocks are added. IO-regions and clocks are added to interconnect nodes to allow QoS configuration. GPU, TPM and USB support are enabled on the evaluation kit (EVK). On Monaco (QCS8300) the two PCIe controllers, the camera subsystem, tsens, display subsystem, crypto, CPUfreq, and coresight are added. On the evaluation kit (EVK) the PCIe busses are enabled, together with an AMC6821-based fan controller and the ST33 TPM chip. On MSM8939 the camera subsystem is described. The Asus ZenFone 2 Laser/Selfie gains battery and hall sensor support. On the Agatti-based RB1 board PM8008 is described and an overlay for the Vision mezzanine is introduced. On SDM630 the compute DSP remoteproc, FastRPC and related entites are described. The LPASS LPI pinctrl node is described. On SDM845-based OnePlus device the bootloader framebuffer and its resources are described, to improve the transition. On the SDM845-based devices from OnePlus, SHIFT, and Xiaomi ath10k calibration variants are specified. The sensor remoteproc is enabled on Xiaomi Pocophone F1. On SM7225-based Fairphone FP4 regulators for the cameras are described, and the camera EEPROM is added. On SM8650 the camera subsystem is described. On the QRD the Samsung S5KJN1 camera sensor is added, and for the HDK an overlay for the "Rear Camera Card" is added. On SM8750 CPUfreq, SDCHCI and Iris (video encode/decode) support are added, and missing - required - properties for the BAM DMA is added. These are then enabled on the MTP. On Talos (SM6150/QCS615) PMU, DisplayPort, and USB/DP combo PHY are added. DisplayPort is enabled on the Talos Ride board. On Hamoa (X Elite) add crypto engine, missing TCSR reference clocks, and random number generator block. The soc bus address width is corrected to match the hardware. On the Lenovo Thinkpad T14s HDMI and audio playback over DisplayPort is introduced. HDMI, Iris (video encode/decode) and PS8830 retimers are described for the ASUS Vivobook S 15. On the Hamoa evaluation kit (EVK) PCIe busses, WiFi, backlight, TPM and RG (red/green) LEDs are described. Enable QSEECOM, and thereby UEFI variable access, on the Medion SPRCHRGD 14 S1 (commit should have been on drivers branch). * tag 'qcom-arm64-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (155 commits) dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings for Kaanapali arm64: dts: qcom: lemans: enable static TPDM arm64: dts: qcom: kodiak: Add memory region for audiopd arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: add HDMI nodes arm64: dts: qcom: x1e: bus is 40-bits (fix 64GB models) arm64: dts: qcom: lemans; Add EL2 overlay arm64: dts: qcom: sm8150: add uart13 arm64: dts: qcom: sdm845-db845c: specify power for WiFi CH1 arm64: dts: qcom: sdm845-db845c: drop CS from SPIO0 arm64: dts: qcom: qrb4210-rb2: Fix UART3 wakeup IRQ storm arm64: dts: qcom: sm6125-ginkgo: Fix missing msm-id subtype arm64: dts: qcom: qcs8300: Add GPU cooling arm64: dts: qcom: sa8775p: Add reg and clocks for QoS configuration arm64: dts: qcom: hamoa-iot-evk: Enable TPM (ST33) on SPI11 arm64: dts: qcom: talos: Add PMU support arm64: dts: qcom: talos: switch to interrupt-cells 4 to add PPI partitions arm64: dts: qcom: ipq9574: Complete USB DWC3 wrapper interrupts arm64: dts: qcom: ipq5018: Correct USB DWC3 wrapper interrupts arm64: dts: qcom: monaco: Add CTCU and ETR nodes ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
43b1d60361
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@ -61,6 +61,11 @@ properties:
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- qcom,apq8084-sbc
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- const: qcom,apq8084
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- items:
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- enum:
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- fairphone,fp6
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- const: qcom,milos
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- items:
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- enum:
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- microsoft,dempsey
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@ -327,6 +332,12 @@ properties:
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- qcom,ipq9574-ap-al02-c9
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- const: qcom,ipq9574
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- items:
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- enum:
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- qcom,kaanapali-mtp
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- qcom,kaanapali-qrd
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- const: qcom,kaanapali
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- description: Sierra Wireless MangOH Green with WP8548 Module
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items:
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- const: swir,mangoh-green-wp8548
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@ -336,6 +347,7 @@ properties:
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- description: Qualcomm Technologies, Inc. Robotics RB1
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items:
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- enum:
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- arduino,imola
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- qcom,qrb2210-rb1
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- const: qcom,qrb2210
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- const: qcom,qcm2290
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@ -348,6 +360,7 @@ properties:
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- qcom,qcs6490-rb3gen2
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- radxa,dragon-q6a
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- shift,otter
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- thundercomm,rubikpi3
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- const: qcom,qcm6490
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- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
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@ -900,6 +913,8 @@ properties:
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- items:
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- enum:
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- google,blueline
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- google,crosshatch
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- huawei,planck
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- lenovo,yoga-c630
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- lg,judyln
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@ -1067,6 +1082,19 @@ properties:
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- const: qcom,x1e78100
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- const: qcom,x1e80100
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- items:
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- enum:
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- medion,sprchrgd14s1
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- tuxedo,elite14gen1
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- const: qcom,x1e78100
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- const: qcom,x1e80100
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- items:
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- const: microsoft,denali-lcd
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- const: microsoft,denali
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- const: qcom,x1p64100
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- const: qcom,x1e80100
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- items:
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- enum:
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- asus,vivobook-s15
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@ -1089,6 +1117,11 @@ properties:
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- const: qcom,hamoa-iot-som
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- const: qcom,x1e80100
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- items:
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- const: microsoft,denali-oled
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- const: microsoft,denali
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- const: qcom,x1e80100
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- items:
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- enum:
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- asus,zenbook-a14-ux3407qa-lcd
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@ -62,6 +62,9 @@ properties:
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- description: USB4_1 PHY max PIPE clock source
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- description: USB4_2 PHY PCIE PIPE clock source
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- description: USB4_2 PHY max PIPE clock source
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- description: UFS PHY RX Symbol 0 clock source
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- description: UFS PHY RX Symbol 1 clock source
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- description: UFS PHY TX Symbol 0 clock source
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power-domains:
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description:
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@ -121,7 +124,10 @@ examples:
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<&usb4_1_phy_pcie_pipe_clk>,
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<&usb4_1_phy_max_pipe_clk>,
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<&usb4_2_phy_pcie_pipe_clk>,
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<&usb4_2_phy_max_pipe_clk>;
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<&usb4_2_phy_max_pipe_clk>,
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<&ufs_phy_rx_symbol_0>,
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<&ufs_phy_rx_symbol_1>,
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<&ufs_phy_tx_symbol_0>;
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power-domains = <&rpmhpd RPMHPD_CX>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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@ -19,6 +19,8 @@ properties:
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- items:
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- enum:
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- qcom,glymur-cpucp-mbox
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- qcom,kaanapali-cpucp-mbox
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- qcom,sm8750-cpucp-mbox
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- const: qcom,x1e80100-cpucp-mbox
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- enum:
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- qcom,x1e80100-cpucp-mbox
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@ -24,6 +24,8 @@ properties:
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compatible:
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items:
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- enum:
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- qcom,glymur-ipcc
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- qcom,kaanapali-ipcc
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- qcom,milos-ipcc
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- qcom,qcs8300-ipcc
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- qcom,qdu1000-ipcc
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@ -158,6 +158,8 @@ patternProperties:
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description: Arctic Sand
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"^arcx,.*":
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description: arcx Inc. / Archronix Inc.
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"^arduino,.*":
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description: Arduino SRL
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"^argon40,.*":
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description: Argon 40 Technologies Limited
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"^ariaboard,.*":
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@ -995,6 +997,8 @@ patternProperties:
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description: Mustek Limited
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"^mediatek,.*":
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description: MediaTek Inc.
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"^medion,.*":
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description: Medion AG
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"^megachips,.*":
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description: MegaChips
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"^mele,.*":
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@ -1697,6 +1701,8 @@ patternProperties:
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description: Theobroma Systems Design und Consulting GmbH
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"^turing,.*":
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description: Turing Machines, Inc.
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"^tuxedo,.*":
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description: TUXEDO Computers GmbH
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"^tyan,.*":
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description: Tyan Computer Corporation
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"^tyhx,.*":
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@ -30,6 +30,8 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
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dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += kaanapali-qrd.dtb
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dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb
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lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo
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@ -37,6 +39,11 @@ lemans-evk-camera-dtbs := lemans-evk.dtb lemans-evk-camera.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera-csi1-imx577.dtb
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dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera.dtb
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lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb
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dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
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@ -138,12 +145,25 @@ qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2
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dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-rubikpi3.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
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qcs9100-ride-el2-dtbs := qcs9100-ride.dtb lemans-el2.dtbo
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qcs9100-ride-r3-el2-dtbs := qcs9100-ride-r3.dtb lemans-el2.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-el2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3-el2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qrb2210-arduino-imola.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
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qrb2210-rb1-vision-mezzanine-dtbs := qrb2210-rb1.dtb qrb2210-rb1-vision-mezzanine.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1-vision-mezzanine.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
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@ -250,6 +270,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
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sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-crosshatch.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-blueline.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
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@ -315,8 +337,12 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8550-samsung-q5q.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb
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sm8650-hdk-display-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo
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sm8650-hdk-display-card-rear-camera-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo sm8650-hdk-rear-camera-card.dtbo
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sm8650-hdk-rear-camera-card-dtbs := sm8650-hdk.dtb sm8650-hdk-rear-camera-card.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card-rear-camera-card.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-rear-camera-card.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
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||||
|
|
@ -346,6 +372,8 @@ x1e80100-hp-omnibook-x14-el2-dtbs := x1e80100-hp-omnibook-x14.dtb x1-el2.dtbo
|
|||
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-hp-omnibook-x14.dtb x1e80100-hp-omnibook-x14-el2.dtb
|
||||
x1e80100-lenovo-yoga-slim7x-el2-dtbs := x1e80100-lenovo-yoga-slim7x.dtb x1-el2.dtbo
|
||||
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb x1e80100-lenovo-yoga-slim7x-el2.dtb
|
||||
x1e80100-medion-sprchrgd-14-s1-el2-dtbs := x1e80100-medion-sprchrgd-14-s1.dtb x1-el2.dtbo
|
||||
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-medion-sprchrgd-14-s1.dtb x1e80100-medion-sprchrgd-14-s1-el2.dtb
|
||||
x1e80100-microsoft-romulus13-el2-dtbs := x1e80100-microsoft-romulus13.dtb x1-el2.dtbo
|
||||
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb x1e80100-microsoft-romulus13-el2.dtb
|
||||
x1e80100-microsoft-romulus15-el2-dtbs := x1e80100-microsoft-romulus15.dtb x1-el2.dtbo
|
||||
|
|
@ -362,3 +390,5 @@ x1p42100-hp-omnibook-x14-el2-dtbs := x1p42100-hp-omnibook-x14.dtb x1-el2.dtbo
|
|||
dtb-$(CONFIG_ARCH_QCOM) += x1p42100-hp-omnibook-x14.dtb x1p42100-hp-omnibook-x14-el2.dtb
|
||||
x1p42100-lenovo-thinkbook-16-el2-dtbs := x1p42100-lenovo-thinkbook-16.dtb x1-el2.dtbo
|
||||
dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb
|
||||
x1p64100-microsoft-denali-el2-dtbs := x1p64100-microsoft-denali.dtb x1-el2.dtbo
|
||||
dtb-$(CONFIG_ARCH_QCOM) += x1p64100-microsoft-denali.dtb x1p64100-microsoft-denali-el2.dtb
|
||||
|
|
|
|||
|
|
@ -562,6 +562,13 @@ qup_uart1_default: qup-uart1-default-state {
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
qup_uart2_default: qup-uart2-default-state {
|
||||
pins = "gpio6", "gpio7", "gpio71", "gpio80";
|
||||
function = "qup2";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qup_uart3_default: qup-uart3-default-state {
|
||||
pins = "gpio8", "gpio9", "gpio10", "gpio11";
|
||||
function = "qup3";
|
||||
|
|
@ -597,6 +604,34 @@ cci1_default: cci1-default-state {
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
mclk0_default: mclk0-default-state {
|
||||
pins = "gpio20";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mclk1_default: mclk1-default-state {
|
||||
pins = "gpio21";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mclk2_default: mclk2-default-state {
|
||||
pins = "gpio27";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mclk3_default: mclk3-default-state {
|
||||
pins = "gpio28";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
sdc1_state_on: sdc1-on-state {
|
||||
clk-pins {
|
||||
pins = "sdc1_clk";
|
||||
|
|
@ -1315,6 +1350,23 @@ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@4a88000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0x0 0x04a88000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
clock-names = "se";
|
||||
pinctrl-0 = <&qup_uart2_default>;
|
||||
pinctrl-names = "default";
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
|
||||
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
|
||||
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
|
||||
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
|
||||
interconnect-names = "qup-core",
|
||||
"qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@4a8c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x0 0x04a8c000 0x0 0x4000>;
|
||||
|
|
|
|||
68
arch/arm64/boot/dts/qcom/glymur-ipcc.h
Normal file
68
arch/arm64/boot/dts/qcom/glymur-ipcc.h
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
#ifndef __DTS_GLYMUR_MAILBOX_IPCC_H
|
||||
#define __DTS_GLYMUR_MAILBOX_IPCC_H
|
||||
|
||||
/* Glymur physical client IDs */
|
||||
#define IPCC_MPROC_AOP 0
|
||||
#define IPCC_MPROC_TZ 1
|
||||
#define IPCC_MPROC_MPSS 2
|
||||
#define IPCC_MPROC_LPASS 3
|
||||
#define IPCC_MPROC_SLPI 4
|
||||
#define IPCC_MPROC_SDC 5
|
||||
#define IPCC_MPROC_CDSP 6
|
||||
#define IPCC_MPROC_NPU 7
|
||||
#define IPCC_MPROC_APSS 8
|
||||
#define IPCC_MPROC_GPU 9
|
||||
#define IPCC_MPROC_ICP 11
|
||||
#define IPCC_MPROC_VPU 12
|
||||
#define IPCC_MPROC_PCIE0 13
|
||||
#define IPCC_MPROC_PCIE1 14
|
||||
#define IPCC_MPROC_PCIE2 15
|
||||
#define IPCC_MPROC_SPSS 16
|
||||
#define IPCC_MPROC_PCIE3 19
|
||||
#define IPCC_MPROC_PCIE4 20
|
||||
#define IPCC_MPROC_PCIE5 21
|
||||
#define IPCC_MPROC_PCIE6 22
|
||||
#define IPCC_MPROC_TME 23
|
||||
#define IPCC_MPROC_WPSS 24
|
||||
#define IPCC_MPROC_PCIE7 44
|
||||
#define IPCC_MPROC_SOCCP 46
|
||||
|
||||
#define IPCC_COMPUTE_L0_LPASS 0
|
||||
#define IPCC_COMPUTE_L0_CDSP 1
|
||||
#define IPCC_COMPUTE_L0_APSS 2
|
||||
#define IPCC_COMPUTE_L0_GPU 3
|
||||
#define IPCC_COMPUTE_L0_CVP 6
|
||||
#define IPCC_COMPUTE_L0_ICP 7
|
||||
#define IPCC_COMPUTE_L0_VPU 8
|
||||
#define IPCC_COMPUTE_L0_DPU 9
|
||||
#define IPCC_COMPUTE_L0_SOCCP 11
|
||||
|
||||
#define IPCC_COMPUTE_L1_LPASS 0
|
||||
#define IPCC_COMPUTE_L1_CDSP 1
|
||||
#define IPCC_COMPUTE_L1_APSS 2
|
||||
#define IPCC_COMPUTE_L1_GPU 3
|
||||
#define IPCC_COMPUTE_L1_CVP 6
|
||||
#define IPCC_COMPUTE_L1_ICP 7
|
||||
#define IPCC_COMPUTE_L1_VPU 8
|
||||
#define IPCC_COMPUTE_L1_DPU 9
|
||||
#define IPCC_COMPUTE_L1_SOCCP 11
|
||||
|
||||
#define IPCC_PERIPH_LPASS 0
|
||||
#define IPCC_PERIPH_APSS 1
|
||||
#define IPCC_PERIPH_PCIE0 2
|
||||
#define IPCC_PERIPH_PCIE1 3
|
||||
#define IPCC_PERIPH_PCIE2 6
|
||||
#define IPCC_PERIPH_PCIE3 7
|
||||
#define IPCC_PERIPH_PCIE4 8
|
||||
#define IPCC_PERIPH_PCIE5 9
|
||||
#define IPCC_PERIPH_PCIE6 10
|
||||
#define IPCC_PERIPH_PCIE7 11
|
||||
#define IPCC_PERIPH_SOCCP 13
|
||||
#define IPCC_PERIPH_WPSS 16
|
||||
|
||||
#endif
|
||||
|
|
@ -5,7 +5,9 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include "hamoa-iot-som.dtsi"
|
||||
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Hamoa IoT EVK";
|
||||
|
|
@ -17,6 +19,16 @@ aliases {
|
|||
serial1 = &uart14;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pmk8550_pwm 0 5000000>;
|
||||
enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
|
||||
power-supply = <&vreg_edp_bl>;
|
||||
|
||||
pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
wcd938x: audio-codec {
|
||||
compatible = "qcom,wcd9385-codec";
|
||||
|
||||
|
|
@ -48,6 +60,32 @@ chosen {
|
|||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
connector3 {
|
||||
compatible = "usb-a-connector";
|
||||
label = "USB-3-Type-A";
|
||||
power-role = "source";
|
||||
|
||||
vbus-supply = <®ulator_usb3_vbus>;
|
||||
|
||||
port {
|
||||
connector_3_in: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
connector6 {
|
||||
compatible = "usb-a-connector";
|
||||
label = "USB-6-Type-A";
|
||||
power-role = "source";
|
||||
|
||||
vbus-supply = <®ulator_usb6_vbus>;
|
||||
|
||||
port {
|
||||
connector_4_in: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmic-glink {
|
||||
compatible = "qcom,x1e80100-pmic-glink",
|
||||
"qcom,sm8550-pmic-glink",
|
||||
|
|
@ -183,6 +221,22 @@ vreg_edp_3p3: regulator-edp-3p3 {
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_edp_bl: regulator-edp-bl {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VBL9";
|
||||
regulator-min-microvolt = <3600000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
|
||||
gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&edp_bl_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_nvme: regulator-nvme {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
|
|
@ -199,6 +253,48 @@ vreg_nvme: regulator-nvme {
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_pcie_12v: regulator-pcie-12v {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_PCIE_12V";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
|
||||
gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&pcie_x8_12v>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
vreg_pcie_3v3: regulator-pcie-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_PCIE_3P3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&pm_sde7_main_3p3_en>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
vreg_pcie_3v3_aux: regulator-pcie-3v3-aux {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_PCIE_3P3_AUX";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&pm_sde7_aux_3p3_en>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
/* Left unused as the retimer is not used on this board. */
|
||||
vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
|
||||
compatible = "regulator-fixed";
|
||||
|
|
@ -344,6 +440,26 @@ vreg_rtmr2_3p3: regulator-rtmr2-3p3 {
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
regulator_usb3_vbus: regulator-usb3-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "USB3_VBUS";
|
||||
gpio = <&pm8550ve_9_gpios 4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&usb3_en>;
|
||||
pinctrl-names = "default";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator_usb6_vbus: regulator-usb6-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "USB6_VBUS";
|
||||
gpio = <&pm8550ve_9_gpios 5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&usb6_en>;
|
||||
pinctrl-names = "default";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vph_pwr: regulator-vph-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
|
|
@ -534,7 +650,7 @@ wcn7850-pmu {
|
|||
bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
|
||||
wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&wcn_bt_en>;
|
||||
pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulators {
|
||||
|
|
@ -819,6 +935,8 @@ &mdss_dp3 {
|
|||
aux-bus {
|
||||
panel {
|
||||
compatible = "edp-panel";
|
||||
|
||||
backlight = <&backlight>;
|
||||
power-supply = <&vreg_edp_3p3>;
|
||||
|
||||
port {
|
||||
|
|
@ -844,10 +962,53 @@ &mdss_dp3_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3_port0 {
|
||||
vpcie12v-supply = <&vreg_pcie_12v>;
|
||||
vpcie3v3-supply = <&vreg_pcie_3v3>;
|
||||
vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>;
|
||||
|
||||
reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pcie4_port0 {
|
||||
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
wifi@0 {
|
||||
compatible = "pci17cb,1107";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
|
||||
vddaon-supply = <&vreg_pmu_aon_0p59>;
|
||||
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
|
||||
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
|
||||
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
|
||||
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
|
||||
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
|
||||
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
|
||||
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
|
||||
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie5 {
|
||||
vddpe-3v3-supply = <&vreg_wwan>;
|
||||
};
|
||||
|
||||
&pcie5_port0 {
|
||||
reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pcie6a {
|
||||
vddpe-3v3-supply = <&vreg_nvme>;
|
||||
};
|
||||
|
||||
&pcie6a_port0 {
|
||||
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pm8550_gpios {
|
||||
rtmr0_default: rtmr0-reset-n-active-state {
|
||||
pins = "gpio10";
|
||||
|
|
@ -868,6 +1029,17 @@ usb0_3p3_reg_en: usb0-3p3-reg-en-state {
|
|||
};
|
||||
};
|
||||
|
||||
&pm8550ve_8_gpios {
|
||||
pcie_x8_12v: pcie-12v-default-state {
|
||||
pins = "gpio8";
|
||||
function = "normal";
|
||||
output-enable;
|
||||
output-high;
|
||||
bias-pull-down;
|
||||
power-source = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pm8550ve_9_gpios {
|
||||
usb0_1p8_reg_en: usb0-1p8-reg-en-state {
|
||||
pins = "gpio8";
|
||||
|
|
@ -877,6 +1049,77 @@ usb0_1p8_reg_en: usb0-1p8-reg-en-state {
|
|||
input-disable;
|
||||
output-enable;
|
||||
};
|
||||
|
||||
usb3_en: usb3-en-state {
|
||||
pins = "gpio4";
|
||||
function = "normal";
|
||||
qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
|
||||
output-enable;
|
||||
power-source = <0>;
|
||||
};
|
||||
|
||||
usb6_en: usb6-en-state {
|
||||
pins = "gpio5";
|
||||
function = "normal";
|
||||
qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
|
||||
output-enable;
|
||||
power-source = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pm8550_pwm {
|
||||
status = "okay";
|
||||
|
||||
multi-led {
|
||||
color = <LED_COLOR_ID_MULTI>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmc8380_3_gpios {
|
||||
edp_bl_en: edp-bl-en-state {
|
||||
pins = "gpio4";
|
||||
function = "normal";
|
||||
power-source = <1>;
|
||||
input-disable;
|
||||
output-enable;
|
||||
};
|
||||
|
||||
edp_bl_reg_en: edp-bl-reg-en-state {
|
||||
pins = "gpio10";
|
||||
function = "normal";
|
||||
};
|
||||
};
|
||||
|
||||
&pmc8380_3_gpios {
|
||||
pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state {
|
||||
pins = "gpio8";
|
||||
function = "normal";
|
||||
output-enable;
|
||||
bias-pull-down;
|
||||
power-source = <0>;
|
||||
};
|
||||
|
||||
pm_sde7_main_3p3_en: pcie-main-3p3-default-state {
|
||||
pins = "gpio6";
|
||||
function = "normal";
|
||||
output-enable;
|
||||
bias-pull-down;
|
||||
power-source = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pmc8380_5_gpios {
|
||||
|
|
@ -890,6 +1133,17 @@ usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state {
|
|||
};
|
||||
};
|
||||
|
||||
&pmk8550_gpios {
|
||||
edp_bl_pwm: edp-bl-pwm-state {
|
||||
pins = "gpio5";
|
||||
function = "func3";
|
||||
};
|
||||
};
|
||||
|
||||
&pmk8550_pwm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&smb2360_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -917,6 +1171,16 @@ &smb2360_2_eusb2_repeater {
|
|||
vdd3-supply = <&vreg_l8b_3p0>;
|
||||
};
|
||||
|
||||
&spi11 {
|
||||
status = "okay";
|
||||
|
||||
tpm@0 {
|
||||
compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -1143,6 +1407,13 @@ wcn_bt_en: wcn-bt-en-state {
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
wcn_wlan_en: wcn-wlan-en-state {
|
||||
pins = "gpio117";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wwan_sw_en: wwan-sw-en-state {
|
||||
pins = "gpio221";
|
||||
function = "gpio";
|
||||
|
|
|
|||
|
|
@ -390,10 +390,21 @@ &gpu_zap_shader {
|
|||
firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
&pcie3 {
|
||||
pinctrl-0 = <&pcie3_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3_phy {
|
||||
vdda-phy-supply = <&vreg_l3c_0p8>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
|
@ -407,10 +418,21 @@ &pcie4_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
&pcie5 {
|
||||
pinctrl-0 = <&pcie5_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie5_phy {
|
||||
vdda-phy-supply = <&vreg_l3i_0p8>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a {
|
||||
pinctrl-0 = <&pcie6a_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
|
@ -453,6 +475,29 @@ &remoteproc_cdsp {
|
|||
&tlmm {
|
||||
gpio-reserved-ranges = <34 2>; /* TPM LP & INT */
|
||||
|
||||
pcie3_default: pcie3-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio144";
|
||||
function = "pcie3_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio143";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio145";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie4_default: pcie4-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio147";
|
||||
|
|
@ -476,6 +521,29 @@ wake-n-pins {
|
|||
};
|
||||
};
|
||||
|
||||
pcie5_default: pcie5-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio150";
|
||||
function = "pcie5_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio149";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio151";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie6a_default: pcie6a-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio153";
|
||||
|
|
|
|||
|
|
@ -791,8 +791,8 @@ soc: soc@0 {
|
|||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
dma-ranges = <0 0 0 0 0x10 0>;
|
||||
ranges = <0 0 0 0 0x10 0>;
|
||||
dma-ranges = <0 0 0 0 0x100 0>;
|
||||
ranges = <0 0 0 0 0x100 0>;
|
||||
|
||||
gcc: clock-controller@100000 {
|
||||
compatible = "qcom,x1e80100-gcc";
|
||||
|
|
@ -834,6 +834,9 @@ gcc: clock-controller@100000 {
|
|||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>;
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_CX>;
|
||||
|
|
@ -2937,7 +2940,7 @@ usb_1_ss1_qmpphy: phy@fda000 {
|
|||
reg = <0 0x00fda000 0 0x4000>;
|
||||
|
||||
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&tcsr TCSR_USB4_1_CLKREF_EN>,
|
||||
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
|
||||
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
|
||||
clock-names = "aux",
|
||||
|
|
@ -3008,7 +3011,7 @@ usb_1_ss2_qmpphy: phy@fdf000 {
|
|||
reg = <0 0x00fdf000 0 0x4000>;
|
||||
|
||||
clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&tcsr TCSR_USB4_2_CLKREF_EN>,
|
||||
<&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
|
||||
<&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
|
||||
clock-names = "aux",
|
||||
|
|
@ -3060,6 +3063,11 @@ usb_1_ss2_qmpphy_dp_in: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
rng: rng@10c3000 {
|
||||
compatible = "qcom,x1e80100-trng", "qcom,trng";
|
||||
reg = <0x0 0x010c3000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
cnoc_main: interconnect@1500000 {
|
||||
compatible = "qcom,x1e80100-cnoc-main";
|
||||
reg = <0 0x01500000 0 0x14400>;
|
||||
|
|
@ -3161,7 +3169,7 @@ usb_south_anoc: interconnect@1770000 {
|
|||
|
||||
mmss_noc: interconnect@1780000 {
|
||||
compatible = "qcom,x1e80100-mmss-noc";
|
||||
reg = <0 0x01780000 0 0x5B800>;
|
||||
reg = <0 0x01780000 0 0x5b800>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
|
|
@ -3253,9 +3261,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|||
|
||||
power-domains = <&gcc GCC_PCIE_3_GDSC>;
|
||||
|
||||
phys = <&pcie3_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
|
||||
0x5555 0x5555 0x5555 0x5555>;
|
||||
eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
|
||||
|
|
@ -3396,12 +3401,14 @@ opp-128000000-4 {
|
|||
};
|
||||
};
|
||||
|
||||
pcie3_port: pcie@0 {
|
||||
pcie3_port0: pcie@0 {
|
||||
device_type = "pci";
|
||||
compatible = "pciclass,0604";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
phys = <&pcie3_phy>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -3530,13 +3537,22 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|||
power-domains = <&gcc GCC_PCIE_6A_GDSC>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
|
||||
phys = <&pcie6a_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
|
||||
eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pcie6a_port0: pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
phys = <&pcie6a_phy>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
pcie6a_phy: phy@1bfc000 {
|
||||
|
|
@ -3662,12 +3678,21 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|||
power-domains = <&gcc GCC_PCIE_5_GDSC>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
|
||||
phys = <&pcie5_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pcie5_port0: pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
phys = <&pcie5_phy>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
pcie5_phy: phy@1c06000 {
|
||||
|
|
@ -3792,9 +3817,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|||
power-domains = <&gcc GCC_PCIE_4_GDSC>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
|
||||
phys = <&pcie4_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
|
||||
|
||||
status = "disabled";
|
||||
|
|
@ -3804,6 +3826,8 @@ pcie4_port0: pcie@0 {
|
|||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
phys = <&pcie4_phy>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -3845,6 +3869,32 @@ pcie4_phy: phy@1c0e000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
cryptobam: dma-controller@1dc4000 {
|
||||
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
|
||||
reg = <0x0 0x01dc4000 0x0 0x28000>;
|
||||
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
iommus = <&apps_smmu 0x480 0x0>,
|
||||
<&apps_smmu 0x481 0x0>;
|
||||
qcom,ee = <0>;
|
||||
qcom,controlled-remotely;
|
||||
num-channels = <20>;
|
||||
qcom,num-ees = <4>;
|
||||
};
|
||||
|
||||
crypto: crypto@1dfa000 {
|
||||
compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce";
|
||||
reg = <0x0 0x01dfa000 0x0 0x6000>;
|
||||
dmas = <&cryptobam 4>, <&cryptobam 5>;
|
||||
dma-names = "rx",
|
||||
"tx";
|
||||
iommus = <&apps_smmu 0x480 0x0>,
|
||||
<&apps_smmu 0x481 0x0>;
|
||||
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "memory";
|
||||
};
|
||||
|
||||
tcsr_mutex: hwlock@1f40000 {
|
||||
compatible = "qcom,tcsr-mutex";
|
||||
reg = <0 0x01f40000 0 0x20000>;
|
||||
|
|
@ -4136,7 +4186,7 @@ gem_noc: interconnect@26400000 {
|
|||
|
||||
nsp_noc: interconnect@320c0000 {
|
||||
compatible = "qcom,x1e80100-nsp-noc";
|
||||
reg = <0 0x320C0000 0 0xe080>;
|
||||
reg = <0 0x320c0000 0 0xe080>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
|
|
@ -4647,7 +4697,7 @@ lpass_lpiaon_noc: interconnect@7400000 {
|
|||
|
||||
lpass_lpicx_noc: interconnect@7430000 {
|
||||
compatible = "qcom,x1e80100-lpass-lpicx-noc";
|
||||
reg = <0 0x07430000 0 0x3A200>;
|
||||
reg = <0 0x07430000 0 0x3a200>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
|
|
@ -5579,6 +5629,7 @@ mdss_dp0: displayport-controller@ae90000 {
|
|||
phy-names = "dp";
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "DisplayPort0";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -5667,6 +5718,7 @@ mdss_dp1: displayport-controller@ae98000 {
|
|||
phy-names = "dp";
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "DisplayPort1";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -5755,6 +5807,7 @@ mdss_dp2: displayport-controller@ae9a000 {
|
|||
phy-names = "dp";
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "DisplayPort2";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -5838,6 +5891,7 @@ mdss_dp3: displayport-controller@aea0000 {
|
|||
phy-names = "dp";
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "DisplayPort3";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -5896,9 +5950,11 @@ mdss_dp2_phy: phy@aec2a00 {
|
|||
<0 0x0aec2000 0 0x1c8>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>;
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&tcsr TCSR_EDP_CLKREF_EN>;
|
||||
clock-names = "aux",
|
||||
"cfg_ahb";
|
||||
"cfg_ahb",
|
||||
"ref";
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_MX>;
|
||||
|
||||
|
|
@ -5916,9 +5972,11 @@ mdss_dp3_phy: phy@aec5a00 {
|
|||
<0 0x0aec5000 0 0x1c8>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>;
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&tcsr TCSR_EDP_CLKREF_EN>;
|
||||
clock-names = "aux",
|
||||
"cfg_ahb";
|
||||
"cfg_ahb",
|
||||
"ref";
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_MX>;
|
||||
|
||||
|
|
|
|||
|
|
@ -340,7 +340,7 @@ prng: rng@e3000 {
|
|||
};
|
||||
|
||||
tsens: thermal-sensor@4a9000 {
|
||||
compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
|
||||
compatible = "qcom,ipq5018-tsens";
|
||||
reg = <0x004a9000 0x1000>,
|
||||
<0x004a8000 0x1000>;
|
||||
|
||||
|
|
@ -571,8 +571,12 @@ usb: usb@8af8800 {
|
|||
compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
|
||||
reg = <0x08af8800 0x400>;
|
||||
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hs_phy_irq";
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event",
|
||||
"dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq";
|
||||
|
||||
clocks = <&gcc GCC_USB0_MASTER_CLK>,
|
||||
<&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
|
||||
|
|
|
|||
|
|
@ -765,8 +765,14 @@ usb3: usb@8af8800 {
|
|||
assigned-clock-rates = <200000000>,
|
||||
<24000000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event";
|
||||
interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event",
|
||||
"qusb2_phy",
|
||||
"dm_hs_phy_irq",
|
||||
"dp_hs_phy_irq";
|
||||
|
||||
resets = <&gcc GCC_USB_BCR>;
|
||||
status = "disabled";
|
||||
|
|
|
|||
58
arch/arm64/boot/dts/qcom/kaanapali-ipcc.h
Normal file
58
arch/arm64/boot/dts/qcom/kaanapali-ipcc.h
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
#ifndef __DTS_KAANAPALI_MAILBOX_IPCC_H
|
||||
#define __DTS_KAANAPALI_MAILBOX_IPCC_H
|
||||
|
||||
/* Physical client IDs */
|
||||
#define IPCC_MPROC_AOP 0
|
||||
#define IPCC_MPROC_TZ 1
|
||||
#define IPCC_MPROC_MPSS 2
|
||||
#define IPCC_MPROC_LPASS 3
|
||||
#define IPCC_MPROC_SDC 4
|
||||
#define IPCC_MPROC_CDSP 5
|
||||
#define IPCC_MPROC_APSS 6
|
||||
#define IPCC_MPROC_SOCCP 13
|
||||
#define IPCC_MPROC_DCP 14
|
||||
#define IPCC_MPROC_SPSS 15
|
||||
#define IPCC_MPROC_TME 16
|
||||
#define IPCC_MPROC_WPSS 17
|
||||
|
||||
#define IPCC_COMPUTE_L0_CDSP 2
|
||||
#define IPCC_COMPUTE_L0_APSS 3
|
||||
#define IPCC_COMPUTE_L0_GPU 4
|
||||
#define IPCC_COMPUTE_L0_CVP 8
|
||||
#define IPCC_COMPUTE_L0_CAM 9
|
||||
#define IPCC_COMPUTE_L0_CAM1 10
|
||||
#define IPCC_COMPUTE_L0_DCP 11
|
||||
#define IPCC_COMPUTE_L0_VPU 12
|
||||
#define IPCC_COMPUTE_L0_SOCCP 16
|
||||
|
||||
#define IPCC_COMPUTE_L1_CDSP 2
|
||||
#define IPCC_COMPUTE_L1_APSS 3
|
||||
#define IPCC_COMPUTE_L1_GPU 4
|
||||
#define IPCC_COMPUTE_L1_CVP 8
|
||||
#define IPCC_COMPUTE_L1_CAM 9
|
||||
#define IPCC_COMPUTE_L1_CAM1 10
|
||||
#define IPCC_COMPUTE_L1_DCP 11
|
||||
#define IPCC_COMPUTE_L1_VPU 12
|
||||
#define IPCC_COMPUTE_L1_SOCCP 16
|
||||
|
||||
#define IPCC_PERIPH_CDSP 2
|
||||
#define IPCC_PERIPH_APSS 3
|
||||
#define IPCC_PERIPH_PCIE0 4
|
||||
#define IPCC_PERIPH_PCIE1 5
|
||||
|
||||
#define IPCC_FENCE_CDSP 2
|
||||
#define IPCC_FENCE_APSS 3
|
||||
#define IPCC_FENCE_GPU 4
|
||||
#define IPCC_FENCE_CVP 8
|
||||
#define IPCC_FENCE_CAM 8
|
||||
#define IPCC_FENCE_CAM1 10
|
||||
#define IPCC_FENCE_DCP 11
|
||||
#define IPCC_FENCE_VPU 20
|
||||
#define IPCC_FENCE_SOCCP 24
|
||||
|
||||
#endif
|
||||
754
arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
Normal file
754
arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
Normal file
|
|
@ -0,0 +1,754 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include "kaanapali.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kaanapali MTP";
|
||||
compatible = "qcom,kaanapali-mtp", "qcom,kaanapali";
|
||||
chassis-type = "handset";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart7;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
clocks {
|
||||
xo_board: xo-board {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <76800000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sleep_clk: sleep-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32764>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
bi_tcxo_div2: bi-tcxo-div2-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK_A>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
regulators-0 {
|
||||
compatible = "qcom,pmh0101-rpmh-regulators";
|
||||
qcom,pmic-id = "B_E0";
|
||||
|
||||
vreg_bob1: bob1 {
|
||||
regulator-name = "vreg_bob1";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <4000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_bob2: bob2 {
|
||||
regulator-name = "vreg_bob2";
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <3552000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1b_1p8: ldo1 {
|
||||
regulator-name = "vreg_l1b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l2b_3p0: ldo2 {
|
||||
regulator-name = "vreg_l2b_3p0";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3048000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l4b_1p8: ldo4 {
|
||||
regulator-name = "vreg_l4b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l5b_3p1: ldo5 {
|
||||
regulator-name = "vreg_l5b_3p1";
|
||||
regulator-min-microvolt = <3100000>;
|
||||
regulator-max-microvolt = <3148000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l6b_1p8: ldo6 {
|
||||
regulator-name = "vreg_l6b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l7b_1p8: ldo7 {
|
||||
regulator-name = "vreg_l7b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l8b_1p8: ldo8 {
|
||||
regulator-name = "vreg_l8b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l9b_2p9: ldo9 {
|
||||
regulator-name = "vreg_l9b_2p9";
|
||||
regulator-min-microvolt = <2960000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l10b_1p8: ldo10 {
|
||||
regulator-name = "vreg_l10b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l11b_1p0: ldo11 {
|
||||
regulator-name = "vreg_l11b_1p0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1292000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l12b_1p8: ldo12 {
|
||||
regulator-name = "vreg_l12b_1p8";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l13b_3p0: ldo13 {
|
||||
regulator-name = "vreg_l13b_3p0";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l14b_3p2: ldo14 {
|
||||
regulator-name = "vreg_l14b_3p2";
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l15b_1p8: ldo15 {
|
||||
regulator-name = "vreg_l15b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l17b_2p5: ldo17 {
|
||||
regulator-name = "vreg_l17b_2p5";
|
||||
regulator-min-microvolt = <2504000>;
|
||||
regulator-max-microvolt = <2504000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l18b_1p2: ldo18 {
|
||||
regulator-name = "vreg_l18b_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-1 {
|
||||
compatible = "qcom,pmh0110-rpmh-regulators";
|
||||
qcom,pmic-id = "D_E0";
|
||||
|
||||
vreg_s10d_1p0: smps10 {
|
||||
regulator-name = "vreg_s10d_1p0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1d_1p2: ldo1 {
|
||||
regulator-name = "vreg_l1d_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1256000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l2d_0p9: ldo2 {
|
||||
regulator-name = "vreg_l2d_0p9";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <958000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l3d_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3d_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l4d_1p2: ldo4 {
|
||||
regulator-name = "vreg_l4d_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-2 {
|
||||
compatible = "qcom,pmh0110-rpmh-regulators";
|
||||
qcom,pmic-id = "F_E0";
|
||||
|
||||
vreg_s6f_0p5: smps6 {
|
||||
regulator-name = "vreg_s6f_0p5";
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <570000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s7f_1p2: smps7 {
|
||||
regulator-name = "vreg_s7f_1p2";
|
||||
regulator-min-microvolt = <1224000>;
|
||||
regulator-max-microvolt = <1372000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s8f_1p8: smps8 {
|
||||
regulator-name = "vreg_s8f_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1f_1p2: ldo1 {
|
||||
regulator-name = "vreg_l1f_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l2f_1p2: ldo2 {
|
||||
regulator-name = "vreg_l2f_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l3f_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3f_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <936000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l4f_0p8: ldo4 {
|
||||
regulator-name = "vreg_l4f_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <912000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-3 {
|
||||
compatible = "qcom,pmh0110-rpmh-regulators";
|
||||
qcom,pmic-id = "G_E0";
|
||||
|
||||
vreg_s7g_0p9: smps7 {
|
||||
regulator-name = "vreg_s7g_0p9";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s9g_1p0: smps9 {
|
||||
regulator-name = "vreg_s9g_1p0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1g_1p2: ldo1 {
|
||||
regulator-name = "vreg_l1g_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l2g_1p8: ldo2 {
|
||||
regulator-name = "vreg_l2g_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l3g_1p2: ldo3 {
|
||||
regulator-name = "vreg_l3g_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l4g_0p9: ldo4 {
|
||||
regulator-name = "vreg_l4g_0p9";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-4 {
|
||||
compatible = "qcom,pmh0110-rpmh-regulators";
|
||||
qcom,pmic-id = "I_E0";
|
||||
|
||||
vreg_s7i_0p9: smps7 {
|
||||
regulator-name = "vreg_s7i_0p9";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <972000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2i_1p2: ldo2 {
|
||||
regulator-name = "vreg_l2i_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l3i_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3i_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-5 {
|
||||
compatible = "qcom,pmh0104-rpmh-regulators";
|
||||
qcom,pmic-id = "J_E1";
|
||||
|
||||
vreg_s1j_0p8: smps1 {
|
||||
regulator-name = "vreg_s1j_0p8";
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s2j_0p8: smps2 {
|
||||
regulator-name = "vreg_s2j_0p8";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s3j_1p2: smps3 {
|
||||
regulator-name = "vreg_s3j_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s4j_0p7: smps4 {
|
||||
regulator-name = "vreg_s4j_0p7";
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-6 {
|
||||
compatible = "qcom,pmr735d-rpmh-regulators";
|
||||
qcom,pmic-id = "K_E1";
|
||||
|
||||
vreg_l1k_0p8: ldo1 {
|
||||
regulator-name = "vreg_l1k_0p8";
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2k_0p7: ldo2 {
|
||||
regulator-name = "vreg_l2k_0p7";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3k_1p2: ldo3 {
|
||||
regulator-name = "vreg_l3k_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l4k_1p0: ldo4 {
|
||||
regulator-name = "vreg_l4k_1p0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5k_0p7: ldo5 {
|
||||
regulator-name = "vreg_l5k_0p7";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6k_1p7: ldo6 {
|
||||
regulator-name = "vreg_l6k_1p7";
|
||||
regulator-min-microvolt = <1700000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7k_0p7: ldo7 {
|
||||
regulator-name = "vreg_l7k_0p7";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <848000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-7 {
|
||||
compatible = "qcom,pm8010-rpmh-regulators";
|
||||
qcom,pmic-id = "M_E1";
|
||||
|
||||
vreg_l1m_1p0: ldo1 {
|
||||
regulator-name = "vreg_l1m_1p0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2m_1p0: ldo2 {
|
||||
regulator-name = "vreg_l2m_1p0";
|
||||
regulator-min-microvolt = <1096000>;
|
||||
regulator-max-microvolt = <1104000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3m_2p8: ldo3 {
|
||||
regulator-name = "vreg_l3m_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l4m_2p2: ldo4 {
|
||||
regulator-name = "vreg_l4m_2p2";
|
||||
regulator-min-microvolt = <2200000>;
|
||||
regulator-max-microvolt = <2200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6m_2p8: ldo6 {
|
||||
regulator-name = "vreg_l6m_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7m_2p8: ldo7 {
|
||||
regulator-name = "vreg_l7m_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-8 {
|
||||
compatible = "qcom,pm8010-rpmh-regulators";
|
||||
qcom,pmic-id = "N_E1";
|
||||
|
||||
vreg_l1n_1p1: ldo1 {
|
||||
regulator-name = "vreg_l1n_1p1";
|
||||
regulator-min-microvolt = <1096000>;
|
||||
regulator-max-microvolt = <1104000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2n_1p2: ldo2 {
|
||||
regulator-name = "vreg_l2n_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3n_1p8: ldo3 {
|
||||
regulator-name = "vreg_l3n_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l4n_1p8: ldo4 {
|
||||
regulator-name = "vreg_l4n_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5n_2p8: ldo5 {
|
||||
regulator-name = "vreg_l5n_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6n_2p8: ldo6 {
|
||||
regulator-name = "vreg_l6n_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7n_3p3: ldo7 {
|
||||
regulator-name = "vreg_l7n_3p3";
|
||||
regulator-min-microvolt = <3304000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-0 = <&pcie0_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0_phy {
|
||||
vdda-phy-supply = <&vreg_l3i_0p8>;
|
||||
vdda-pll-supply = <&vreg_l1d_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_port0 {
|
||||
wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vmmc-supply = <&vreg_l9b_2p9>;
|
||||
vqmmc-supply = <&vreg_l8b_1p8>;
|
||||
|
||||
bus-width = <4>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
|
||||
pinctrl-0 = <&sdc2_default>;
|
||||
pinctrl-1 = <&sdc2_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */
|
||||
<74 1>, /* eSE */
|
||||
<119 2>, /* SoCCP */
|
||||
<144 4>; /* CXM UART */
|
||||
|
||||
pcie0_default_state: pcie0-default-state {
|
||||
perst-n-pins {
|
||||
pins = "gpio102";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
clkreq-n-pins {
|
||||
pins = "gpio103";
|
||||
function = "pcie0_clk_req_n";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio104";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_mem_hc {
|
||||
reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vcc-supply = <&vreg_l17b_2p5>;
|
||||
vcc-max-microamp = <1200000>;
|
||||
vccq-supply = <&vreg_l4d_1p2>;
|
||||
vccq-max-microamp = <1200000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_mem_phy {
|
||||
vdda-phy-supply = <&vreg_l4g_0p9>;
|
||||
vdda-pll-supply = <&vreg_l1d_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
712
arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
Normal file
712
arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
Normal file
|
|
@ -0,0 +1,712 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include "kaanapali.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kaanapali QRD";
|
||||
compatible = "qcom,kaanapali-qrd", "qcom,kaanapali";
|
||||
chassis-type = "handset";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart7;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
clocks {
|
||||
xo_board: xo-board {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <76800000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sleep_clk: sleep-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32764>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
bi_tcxo_div2: bi-tcxo-div2-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK_A>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
regulators-0 {
|
||||
compatible = "qcom,pmh0101-rpmh-regulators";
|
||||
qcom,pmic-id = "B_E0";
|
||||
|
||||
vreg_bob1: bob1 {
|
||||
regulator-name = "vreg_bob1";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <4000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_bob2: bob2 {
|
||||
regulator-name = "vreg_bob2";
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <3552000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1b_1p8: ldo1 {
|
||||
regulator-name = "vreg_l1b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l2b_3p0: ldo2 {
|
||||
regulator-name = "vreg_l2b_3p0";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3048000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l4b_1p8: ldo4 {
|
||||
regulator-name = "vreg_l4b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l5b_3p1: ldo5 {
|
||||
regulator-name = "vreg_l5b_3p1";
|
||||
regulator-min-microvolt = <3100000>;
|
||||
regulator-max-microvolt = <3148000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l6b_1p8: ldo6 {
|
||||
regulator-name = "vreg_l6b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l7b_1p8: ldo7 {
|
||||
regulator-name = "vreg_l7b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l8b_1p8: ldo8 {
|
||||
regulator-name = "vreg_l8b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l9b_2p9: ldo9 {
|
||||
regulator-name = "vreg_l9b_2p9";
|
||||
regulator-min-microvolt = <2960000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l10b_1p8: ldo10 {
|
||||
regulator-name = "vreg_l10b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l11b_1p0: ldo11 {
|
||||
regulator-name = "vreg_l11b_1p0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1292000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l12b_1p8: ldo12 {
|
||||
regulator-name = "vreg_l12b_1p8";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l13b_3p0: ldo13 {
|
||||
regulator-name = "vreg_l13b_3p0";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l14b_3p2: ldo14 {
|
||||
regulator-name = "vreg_l14b_3p2";
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l15b_1p8: ldo15 {
|
||||
regulator-name = "vreg_l15b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l17b_2p5: ldo17 {
|
||||
regulator-name = "vreg_l17b_2p5";
|
||||
regulator-min-microvolt = <2504000>;
|
||||
regulator-max-microvolt = <2504000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l18b_1p2: ldo18 {
|
||||
regulator-name = "vreg_l18b_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-1 {
|
||||
compatible = "qcom,pmh0110-rpmh-regulators";
|
||||
qcom,pmic-id = "D_E0";
|
||||
|
||||
vreg_s10d_1p0: smps10 {
|
||||
regulator-name = "vreg_s10d_1p0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1d_1p2: ldo1 {
|
||||
regulator-name = "vreg_l1d_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1256000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l2d_0p9: ldo2 {
|
||||
regulator-name = "vreg_l2d_0p9";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <958000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l3d_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3d_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l4d_1p2: ldo4 {
|
||||
regulator-name = "vreg_l4d_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-2 {
|
||||
compatible = "qcom,pmh0110-rpmh-regulators";
|
||||
qcom,pmic-id = "F_E0";
|
||||
|
||||
vreg_s6f_0p5: smps6 {
|
||||
regulator-name = "vreg_s6f_0p5";
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <570000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s7f_1p2: smps7 {
|
||||
regulator-name = "vreg_s7f_1p2";
|
||||
regulator-min-microvolt = <1224000>;
|
||||
regulator-max-microvolt = <1372000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s8f_1p8: smps8 {
|
||||
regulator-name = "vreg_s8f_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1f_1p2: ldo1 {
|
||||
regulator-name = "vreg_l1f_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l2f_1p2: ldo2 {
|
||||
regulator-name = "vreg_l2f_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l3f_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3f_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <936000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l4f_0p8: ldo4 {
|
||||
regulator-name = "vreg_l4f_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <912000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-3 {
|
||||
compatible = "qcom,pmh0110-rpmh-regulators";
|
||||
qcom,pmic-id = "G_E0";
|
||||
|
||||
vreg_s7g_0p9: smps7 {
|
||||
regulator-name = "vreg_s7g_0p9";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s9g_1p0: smps9 {
|
||||
regulator-name = "vreg_s9g_1p0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1g_1p2: ldo1 {
|
||||
regulator-name = "vreg_l1g_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l2g_1p8: ldo2 {
|
||||
regulator-name = "vreg_l2g_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l3g_1p2: ldo3 {
|
||||
regulator-name = "vreg_l3g_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l4g_0p9: ldo4 {
|
||||
regulator-name = "vreg_l4g_0p9";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-4 {
|
||||
compatible = "qcom,pmh0110-rpmh-regulators";
|
||||
qcom,pmic-id = "I_E0";
|
||||
|
||||
vreg_s7i_0p9: smps7 {
|
||||
regulator-name = "vreg_s7i_0p9";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <972000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2i_1p2: ldo2 {
|
||||
regulator-name = "vreg_l2i_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l3i_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3i_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-5 {
|
||||
compatible = "qcom,pmh0104-rpmh-regulators";
|
||||
qcom,pmic-id = "J_E1";
|
||||
|
||||
vreg_s1j_0p8: smps1 {
|
||||
regulator-name = "vreg_s1j_0p8";
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s2j_0p8: smps2 {
|
||||
regulator-name = "vreg_s2j_0p8";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s3j_1p2: smps3 {
|
||||
regulator-name = "vreg_s3j_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s4j_0p7: smps4 {
|
||||
regulator-name = "vreg_s4j_0p7";
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-6 {
|
||||
compatible = "qcom,pmr735d-rpmh-regulators";
|
||||
qcom,pmic-id = "K_E1";
|
||||
|
||||
vreg_l1k_0p8: ldo1 {
|
||||
regulator-name = "vreg_l1k_0p8";
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2k_0p7: ldo2 {
|
||||
regulator-name = "vreg_l2k_0p7";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3k_1p2: ldo3 {
|
||||
regulator-name = "vreg_l3k_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l4k_1p0: ldo4 {
|
||||
regulator-name = "vreg_l4k_1p0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5k_0p7: ldo5 {
|
||||
regulator-name = "vreg_l5k_0p7";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6k_1p7: ldo6 {
|
||||
regulator-name = "vreg_l6k_1p7";
|
||||
regulator-min-microvolt = <1700000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7k_0p7: ldo7 {
|
||||
regulator-name = "vreg_l7k_0p7";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <848000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-7 {
|
||||
compatible = "qcom,pm8010-rpmh-regulators";
|
||||
qcom,pmic-id = "M_E1";
|
||||
|
||||
vreg_l1m_1p0: ldo1 {
|
||||
regulator-name = "vreg_l1m_1p0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2m_1p0: ldo2 {
|
||||
regulator-name = "vreg_l2m_1p0";
|
||||
regulator-min-microvolt = <1096000>;
|
||||
regulator-max-microvolt = <1104000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3m_2p8: ldo3 {
|
||||
regulator-name = "vreg_l3m_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l4m_2p2: ldo4 {
|
||||
regulator-name = "vreg_l4m_2p2";
|
||||
regulator-min-microvolt = <2200000>;
|
||||
regulator-max-microvolt = <2200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6m_2p8: ldo6 {
|
||||
regulator-name = "vreg_l6m_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7m_2p8: ldo7 {
|
||||
regulator-name = "vreg_l7m_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-8 {
|
||||
compatible = "qcom,pm8010-rpmh-regulators";
|
||||
qcom,pmic-id = "N_E1";
|
||||
|
||||
vreg_l1n_1p1: ldo1 {
|
||||
regulator-name = "vreg_l1n_1p1";
|
||||
regulator-min-microvolt = <1096000>;
|
||||
regulator-max-microvolt = <1104000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2n_1p2: ldo2 {
|
||||
regulator-name = "vreg_l2n_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3n_1p8: ldo3 {
|
||||
regulator-name = "vreg_l3n_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l4n_1p8: ldo4 {
|
||||
regulator-name = "vreg_l4n_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5n_2p8: ldo5 {
|
||||
regulator-name = "vreg_l5n_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6n_2p8: ldo6 {
|
||||
regulator-name = "vreg_l6n_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7n_3p3: ldo7 {
|
||||
regulator-name = "vreg_l7n_3p3";
|
||||
regulator-min-microvolt = <3304000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vmmc-supply = <&vreg_l9b_2p9>;
|
||||
vqmmc-supply = <&vreg_l8b_1p8>;
|
||||
|
||||
bus-width = <4>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
|
||||
pinctrl-0 = <&sdc2_default>;
|
||||
pinctrl-1 = <&sdc2_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */
|
||||
<74 1>, /* eSE */
|
||||
<119 2>, /* SoCCP */
|
||||
<144 4>; /* CXM UART */
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_mem_hc {
|
||||
reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vcc-supply = <&vreg_l17b_2p5>;
|
||||
vcc-max-microamp = <1200000>;
|
||||
vccq-supply = <&vreg_l4d_1p2>;
|
||||
vccq-max-microamp = <1200000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_mem_phy {
|
||||
vdda-phy-supply = <&vreg_l4g_0p9>;
|
||||
vdda-pll-supply = <&vreg_l1d_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
1606
arch/arm64/boot/dts/qcom/kaanapali.dtsi
Normal file
1606
arch/arm64/boot/dts/qcom/kaanapali.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -190,6 +190,11 @@ rmtfs_mem: rmtfs@9c900000 {
|
|||
qcom,client-id = <1>;
|
||||
qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
|
||||
};
|
||||
|
||||
adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@9cb80000 {
|
||||
reg = <0x0 0x9cb80000 0x0 0x800000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -2424,7 +2429,7 @@ pcie1: pcie@1c08000 {
|
|||
|
||||
status = "disabled";
|
||||
|
||||
pcie@0 {
|
||||
pcie1_port0: pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
|
@ -2994,6 +2999,11 @@ lpass_tlmm: pinctrl@33c0000 {
|
|||
compatible = "qcom,sc7280-lpass-lpi-pinctrl";
|
||||
reg = <0 0x033c0000 0x0 0x20000>,
|
||||
<0 0x03550000 0x0 0x10000>;
|
||||
|
||||
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
|
||||
clock-names = "core", "audio";
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&lpass_tlmm 0 0 15>;
|
||||
|
|
@ -4431,6 +4441,9 @@ fastrpc {
|
|||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
label = "adsp";
|
||||
qcom,non-secure-domain;
|
||||
memory-region = <&adsp_rpc_remote_heap_mem>;
|
||||
qcom,vmids = <QCOM_SCM_VMID_LPASS
|
||||
QCOM_SCM_VMID_ADSP_HEAP>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
|
|
|||
35
arch/arm64/boot/dts/qcom/lemans-el2.dtso
Normal file
35
arch/arm64/boot/dts/qcom/lemans-el2.dtso
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Lemans specific modifications required to boot in EL2.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&iris {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
iommus = <&apps_smmu 0x3000 0x0>;
|
||||
};
|
||||
|
||||
&remoteproc_cdsp0 {
|
||||
iommus = <&apps_smmu 0x21c0 0x0400>;
|
||||
};
|
||||
|
||||
&remoteproc_cdsp1 {
|
||||
iommus = <&apps_smmu 0x29c0 0x0400>;
|
||||
};
|
||||
|
||||
&remoteproc_gpdsp0 {
|
||||
iommus = <&apps_smmu 0x38a0 0x0>;
|
||||
};
|
||||
|
||||
&remoteproc_gpdsp1 {
|
||||
iommus = <&apps_smmu 0x38c0 0x0>;
|
||||
};
|
||||
|
|
@ -38,6 +38,36 @@ chosen {
|
|||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
connector-0 {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB0-Type-C";
|
||||
data-role = "dual";
|
||||
power-role = "dual";
|
||||
|
||||
vbus-supply = <&vbus_supply_regulator_0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
usb0_con_hs_ep: endpoint {
|
||||
remote-endpoint = <&usb_0_dwc3_hs>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
usb0_con_ss_ep: endpoint {
|
||||
remote-endpoint = <&hd3ss3220_in_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
edp0-connector {
|
||||
compatible = "dp-connector";
|
||||
label = "EDP0";
|
||||
|
|
@ -102,6 +132,15 @@ platform {
|
|||
};
|
||||
};
|
||||
|
||||
vbus_supply_regulator_0: regulator-vbus-supply-0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbus_supply_0";
|
||||
gpio = <&expander1 2 GPIO_ACTIVE_HIGH>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vmmc_sdc: regulator-vmmc-sdc {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
|
|
@ -454,6 +493,51 @@ &gpi_dma2 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/sa8775p/a663_zap.mbn";
|
||||
};
|
||||
|
||||
&i2c11 {
|
||||
status = "okay";
|
||||
|
||||
usb-typec@67 {
|
||||
compatible = "ti,hd3ss3220";
|
||||
reg = <0x67>;
|
||||
|
||||
interrupts-extended = <&pmm8654au_2_gpios 5 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
id-gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&usb_id>, <&usb0_intr_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hd3ss3220_in_ep: endpoint {
|
||||
remote-endpoint = <&usb0_con_ss_ep>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hd3ss3220_out_ep: endpoint {
|
||||
remote-endpoint = <&usb_0_dwc3_ss>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c18 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -607,6 +691,16 @@ &pmm8654au_0_pon_resin {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pmm8654au_2_gpios {
|
||||
usb0_intr_state: usb0-intr-state {
|
||||
pins = "gpio5";
|
||||
function = "normal";
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
power-source = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&qup_i2c19_default {
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
|
|
@ -683,6 +777,16 @@ &sleep_clk {
|
|||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&spi16 {
|
||||
status = "okay";
|
||||
|
||||
tpm@0 {
|
||||
compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
ethernet0_default: ethernet0-default-state {
|
||||
ethernet0_mdc: ethernet0-mdc-pins {
|
||||
|
|
@ -746,11 +850,24 @@ wake-pins {
|
|||
};
|
||||
};
|
||||
|
||||
qup_i2c11_default: qup-i2c11-state {
|
||||
pins = "gpio48", "gpio49";
|
||||
function = "qup1_se4";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
sd_cd: sd-cd-state {
|
||||
pins = "gpio36";
|
||||
function = "gpio";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
usb_id: usb-id-state {
|
||||
pins = "gpio50";
|
||||
function = "gpio";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&uart10 {
|
||||
|
|
@ -779,11 +896,17 @@ &ufs_mem_phy {
|
|||
};
|
||||
|
||||
&usb_0 {
|
||||
dr_mode = "peripheral";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_0_dwc3_hs {
|
||||
remote-endpoint = <&usb0_con_hs_ep>;
|
||||
};
|
||||
|
||||
&usb_0_dwc3_ss {
|
||||
remote-endpoint = <&hd3ss3220_out_ep>;
|
||||
};
|
||||
|
||||
&usb_0_hsphy {
|
||||
vdda-pll-supply = <&vreg_l7a>;
|
||||
vdda18-supply = <&vreg_l6c>;
|
||||
|
|
|
|||
|
|
@ -436,6 +436,14 @@ vreg_l8e: ldo8 {
|
|||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/sa8775p/a663_zap.mbn";
|
||||
};
|
||||
|
||||
&i2c11 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/soc/qcom,gpr.h>
|
||||
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&intc>;
|
||||
|
|
@ -54,6 +55,7 @@ cpu0: cpu@0 {
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
next-level-cache = <&l2_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
dynamic-power-coefficient = <100>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
|
|
@ -83,6 +85,7 @@ cpu1: cpu@100 {
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
next-level-cache = <&l2_1>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
dynamic-power-coefficient = <100>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
|
|
@ -107,6 +110,7 @@ cpu2: cpu@200 {
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
next-level-cache = <&l2_2>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
dynamic-power-coefficient = <100>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
|
|
@ -131,6 +135,7 @@ cpu3: cpu@300 {
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
next-level-cache = <&l2_3>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
dynamic-power-coefficient = <100>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
|
|
@ -155,6 +160,7 @@ cpu4: cpu@10000 {
|
|||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
next-level-cache = <&l2_4>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
dynamic-power-coefficient = <100>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
|
|
@ -185,6 +191,7 @@ cpu5: cpu@10100 {
|
|||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
next-level-cache = <&l2_5>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
dynamic-power-coefficient = <100>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
|
|
@ -209,6 +216,7 @@ cpu6: cpu@10200 {
|
|||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
next-level-cache = <&l2_6>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
dynamic-power-coefficient = <100>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
|
|
@ -233,6 +241,7 @@ cpu7: cpu@10300 {
|
|||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
next-level-cache = <&l2_7>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
dynamic-power-coefficient = <100>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
|
|
@ -518,90 +527,18 @@ scm {
|
|||
};
|
||||
};
|
||||
|
||||
aggre1_noc: interconnect-aggre1-noc {
|
||||
compatible = "qcom,sa8775p-aggre1-noc";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
aggre2_noc: interconnect-aggre2-noc {
|
||||
compatible = "qcom,sa8775p-aggre2-noc";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
clk_virt: interconnect-clk-virt {
|
||||
compatible = "qcom,sa8775p-clk-virt";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
config_noc: interconnect-config-noc {
|
||||
compatible = "qcom,sa8775p-config-noc";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
dc_noc: interconnect-dc-noc {
|
||||
compatible = "qcom,sa8775p-dc-noc";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
gem_noc: interconnect-gem-noc {
|
||||
compatible = "qcom,sa8775p-gem-noc";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
gpdsp_anoc: interconnect-gpdsp-anoc {
|
||||
compatible = "qcom,sa8775p-gpdsp-anoc";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
lpass_ag_noc: interconnect-lpass-ag-noc {
|
||||
compatible = "qcom,sa8775p-lpass-ag-noc";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
mc_virt: interconnect-mc-virt {
|
||||
compatible = "qcom,sa8775p-mc-virt";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
mmss_noc: interconnect-mmss-noc {
|
||||
compatible = "qcom,sa8775p-mmss-noc";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
nspa_noc: interconnect-nspa-noc {
|
||||
compatible = "qcom,sa8775p-nspa-noc";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
nspb_noc: interconnect-nspb-noc {
|
||||
compatible = "qcom,sa8775p-nspb-noc";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
pcie_anoc: interconnect-pcie-anoc {
|
||||
compatible = "qcom,sa8775p-pcie-anoc";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
system_noc: interconnect-system-noc {
|
||||
compatible = "qcom,sa8775p-system-noc";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
/* Will be updated by the bootloader. */
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
|
|
@ -1098,6 +1035,18 @@ ipcc: mailbox@408000 {
|
|||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
qfprom: efuse@784000 {
|
||||
compatible = "qcom,sa8775p-qfprom", "qcom,qfprom";
|
||||
reg = <0x0 0x00784000 0x0 0x3000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
gpu_speed_bin: gpu_speed_bin@240c {
|
||||
reg = <0x240c 0x1>;
|
||||
bits = <0 8>;
|
||||
};
|
||||
};
|
||||
|
||||
gpi_dma2: dma-controller@800000 {
|
||||
compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
|
||||
reg = <0x0 0x00800000 0x0 0x60000>;
|
||||
|
|
@ -2689,6 +2638,62 @@ rng: rng@10d2000 {
|
|||
reg = <0 0x010d2000 0 0x1000>;
|
||||
};
|
||||
|
||||
config_noc: interconnect@14c0000 {
|
||||
compatible = "qcom,sa8775p-config-noc";
|
||||
reg = <0x0 0x014c0000 0x0 0x13080>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
system_noc: interconnect@1680000 {
|
||||
compatible = "qcom,sa8775p-system-noc";
|
||||
reg = <0x0 0x01680000 0x0 0x15080>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
aggre1_noc: interconnect@16c0000 {
|
||||
compatible = "qcom,sa8775p-aggre1-noc";
|
||||
reg = <0x0 0x016c0000 0x0 0x18080>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
|
||||
};
|
||||
|
||||
aggre2_noc: interconnect@1700000 {
|
||||
compatible = "qcom,sa8775p-aggre2-noc";
|
||||
reg = <0x0 0x01700000 0x0 0x1b080>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
|
||||
<&rpmhcc RPMH_IPA_CLK>;
|
||||
};
|
||||
|
||||
pcie_anoc: interconnect@1760000 {
|
||||
compatible = "qcom,sa8775p-pcie-anoc";
|
||||
reg = <0x0 0x01760000 0x0 0xc080>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
gpdsp_anoc: interconnect@1780000 {
|
||||
compatible = "qcom,sa8775p-gpdsp-anoc";
|
||||
reg = <0x0 0x01780000 0x0 0xe080>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
mmss_noc: interconnect@17a0000 {
|
||||
compatible = "qcom,sa8775p-mmss-noc";
|
||||
reg = <0x0 0x017a0000 0x0 0x40000>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
ufs_mem_hc: ufshc@1d84000 {
|
||||
compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
|
||||
reg = <0x0 0x01d84000 0x0 0x3000>;
|
||||
|
|
@ -2769,6 +2774,25 @@ cryptobam: dma-controller@1dc4000 {
|
|||
<&apps_smmu 0x481 0x00>;
|
||||
};
|
||||
|
||||
crypto: crypto@1dfa000 {
|
||||
compatible = "qcom,sa8775p-qce", "qcom,sm8150-qce", "qcom,qce";
|
||||
reg = <0x0 0x01dfa000 0x0 0x6000>;
|
||||
dmas = <&cryptobam 4>, <&cryptobam 5>;
|
||||
dma-names = "rx", "tx";
|
||||
iommus = <&apps_smmu 0x480 0x0>,
|
||||
<&apps_smmu 0x481 0x0>;
|
||||
interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "memory";
|
||||
};
|
||||
|
||||
lpass_ag_noc: interconnect@3c40000 {
|
||||
compatible = "qcom,sa8775p-lpass-ag-noc";
|
||||
reg = <0x0 0x03c40000 0x0 0x17200>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
ctcu@4001000 {
|
||||
compatible = "qcom,sa8775p-ctcu";
|
||||
reg = <0x0 0x04001000 0x0 0x1000>;
|
||||
|
|
@ -2961,6 +2985,14 @@ funnel1_in4: endpoint {
|
|||
<&apss_funnel1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
|
||||
funnel1_in5: endpoint {
|
||||
remote-endpoint = <&dlct0_funnel_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -3118,6 +3150,60 @@ etr1_out: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
tpda@4ad3000 {
|
||||
compatible = "qcom,coresight-tpda", "arm,primecell";
|
||||
reg = <0x0 0x4ad3000 0x0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@10 {
|
||||
reg = <16>;
|
||||
dlct0_tpda_in16: endpoint {
|
||||
remote-endpoint = <&turing0_funnel_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
dlct0_tpda_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&dlct0_funnel_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
funnel@4ad4000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0x0 0x4ad4000 0x0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
dlct0_funnel_in0: endpoint {
|
||||
remote-endpoint = <&dlct0_tpda_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
dlct0_funnel_out: endpoint {
|
||||
remote-endpoint = <&funnel1_in5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@4b04000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0x0 0x4b04000 0x0 0x1000>;
|
||||
|
|
@ -3390,6 +3476,35 @@ aoss_cti: cti@4b13000 {
|
|||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
funnel@4b83000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0x0 0x4b83000 0x0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
turing0_funnel_in1: endpoint {
|
||||
remote-endpoint = <&turing_llm_tpdm_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
turing0_funnel_out: endpoint {
|
||||
remote-endpoint = <&dlct0_tpda_in16>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@6040000 {
|
||||
compatible = "arm,primecell";
|
||||
reg = <0x0 0x6040000 0x0 0x1000>;
|
||||
|
|
@ -3981,6 +4096,20 @@ refgen: regulator@891c000 {
|
|||
reg = <0x0 0x0891c000 0x0 0x84>;
|
||||
};
|
||||
|
||||
dc_noc: interconnect@90e0000 {
|
||||
compatible = "qcom,sa8775p-dc-noc";
|
||||
reg = <0x0 0x090e0000 0x0 0x5080>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
gem_noc: interconnect@9100000 {
|
||||
compatible = "qcom,sa8775p-gem-noc";
|
||||
reg = <0x0 0x09100000 0x0 0xf6080>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
usb_0: usb@a600000 {
|
||||
compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3";
|
||||
reg = <0 0x0a600000 0 0xfc100>;
|
||||
|
|
@ -4026,7 +4155,27 @@ usb_0: usb@a600000 {
|
|||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
|
||||
usb-role-switch;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
usb_0_dwc3_hs: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
usb_0_dwc3_ss: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb_1: usb@a800000 {
|
||||
|
|
@ -4135,6 +4284,113 @@ tcsr: syscon@1fc0000 {
|
|||
reg = <0x0 0x1fc0000 0x0 0x30000>;
|
||||
};
|
||||
|
||||
gpu: gpu@3d00000 {
|
||||
compatible = "qcom,adreno-663.0", "qcom,adreno";
|
||||
reg = <0x0 0x03d00000 0x0 0x40000>,
|
||||
<0x0 0x03d9e000 0x0 0x1000>,
|
||||
<0x0 0x03d61000 0x0 0x800>;
|
||||
reg-names = "kgsl_3d0_reg_memory",
|
||||
"cx_mem",
|
||||
"cx_dbgc";
|
||||
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&adreno_smmu 0 0xc00>,
|
||||
<&adreno_smmu 1 0xc00>;
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
qcom,gmu = <&gmu>;
|
||||
interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "gfx-mem";
|
||||
#cooling-cells = <2>;
|
||||
|
||||
nvmem-cells = <&gpu_speed_bin>;
|
||||
nvmem-cell-names = "speed_bin";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
gpu_zap_shader: zap-shader {
|
||||
memory-region = <&pil_gpu_mem>;
|
||||
};
|
||||
|
||||
gpu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-405000000 {
|
||||
opp-hz = /bits/ 64 <405000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
opp-peak-kBps = <5285156>;
|
||||
opp-supported-hw = <0x3>;
|
||||
};
|
||||
|
||||
opp-530000000 {
|
||||
opp-hz = /bits/ 64 <530000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
opp-peak-kBps = <12484375>;
|
||||
opp-supported-hw = <0x2>;
|
||||
};
|
||||
|
||||
opp-676000000 {
|
||||
opp-hz = /bits/ 64 <676000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
opp-peak-kBps = <8171875>;
|
||||
opp-supported-hw = <0x1>;
|
||||
};
|
||||
|
||||
opp-778000000 {
|
||||
opp-hz = /bits/ 64 <778000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
opp-peak-kBps = <10687500>;
|
||||
opp-supported-hw = <0x1>;
|
||||
};
|
||||
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
opp-peak-kBps = <12484375>;
|
||||
opp-supported-hw = <0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmu: gmu@3d6a000 {
|
||||
compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu";
|
||||
reg = <0x0 0x03d6a000 0x0 0x34000>,
|
||||
<0x0 0x03de0000 0x0 0x10000>,
|
||||
<0x0 0x0b290000 0x0 0x10000>;
|
||||
reg-names = "gmu", "rscc", "gmu_pdc";
|
||||
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hfi", "gmu";
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
|
||||
clock-names = "gmu",
|
||||
"cxo",
|
||||
"axi",
|
||||
"memnoc",
|
||||
"ahb",
|
||||
"hub",
|
||||
"smmu_vote";
|
||||
power-domains = <&gpucc GPU_CC_CX_GDSC>,
|
||||
<&gpucc GPU_CC_GX_GDSC>;
|
||||
power-domain-names = "cx",
|
||||
"gx";
|
||||
iommus = <&adreno_smmu 5 0xc00>;
|
||||
operating-points-v2 = <&gmu_opp_table>;
|
||||
|
||||
gmu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpucc: clock-controller@3d90000 {
|
||||
compatible = "qcom,sa8775p-gpucc";
|
||||
reg = <0x0 0x03d90000 0x0 0xa000>;
|
||||
|
|
@ -4928,7 +5184,7 @@ mdss0_dsi0_in: endpoint {
|
|||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mdss0_dsi0_out: endpoint{ };
|
||||
mdss0_dsi0_out: endpoint { };
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -6888,6 +7144,13 @@ &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>,
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
nspa_noc: interconnect@260c0000 {
|
||||
compatible = "qcom,sa8775p-nspa-noc";
|
||||
reg = <0x0 0x260c0000 0x0 0x16080>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
remoteproc_cdsp0: remoteproc@26300000 {
|
||||
compatible = "qcom,sa8775p-cdsp0-pas";
|
||||
reg = <0x0 0x26300000 0x0 0x10000>;
|
||||
|
|
@ -7020,9 +7283,16 @@ compute-cb@11 {
|
|||
};
|
||||
};
|
||||
|
||||
nspb_noc: interconnect@2a0c0000 {
|
||||
compatible = "qcom,sa8775p-nspb-noc";
|
||||
reg = <0x0 0x2a0c0000 0x0 0x16080>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
remoteproc_cdsp1: remoteproc@2a300000 {
|
||||
compatible = "qcom,sa8775p-cdsp1-pas";
|
||||
reg = <0x0 0x2A300000 0x0 0x10000>;
|
||||
reg = <0x0 0x2a300000 0x0 0x10000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
|
||||
<&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
|
|
@ -7395,8 +7665,15 @@ gpuss-0-thermal {
|
|||
|
||||
thermal-sensors = <&tsens0 5>;
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&gpuss0_alert0>;
|
||||
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
|
||||
trips {
|
||||
trip-point0 {
|
||||
gpuss0_alert0: trip-point0 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <5000>;
|
||||
type = "passive";
|
||||
|
|
@ -7415,8 +7692,15 @@ gpuss-1-thermal {
|
|||
|
||||
thermal-sensors = <&tsens0 6>;
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&gpuss1_alert0>;
|
||||
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
|
||||
trips {
|
||||
trip-point0 {
|
||||
gpuss1_alert0: trip-point0 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <5000>;
|
||||
type = "passive";
|
||||
|
|
@ -7435,8 +7719,15 @@ gpuss-2-thermal {
|
|||
|
||||
thermal-sensors = <&tsens0 7>;
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&gpuss2_alert0>;
|
||||
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
|
||||
trips {
|
||||
trip-point0 {
|
||||
gpuss2_alert0: trip-point0 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <5000>;
|
||||
type = "passive";
|
||||
|
|
@ -7625,8 +7916,15 @@ gpuss-3-thermal {
|
|||
|
||||
thermal-sensors = <&tsens1 5>;
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&gpuss3_alert0>;
|
||||
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
|
||||
trips {
|
||||
trip-point0 {
|
||||
gpuss3_alert0: trip-point0 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <5000>;
|
||||
type = "passive";
|
||||
|
|
@ -7645,8 +7943,15 @@ gpuss-4-thermal {
|
|||
|
||||
thermal-sensors = <&tsens1 6>;
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&gpuss4_alert0>;
|
||||
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
|
||||
trips {
|
||||
trip-point0 {
|
||||
gpuss4_alert0: trip-point0 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <5000>;
|
||||
type = "passive";
|
||||
|
|
@ -7665,8 +7970,15 @@ gpuss-5-thermal {
|
|||
|
||||
thermal-sensors = <&tsens1 7>;
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&gpuss5_alert0>;
|
||||
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
|
||||
trips {
|
||||
trip-point0 {
|
||||
gpuss5_alert0: trip-point0 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <5000>;
|
||||
type = "passive";
|
||||
|
|
@ -8269,6 +8581,20 @@ arch_timer: timer {
|
|||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
turing-llm-tpdm {
|
||||
compatible = "qcom,coresight-static-tpdm";
|
||||
|
||||
qcom,cmb-element-bits = <32>;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
turing_llm_tpdm_out: endpoint {
|
||||
remote-endpoint = <&turing0_funnel_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie0: pcie@1c00000 {
|
||||
compatible = "qcom,pcie-sa8775p";
|
||||
reg = <0x0 0x01c00000 0x0 0x3000>,
|
||||
|
|
|
|||
790
arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
Normal file
790
arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
Normal file
|
|
@ -0,0 +1,790 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#define PMIV0104_SID 7
|
||||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include "milos.dtsi"
|
||||
#include "pm7550.dtsi"
|
||||
#include "pm8550vs.dtsi"
|
||||
#include "pmiv0104.dtsi" /* PMIV0108 */
|
||||
#include "pmk8550.dtsi" /* PMK7635 */
|
||||
#include "pmr735b.dtsi"
|
||||
|
||||
/ {
|
||||
model = "The Fairphone (Gen. 6)";
|
||||
compatible = "fairphone,fp6", "qcom,milos";
|
||||
chassis-type = "handset";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart5;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&volume_up_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
key-volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&pm7550_gpios 6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
|
||||
switch {
|
||||
label = "Switch";
|
||||
gpios = <&tlmm 107 GPIO_ACTIVE_HIGH>;
|
||||
linux,input-type = <EV_SW>;
|
||||
linux,code = <SW_MUTE_DEVICE>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic-glink {
|
||||
compatible = "qcom,milos-pmic-glink",
|
||||
"qcom,sm8550-pmic-glink",
|
||||
"qcom,pmic-glink";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
orientation-gpios = <&tlmm 131 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
connector@0 {
|
||||
compatible = "usb-c-connector";
|
||||
reg = <0>;
|
||||
|
||||
power-role = "dual";
|
||||
data-role = "dual";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
pmic_glink_hs_in: endpoint {
|
||||
remote-endpoint = <&usb_1_dwc3_hs>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vreg_ff_afvdd_2p8: regulator-ff-afvdd-2p8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "ff_afvdd_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
startup-delay-us = <100>;
|
||||
|
||||
gpio = <&tlmm 93 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
vin-supply = <&vreg_bob>;
|
||||
};
|
||||
|
||||
vreg_uw_afvdd_2p8: regulator-uw-afvdd-2p8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "uw_afvdd_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
startup-delay-us = <100>;
|
||||
|
||||
gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
vin-supply = <&vreg_bob>;
|
||||
};
|
||||
|
||||
vreg_uw_dvdd: regulator-uw-dvdd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "uw_dvdd";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
startup-delay-us = <100>;
|
||||
|
||||
gpio = <&tlmm 28 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
vin-supply = <&vreg_s1b>;
|
||||
};
|
||||
|
||||
vreg_ois_avdd0_1p8: regulator-ois-avdd0-1p8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "ois_avdd0_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
startup-delay-us = <100>;
|
||||
|
||||
gpio = <&tlmm 27 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
vin-supply = <&vreg_bob>;
|
||||
};
|
||||
|
||||
vreg_ois_vdd: regulator-ois-vdd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "ois_vdd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <100>;
|
||||
|
||||
gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
vin-supply = <&vph_pwr>;
|
||||
};
|
||||
|
||||
vreg_oled_dvdd_1p2: regulator-oled-dvdd-1p2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "oled_dvdd_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
|
||||
gpio = <&tlmm 54 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
vin-supply = <&vreg_s2b>;
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_s1j: regulator-pm3001a-s1j {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pm3001a_s1j";
|
||||
regulator-min-microvolt = <2200000>;
|
||||
regulator-max-microvolt = <2200000>;
|
||||
startup-delay-us = <1000>;
|
||||
|
||||
gpio = <&pmr735b_gpios 1 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
vin-supply = <&vph_pwr>;
|
||||
|
||||
pinctrl-0 = <&s1j_enable_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
vreg_vtof_ldo_3p3: regulator-vtof-ldo-3p3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vtof_ldo_3p3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <100>;
|
||||
|
||||
gpio = <&tlmm 76 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
vin-supply = <&vph_pwr>;
|
||||
};
|
||||
|
||||
vph_pwr: regulator-vph-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
pm8008-thermal {
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&pm8008>;
|
||||
|
||||
trips {
|
||||
trip0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
trip1 {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
regulators-0 {
|
||||
compatible = "qcom,pm7550-rpmh-regulators";
|
||||
|
||||
vdd-l1-supply = <&vreg_s1b>;
|
||||
vdd-l2-l3-supply = <&vreg_s3b>;
|
||||
vdd-l4-l5-supply = <&vreg_s2b>;
|
||||
vdd-l6-supply = <&vreg_s2b>;
|
||||
vdd-l7-supply = <&vreg_s1b>;
|
||||
vdd-l8-supply = <&vreg_s1b>;
|
||||
vdd-l9-l10-supply = <&vreg_s1b>;
|
||||
vdd-l11-supply = <&vreg_s1b>;
|
||||
vdd-l12-l14-supply = <&vreg_bob>;
|
||||
vdd-l13-l16-supply = <&vreg_bob>;
|
||||
vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply = <&vreg_bob>;
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
|
||||
qcom,pmic-id = "b";
|
||||
|
||||
vreg_s1b: smps1 {
|
||||
regulator-name = "vreg_s1b";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2080000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s2b: smps2 {
|
||||
regulator-name = "vreg_s2b";
|
||||
regulator-min-microvolt = <1256000>;
|
||||
regulator-max-microvolt = <1408000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s3b: smps3 {
|
||||
regulator-name = "vreg_s3b";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <1040000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2b: ldo2 {
|
||||
regulator-name = "vreg_l2b";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <912000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3b: ldo3 {
|
||||
regulator-name = "vreg_l3b";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <912000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l4b: ldo4 {
|
||||
regulator-name = "vreg_l4b";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5b: ldo5 {
|
||||
regulator-name = "vreg_l5b";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7b: ldo7 {
|
||||
regulator-name = "vreg_l7b";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l8b: ldo8 {
|
||||
regulator-name = "vreg_l8b";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l9b: ldo9 {
|
||||
regulator-name = "vreg_l9b";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l10b: ldo10 {
|
||||
regulator-name = "vreg_l10b";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l11b: ldo11 {
|
||||
regulator-name = "vreg_l11b";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l12b: ldo12 {
|
||||
regulator-name = "vreg_l12b";
|
||||
/*
|
||||
* Skip voltage voting for UFS VCC.
|
||||
*/
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l13b: ldo13 {
|
||||
regulator-name = "vreg_l13b";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l14b: ldo14 {
|
||||
regulator-name = "vreg_l14b";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l15b: ldo15 {
|
||||
regulator-name = "vreg_l15b";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l16b: ldo16 {
|
||||
regulator-name = "vreg_l16b";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l17b: ldo17 {
|
||||
regulator-name = "vreg_l17b";
|
||||
regulator-min-microvolt = <3104000>;
|
||||
regulator-max-microvolt = <3104000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l18b: ldo18 {
|
||||
regulator-name = "vreg_l18b";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l19b: ldo19 {
|
||||
regulator-name = "vreg_l19b";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l20b: ldo20 {
|
||||
regulator-name = "vreg_l20b";
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l21b: ldo21 {
|
||||
regulator-name = "vreg_l21b";
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l22b: ldo22 {
|
||||
regulator-name = "vreg_l22b";
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l23b: ldo23 {
|
||||
regulator-name = "vreg_l23b";
|
||||
regulator-min-microvolt = <1650000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_bob: bob {
|
||||
regulator-name = "vreg_bob";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-1 {
|
||||
compatible = "qcom,pm8550vs-rpmh-regulators";
|
||||
|
||||
vdd-l1-supply = <&vreg_s3b>;
|
||||
vdd-l3-supply = <&vreg_s3b>;
|
||||
|
||||
qcom,pmic-id = "c";
|
||||
|
||||
vreg_l2c: ldo2 {
|
||||
regulator-name = "vreg_l2c";
|
||||
regulator-min-microvolt = <320000>;
|
||||
regulator-max-microvolt = <650000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-2 {
|
||||
compatible = "qcom,pmr735b-rpmh-regulators";
|
||||
|
||||
vdd-l1-l2-supply= <&vreg_s3b>;
|
||||
vdd-l3-supply= <&vreg_s3b>;
|
||||
vdd-l4-supply= <&vreg_s1b>;
|
||||
vdd-l5-supply= <&vreg_s2b>;
|
||||
vdd-l6-supply= <&vreg_s2b>;
|
||||
vdd-l7-l8-supply= <&vreg_s2b>;
|
||||
vdd-l9-supply= <&vreg_s3b>;
|
||||
vdd-l10-supply= <&vreg_s1b>;
|
||||
vdd-l11-supply= <&vreg_s3b>;
|
||||
vdd-l12-supply= <&vreg_s3b>;
|
||||
|
||||
qcom,pmic-id = "f";
|
||||
|
||||
vreg_l1f: ldo1 {
|
||||
regulator-name = "vreg_l1f";
|
||||
regulator-min-microvolt = <852000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2f: ldo2 {
|
||||
regulator-name = "vreg_l2f";
|
||||
regulator-min-microvolt = <751000>;
|
||||
regulator-max-microvolt = <824000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3f: ldo3 {
|
||||
regulator-name = "vreg_l3f";
|
||||
regulator-min-microvolt = <650000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l4f: ldo4 {
|
||||
regulator-name = "vreg_l4f";
|
||||
regulator-min-microvolt = <1700000>;
|
||||
regulator-max-microvolt = <1950000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5f: ldo5 {
|
||||
regulator-name = "vreg_l5f";
|
||||
regulator-min-microvolt = <1140000>;
|
||||
regulator-max-microvolt = <1260000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6f: ldo6 {
|
||||
regulator-name = "vreg_l6f";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7f: ldo7 {
|
||||
regulator-name = "vreg_l7f";
|
||||
regulator-min-microvolt = <1080000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l8f: ldo8 {
|
||||
regulator-name = "vreg_l8f";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1320000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l9f: ldo9 {
|
||||
regulator-name = "vreg_l9f";
|
||||
regulator-min-microvolt = <870000>;
|
||||
regulator-max-microvolt = <970000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l10f: ldo10 {
|
||||
regulator-name = "vreg_l10f";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l11f: ldo11 {
|
||||
regulator-name = "vreg_l11f";
|
||||
regulator-min-microvolt = <320000>;
|
||||
regulator-max-microvolt = <864000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_PCIE_1_AUX_CLK>, <GCC_PCIE_1_AUX_CLK_SRC>,
|
||||
<GCC_PCIE_1_CFG_AHB_CLK>, <GCC_PCIE_1_MSTR_AXI_CLK>,
|
||||
<GCC_PCIE_1_PHY_RCHNG_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>,
|
||||
<GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>,
|
||||
<GCC_PCIE_1_PIPE_DIV2_CLK>, <GCC_PCIE_1_PIPE_DIV2_CLK_SRC>,
|
||||
<GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
/* Samsung NFC @ 0x27 */
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
/* AW88261FCR amplifier (top) @ 0x34 */
|
||||
/* AW88261FCR amplifier (bottom) @ 0x35 */
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
|
||||
pm8008: pmic@8 {
|
||||
compatible = "qcom,pm8008";
|
||||
reg = <0x8>;
|
||||
|
||||
interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_RISING>;
|
||||
reset-gpios = <&pmr735b_gpios 3 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vdd-l1-l2-supply = <&vreg_s2b>;
|
||||
vdd-l3-l4-supply = <&vreg_bob>;
|
||||
vdd-l5-supply = <&vreg_bob>;
|
||||
vdd-l6-supply = <&vreg_s1b>;
|
||||
vdd-l7-supply = <&vreg_bob>;
|
||||
|
||||
pinctrl-0 = <&pm8008_int_default>, <&pm8008_reset_n_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pm8008 0 0 2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
#thermal-sensor-cells = <0>;
|
||||
|
||||
regulators {
|
||||
vreg_l1p: ldo1 {
|
||||
regulator-name = "vreg_l1p";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
vreg_l2p: ldo2 {
|
||||
regulator-name = "vreg_l2p";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1144000>;
|
||||
};
|
||||
|
||||
vreg_l3p: ldo3 {
|
||||
regulator-name = "vreg_l3p";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
vreg_l4p: ldo4 {
|
||||
regulator-name = "vreg_l4p";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
};
|
||||
|
||||
vreg_l5p: ldo5 {
|
||||
regulator-name = "vreg_l5p";
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
};
|
||||
|
||||
vreg_l6p: ldo6 {
|
||||
regulator-name = "vreg_l6p";
|
||||
regulator-min-microvolt = <1700000>;
|
||||
regulator-max-microvolt = <1896000>;
|
||||
};
|
||||
|
||||
vreg_l7p: ldo7 {
|
||||
regulator-name = "vreg_l7p";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* VL53L3 ToF @ 0x29 */
|
||||
/* AW86938FCR vibrator @ 0x5a */
|
||||
};
|
||||
|
||||
&pm8550vs_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmiv0104_eusb2_repeater {
|
||||
vdd18-supply = <&vreg_l7b>;
|
||||
vdd3-supply = <&vreg_l17b>;
|
||||
|
||||
qcom,tune-res-fsdif = /bits/ 8 <0x5>;
|
||||
qcom,tune-usb2-amplitude = /bits/ 8 <0x8>;
|
||||
qcom,tune-usb2-disc-thres = /bits/ 8 <0x7>;
|
||||
qcom,tune-usb2-preem = /bits/ 8 <0x6>;
|
||||
};
|
||||
|
||||
&pmr735b_gpios {
|
||||
s1j_enable_default: s1j-enable-default-state {
|
||||
pins = "gpio1";
|
||||
function = PMIC_GPIO_FUNC_NORMAL;
|
||||
power-source = <0>;
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
|
||||
pm8008_reset_n_default: pm8008-reset-n-default-state {
|
||||
pins = "gpio3";
|
||||
function = PMIC_GPIO_FUNC_NORMAL;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
&pm7550_gpios {
|
||||
volume_up_default: volume-up-default-state {
|
||||
pins = "gpio6";
|
||||
function = PMIC_GPIO_FUNC_NORMAL;
|
||||
power-source = <1>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&pm7550_flash {
|
||||
status = "okay";
|
||||
|
||||
led-0 {
|
||||
function = LED_FUNCTION_FLASH;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
led-sources = <1>, <4>;
|
||||
led-max-microamp = <350000>;
|
||||
flash-max-microamp = <1500000>;
|
||||
flash-max-timeout-us = <400000>;
|
||||
};
|
||||
};
|
||||
|
||||
&pon_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_resin {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/milos/fairphone/fp6/adsp.mbn",
|
||||
"qcom/milos/fairphone/fp6/adsp_dtb.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp {
|
||||
firmware-name = "qcom/milos/fairphone/fp6/cdsp.mbn",
|
||||
"qcom/milos/fairphone/fp6/cdsp_dtb.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_mpss {
|
||||
firmware-name = "qcom/milos/fairphone/fp6/modem.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_wpss {
|
||||
firmware-name = "qcom/milos/fairphone/fp6/wpss.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
cd-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
vmmc-supply = <&vreg_l13b>;
|
||||
vqmmc-supply = <&vreg_l23b>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
|
||||
pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>;
|
||||
pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
/* Eswin EPH8621 touchscreen @ 0 */
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <8 4>, /* Fingerprint SPI */
|
||||
<13 1>, /* NC */
|
||||
<63 2>; /* WLAN UART */
|
||||
|
||||
sdc2_card_det_n: sdc2-card-det-state {
|
||||
pins = "gpio65";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pm8008_int_default: pm8008-int-default-state {
|
||||
pins = "gpio125";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
dr_mode = "otg";
|
||||
|
||||
/* USB 2.0 only, HW does not support USB 3.x */
|
||||
qcom,select-utmi-as-pipe-clk;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_dwc3_hs {
|
||||
remote-endpoint = <&pmic_glink_hs_in>;
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
vdd-supply = <&vreg_l2b>;
|
||||
vdda12-supply = <&vreg_l4b>;
|
||||
|
||||
phys = <&pmiv0104_eusb2_repeater>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
2633
arch/arm64/boot/dts/qcom/milos.dtsi
Normal file
2633
arch/arm64/boot/dts/qcom/milos.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -6,6 +6,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <dt-bindings/sound/qcom,q6afe.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
|
||||
|
|
@ -323,6 +324,16 @@ &i2c1 {
|
|||
|
||||
status = "okay";
|
||||
|
||||
fan_controller: fan@18 {
|
||||
compatible = "ti,amc6821";
|
||||
reg = <0x18>;
|
||||
#pwm-cells = <2>;
|
||||
|
||||
fan {
|
||||
pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom0: eeprom@50 {
|
||||
compatible = "atmel,24c256";
|
||||
reg = <0x50>;
|
||||
|
|
@ -400,6 +411,44 @@ &iris {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-0 = <&pcie0_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0_phy {
|
||||
vdda-phy-supply = <&vreg_l6a>;
|
||||
vdda-pll-supply = <&vreg_l5a>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
pinctrl-0 = <&pcie1_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1_phy {
|
||||
vdda-phy-supply = <&vreg_l6a>;
|
||||
vdda-pll-supply = <&vreg_l5a>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcieport0 {
|
||||
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&pcieport1 {
|
||||
reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
firmware-name = "qcom/qcs8300/qupv3fw.elf";
|
||||
status = "okay";
|
||||
|
|
@ -434,7 +483,41 @@ &serdes0 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&spi10 {
|
||||
status = "okay";
|
||||
|
||||
tpm@0 {
|
||||
compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
|
||||
pcie0_default_state: pcie0-default-state {
|
||||
wake-pins {
|
||||
pins = "gpio0";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
clkreq-pins {
|
||||
pins = "gpio1";
|
||||
function = "pcie0_clkreq";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-pins {
|
||||
pins = "gpio2";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet0_default: ethernet0-default-state {
|
||||
ethernet0_mdc: ethernet0-mdc-pins {
|
||||
pins = "gpio5";
|
||||
|
|
@ -458,6 +541,29 @@ qup_i2c1_default: qup-i2c1-state {
|
|||
bias-pull-up;
|
||||
};
|
||||
|
||||
pcie1_default_state: pcie1-default-state {
|
||||
wake-pins {
|
||||
pins = "gpio21";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
clkreq-pins {
|
||||
pins = "gpio22";
|
||||
function = "pcie1_clkreq";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-pins {
|
||||
pins = "gpio23";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c15_default: qup-i2c15-state {
|
||||
pins = "gpio91", "gpio92";
|
||||
function = "qup1_se7";
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -996,7 +996,7 @@ mdss: display-subsystem@1a00000 {
|
|||
clock-names = "iface",
|
||||
"bus",
|
||||
"vsync";
|
||||
|
||||
resets = <&gcc GCC_MDSS_BCR>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
interrupt-controller;
|
||||
|
|
|
|||
|
|
@ -1044,6 +1044,7 @@ mdss: display-subsystem@1a00000 {
|
|||
clock-names = "iface",
|
||||
"bus",
|
||||
"vsync";
|
||||
resets = <&gcc GCC_MDSS_BCR>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
interrupt-controller;
|
||||
|
|
|
|||
|
|
@ -20,6 +20,61 @@ aliases {
|
|||
serial0 = &blsp_uart2;
|
||||
};
|
||||
|
||||
battery: battery {
|
||||
compatible = "simple-battery";
|
||||
device-chemistry = "lithium-ion-polymer";
|
||||
voltage-min-design-microvolt = <3400000>;
|
||||
voltage-max-design-microvolt = <4400000>;
|
||||
energy-full-design-microwatt-hours = <11500000>;
|
||||
charge-full-design-microamp-hours = <3000000>;
|
||||
|
||||
ocv-capacity-celsius = <(-20) 0 25 40 60>;
|
||||
ocv-capacity-table-0 = <4378000 100>, <4220000 95>, <4125000 90>,
|
||||
<4071000 85>, <3977000 80>, <3916000 75>, <3866000 70>,
|
||||
<3838000 65>, <3822000 60>, <3809000 55>, <3797000 50>,
|
||||
<3784000 45>, <3771000 40>, <3757000 35>, <3743000 30>,
|
||||
<3726000 25>, <3707000 20>, <3688000 16>, <3670000 13>,
|
||||
<3655000 11>, <3648000 10>, <3636000 9>, <3624000 8>,
|
||||
<3612000 7>, <3592000 6>, <3569000 5>, <3540000 4>,
|
||||
<3494000 3>, <3418000 2>, <3289000 1>, <3000000 0>;
|
||||
|
||||
ocv-capacity-table-1 = <4378000 100>, <4292000 95>, <4226000 90>,
|
||||
<4166000 85>, <4109000 80>, <4064000 75>, <3992000 70>,
|
||||
<3942000 65>, <3898000 60>, <3859000 55>, <3826000 50>,
|
||||
<3802000 45>, <3788000 40>, <3779000 35>, <3768000 30>,
|
||||
<3752000 25>, <3732000 20>, <3712000 16>, <3696000 13>,
|
||||
<3688000 11>, <3684000 10>, <3680000 9>, <3675000 8>,
|
||||
<3669000 7>, <3658000 6>, <3636000 5>, <3599000 4>,
|
||||
<3544000 3>, <3466000 2>, <3341000 1>, <3000000 0>;
|
||||
|
||||
ocv-capacity-table-2 = <4372000 100>, <4306000 95>, <4247000 90>,
|
||||
<4190000 85>, <4134000 80>, <4081000 75>, <4030000 70>,
|
||||
<3984000 65>, <3930000 60>, <3884000 55>, <3850000 50>,
|
||||
<3826000 45>, <3804000 40>, <3786000 35>, <3770000 30>,
|
||||
<3753000 25>, <3734000 20>, <3712000 16>, <3693000 13>,
|
||||
<3686000 11>, <3684000 10>, <3682000 9>, <3680000 8>,
|
||||
<3676000 7>, <3668000 6>, <3643000 5>, <3600000 4>,
|
||||
<3542000 3>, <3462000 2>, <3340000 1>, <3000000 0>;
|
||||
|
||||
ocv-capacity-table-3 = <4365000 100>, <4304000 95>, <4246000 90>,
|
||||
<4189000 85>, <4133000 80>, <4080000 75>, <4030000 70>,
|
||||
<3985000 65>, <3933000 60>, <3886000 55>, <3852000 50>,
|
||||
<3827000 45>, <3806000 40>, <3789000 35>, <3769000 30>,
|
||||
<3746000 25>, <3726000 20>, <3706000 16>, <3688000 13>,
|
||||
<3681000 11>, <3678000 10>, <3676000 9>, <3676000 8>,
|
||||
<3672000 7>, <3660000 6>, <3634000 5>, <3588000 4>,
|
||||
<3528000 3>, <3448000 2>, <3322000 1>, <3000000 0>;
|
||||
|
||||
ocv-capacity-table-4 = <4358000 100>, <4298000 95>, <4240000 90>,
|
||||
<4183000 85>, <4128000 80>, <4076000 75>, <4027000 70>,
|
||||
<3983000 65>, <3935000 60>, <3887000 55>, <3852000 50>,
|
||||
<3827000 45>, <3806000 40>, <3789000 35>, <3764000 30>,
|
||||
<3738000 25>, <3715000 20>, <3695000 16>, <3677000 13>,
|
||||
<3672000 11>, <3669000 10>, <3667000 9>, <3666000 8>,
|
||||
<3662000 7>, <3652000 6>, <3622000 5>, <3577000 4>,
|
||||
<3518000 3>, <3440000 2>, <3321000 1>, <3000000 0>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0";
|
||||
};
|
||||
|
|
@ -27,7 +82,7 @@ chosen {
|
|||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&gpio_keys_default>;
|
||||
pinctrl-0 = <&gpio_hall_sensor_default>, <&gpio_keys_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
button-volume-up {
|
||||
|
|
@ -43,6 +98,15 @@ button-volume-down {
|
|||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
debounce-interval = <15>;
|
||||
};
|
||||
|
||||
event-hall-sensor {
|
||||
label = "Hall Effect Sensor";
|
||||
gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
|
||||
linux,input-type = <EV_SW>;
|
||||
linux,code = <SW_LID>;
|
||||
linux,can-disable;
|
||||
debounce-interval = <150>;
|
||||
};
|
||||
};
|
||||
|
||||
reg_sd_vmmc: regulator-sdcard-vmmc {
|
||||
|
|
@ -135,6 +199,12 @@ &mpss_mem {
|
|||
reg = <0x0 0x86800000 0x0 0x5500000>;
|
||||
};
|
||||
|
||||
&pm8916_bms {
|
||||
monitored-battery = <&battery>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8916_codec {
|
||||
qcom,micbias-lvl = <2800>;
|
||||
qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
|
||||
|
|
@ -240,6 +310,13 @@ gpio_keys_default: gpio-keys-default-state {
|
|||
bias-pull-up;
|
||||
};
|
||||
|
||||
gpio_hall_sensor_default: gpio-hall-sensor-default-state {
|
||||
pins = "gpio108";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
usb_id_default: usb-id-default-state {
|
||||
pins = "gpio110";
|
||||
function = "gpio";
|
||||
|
|
|
|||
|
|
@ -11,6 +11,10 @@
|
|||
#include "msm8939.dtsi"
|
||||
#include "pm8916.dtsi"
|
||||
|
||||
&camss {
|
||||
vdda-supply = <&pm8916_l2>;
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-supply = <&pm8916_l2>;
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
|
|
|
|||
|
|
@ -1436,6 +1436,145 @@ mdss_dsi1_phy: phy@1aa0300 {
|
|||
};
|
||||
};
|
||||
|
||||
camss: isp@1b0ac00 {
|
||||
compatible = "qcom,msm8939-camss";
|
||||
reg = <0x01b0ac00 0x200>,
|
||||
<0x01b00030 0x4>,
|
||||
<0x01b0b000 0x200>,
|
||||
<0x01b00038 0x4>,
|
||||
<0x01b08000 0x100>,
|
||||
<0x01b08400 0x100>,
|
||||
<0x01b0a000 0x500>,
|
||||
<0x01b00020 0x10>,
|
||||
<0x01b10000 0x1000>,
|
||||
<0x01b08800 0x100>,
|
||||
<0x01b40000 0x200>;
|
||||
reg-names = "csiphy0",
|
||||
"csiphy0_clk_mux",
|
||||
"csiphy1",
|
||||
"csiphy1_clk_mux",
|
||||
"csid0",
|
||||
"csid1",
|
||||
"ispif",
|
||||
"csi_clk_mux",
|
||||
"vfe0",
|
||||
"csid2",
|
||||
"vfe0_vbif";
|
||||
|
||||
clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
|
||||
<&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI0_AHB_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI0_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI0PHY_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI0PIX_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI0RDI_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI1_AHB_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI1_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI1PHY_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI1PIX_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI1RDI_CLK>,
|
||||
<&gcc GCC_CAMSS_AHB_CLK>,
|
||||
<&gcc GCC_CAMSS_VFE0_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
|
||||
<&gcc GCC_CAMSS_VFE_AHB_CLK>,
|
||||
<&gcc GCC_CAMSS_VFE_AXI_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI2_AHB_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI2_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI2PHY_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI2PIX_CLK>,
|
||||
<&gcc GCC_CAMSS_CSI2RDI_CLK>;
|
||||
clock-names = "top_ahb",
|
||||
"ispif_ahb",
|
||||
"csiphy0_timer",
|
||||
"csiphy1_timer",
|
||||
"csi0_ahb",
|
||||
"csi0",
|
||||
"csi0_phy",
|
||||
"csi0_pix",
|
||||
"csi0_rdi",
|
||||
"csi1_ahb",
|
||||
"csi1",
|
||||
"csi1_phy",
|
||||
"csi1_pix",
|
||||
"csi1_rdi",
|
||||
"ahb",
|
||||
"vfe0",
|
||||
"csi_vfe0",
|
||||
"vfe_ahb",
|
||||
"vfe_axi",
|
||||
"csi2_ahb",
|
||||
"csi2",
|
||||
"csi2_phy",
|
||||
"csi2_pix",
|
||||
"csi2_rdi";
|
||||
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 153 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "csiphy0",
|
||||
"csiphy1",
|
||||
"csid0",
|
||||
"csid1",
|
||||
"ispif",
|
||||
"vfe0",
|
||||
"csid2";
|
||||
|
||||
iommus = <&apps_iommu 3>;
|
||||
|
||||
power-domains = <&gcc VFE_GDSC>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cci: cci@1b0c000 {
|
||||
compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
|
||||
reg = <0x01b0c000 0x1000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
|
||||
<&gcc GCC_CAMSS_CCI_AHB_CLK>,
|
||||
<&gcc GCC_CAMSS_CCI_CLK>,
|
||||
<&gcc GCC_CAMSS_AHB_CLK>;
|
||||
clock-names = "camss_top_ahb",
|
||||
"cci_ahb",
|
||||
"cci",
|
||||
"camss_ahb";
|
||||
assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
|
||||
<&gcc GCC_CAMSS_CCI_CLK>;
|
||||
assigned-clock-rates = <80000000>,
|
||||
<19200000>;
|
||||
pinctrl-0 = <&cci0_default>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
cci_i2c0: i2c-bus@0 {
|
||||
reg = <0>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpu: gpu@1c00000 {
|
||||
compatible = "qcom,adreno-405.0", "qcom,adreno";
|
||||
reg = <0x01c00000 0x10000>;
|
||||
|
|
@ -1500,6 +1639,13 @@ apps_iommu: iommu@1ef0000 {
|
|||
#iommu-cells = <1>;
|
||||
qcom,iommu-secure-id = <17>;
|
||||
|
||||
/* vfe */
|
||||
iommu-ctx@3000 {
|
||||
compatible = "qcom,msm-iommu-v1-sec";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
/* mdp_0: */
|
||||
iommu-ctx@4000 {
|
||||
compatible = "qcom,msm-iommu-v1-ns";
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ / {
|
|||
chassis-type = "handset";
|
||||
|
||||
qcom,msm-id = <251 0>, <252 0>;
|
||||
qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
|
||||
qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>;
|
||||
|
||||
/* Bullhead firmware doesn't support PSCI */
|
||||
/delete-node/ psci;
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ / {
|
|||
chassis-type = "handset";
|
||||
/* required for bootloader to select correct board */
|
||||
qcom,msm-id = <207 0x20000>;
|
||||
qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
|
||||
qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>;
|
||||
qcom,board-id = <8026 0>;
|
||||
|
||||
aliases {
|
||||
|
|
|
|||
|
|
@ -378,7 +378,7 @@ &blsp2_i2c1 {
|
|||
status = "okay";
|
||||
|
||||
sideinteraction: touch@2c {
|
||||
compatible = "ad,ad7147_captouch";
|
||||
compatible = "adi,ad7147_captouch";
|
||||
reg = <0x2c>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
|
|
|||
67
arch/arm64/boot/dts/qcom/pm7550.dtsi
Normal file
67
arch/arm64/boot/dts/qcom/pm7550.dtsi
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
/ {
|
||||
thermal-zones {
|
||||
pm7550_thermal: pm7550-thermal {
|
||||
polling-delay-passive = <100>;
|
||||
|
||||
thermal-sensors = <&pm7550_temp_alarm>;
|
||||
|
||||
trips {
|
||||
trip0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
trip1 {
|
||||
/*
|
||||
* Current Linux driver currently only supports up to
|
||||
* 125°C, should be updated to 145°C once available.
|
||||
*/
|
||||
temperature = <125000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spmi_bus {
|
||||
pm7550: pmic@1 {
|
||||
compatible = "qcom,pm7550", "qcom,spmi-pmic";
|
||||
reg = <0x1 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pm7550_temp_alarm: temp-alarm@a00 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0xa00>;
|
||||
interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
pm7550_gpios: gpio@8800 {
|
||||
compatible = "qcom,pm7550-gpio", "qcom,spmi-gpio";
|
||||
reg = <0x8800>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pm7550_gpios 0 0 12>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pm7550_flash: led-controller@ee00 {
|
||||
compatible = "qcom,pm7550-flash-led", "qcom,spmi-flash-led";
|
||||
reg = <0xee00>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -98,6 +98,8 @@ pm8550vs_c: pmic@2 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pm8550vs_c_temp_alarm: temp-alarm@a00 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0xa00>;
|
||||
|
|
@ -122,6 +124,8 @@ pm8550vs_d: pmic@3 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pm8550vs_d_temp_alarm: temp-alarm@a00 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0xa00>;
|
||||
|
|
@ -146,6 +150,8 @@ pm8550vs_e: pmic@4 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pm8550vs_e_temp_alarm: temp-alarm@a00 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0xa00>;
|
||||
|
|
@ -170,6 +176,8 @@ pm8550vs_g: pmic@6 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pm8550vs_g_temp_alarm: temp-alarm@a00 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0xa00>;
|
||||
|
|
|
|||
73
arch/arm64/boot/dts/qcom/pmiv0104.dtsi
Normal file
73
arch/arm64/boot/dts/qcom/pmiv0104.dtsi
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
/ {
|
||||
thermal-zones {
|
||||
pmiv0104-thermal {
|
||||
polling-delay-passive = <100>;
|
||||
|
||||
thermal-sensors = <&pmiv0104_temp_alarm>;
|
||||
|
||||
trips {
|
||||
trip0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
trip1 {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "hot";
|
||||
};
|
||||
|
||||
trip2 {
|
||||
/*
|
||||
* Current Linux driver currently only supports up to
|
||||
* 125°C, should be updated to 145°C once available.
|
||||
*/
|
||||
temperature = <125000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spmi_bus {
|
||||
pmic@PMIV0104_SID {
|
||||
compatible = "qcom,pmiv0104", "qcom,spmi-pmic";
|
||||
reg = <PMIV0104_SID SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmiv0104_temp_alarm: temp-alarm@a00 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0xa00>;
|
||||
interrupts = <PMIV0104_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
pmiv0104_gpios: gpio@8800 {
|
||||
compatible = "qcom,pmiv0104-gpio", "qcom,spmi-gpio";
|
||||
reg = <0x8800>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pmiv0104_gpios 0 0 10>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pmiv0104_eusb2_repeater: phy@fd00 {
|
||||
compatible = "qcom,pmiv0104-eusb2-repeater";
|
||||
reg = <0xfd00>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -39,6 +39,20 @@ xo_board_clk: xo-board-clk {
|
|||
};
|
||||
};
|
||||
|
||||
dp0-connector {
|
||||
compatible = "dp-connector";
|
||||
label = "DP0";
|
||||
type = "mini";
|
||||
|
||||
hpd-gpios = <&io_expander 8 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
port {
|
||||
dp0_connector_in: endpoint {
|
||||
remote-endpoint = <&mdss_dp0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dp-dsi0-connector {
|
||||
compatible = "dp-connector";
|
||||
label = "DSI0";
|
||||
|
|
@ -423,6 +437,15 @@ &mdss {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dp0_out {
|
||||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>;
|
||||
remote-endpoint = <&dp0_connector_in>;
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-supply = <&vreg_l11a>;
|
||||
status = "okay";
|
||||
|
|
@ -624,6 +647,13 @@ &usb_qmpphy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_qmpphy_2 {
|
||||
vdda-phy-supply = <&vreg_l5a>;
|
||||
vdda-pll-supply = <&vreg_l12a>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -262,6 +262,30 @@ active-config0 {
|
|||
};
|
||||
};
|
||||
|
||||
vdd_ntn_0p9: regulator-vdd-ntn-0p9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_NTN_0P9";
|
||||
gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>;
|
||||
regulator-min-microvolt = <899400>;
|
||||
regulator-max-microvolt = <899400>;
|
||||
enable-active-high;
|
||||
pinctrl-0 = <&ntn_0p9_en>;
|
||||
pinctrl-names = "default";
|
||||
regulator-enable-ramp-delay = <4300>;
|
||||
};
|
||||
|
||||
vdd_ntn_1p8: regulator-vdd-ntn-1p8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_NTN_1P8";
|
||||
gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
enable-active-high;
|
||||
pinctrl-0 = <&ntn_1p8_en>;
|
||||
pinctrl-names = "default";
|
||||
regulator-enable-ramp-delay = <10000>;
|
||||
};
|
||||
|
||||
wcn6750-pmu {
|
||||
compatible = "qcom,wcn6750-pmu";
|
||||
pinctrl-0 = <&bt_en>;
|
||||
|
|
@ -803,6 +827,78 @@ &pcie1_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1_port0 {
|
||||
pcie@0,0 {
|
||||
compatible = "pci1179,0623";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
device_type = "pci";
|
||||
ranges;
|
||||
bus-range = <0x2 0xff>;
|
||||
|
||||
vddc-supply = <&vdd_ntn_0p9>;
|
||||
vdd18-supply = <&vdd_ntn_1p8>;
|
||||
vdd09-supply = <&vdd_ntn_0p9>;
|
||||
vddio1-supply = <&vdd_ntn_1p8>;
|
||||
vddio2-supply = <&vdd_ntn_1p8>;
|
||||
vddio18-supply = <&vdd_ntn_1p8>;
|
||||
|
||||
i2c-parent = <&i2c0 0x77>;
|
||||
|
||||
resx-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&tc9563_resx_n>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
pcie@1,0 {
|
||||
reg = <0x20800 0x0 0x0 0x0 0x0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
device_type = "pci";
|
||||
ranges;
|
||||
bus-range = <0x3 0xff>;
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
reg = <0x21000 0x0 0x0 0x0 0x0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
device_type = "pci";
|
||||
ranges;
|
||||
bus-range = <0x4 0xff>;
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
reg = <0x21800 0x0 0x0 0x0 0x0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
ranges;
|
||||
bus-range = <0x5 0xff>;
|
||||
|
||||
pci@0,0 {
|
||||
reg = <0x50000 0x0 0x0 0x0 0x0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
ranges;
|
||||
};
|
||||
|
||||
pci@0,1 {
|
||||
reg = <0x50100 0x0 0x0 0x0 0x0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pm7325_gpios {
|
||||
kypd_vol_up_n: kypd-vol-up-n-state {
|
||||
pins = "gpio6";
|
||||
|
|
@ -1081,6 +1177,38 @@ right_spkr: speaker@0,2 {
|
|||
};
|
||||
};
|
||||
|
||||
&pm8350c_gpios {
|
||||
ntn_0p9_en: ntn-0p9-en-state {
|
||||
pins = "gpio2";
|
||||
function = "normal";
|
||||
|
||||
bias-disable;
|
||||
input-disable;
|
||||
output-enable;
|
||||
power-source = <0>;
|
||||
};
|
||||
|
||||
ntn_1p8_en: ntn-1p8-en-state {
|
||||
pins = "gpio3";
|
||||
function = "normal";
|
||||
|
||||
bias-disable;
|
||||
input-disable;
|
||||
output-enable;
|
||||
power-source = <0>;
|
||||
};
|
||||
|
||||
tc9563_resx_n: tc9563-resx-state {
|
||||
pins = "gpio1";
|
||||
function = "normal";
|
||||
|
||||
bias-disable;
|
||||
input-disable;
|
||||
output-enable;
|
||||
power-source = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <32 2>, /* ADSP */
|
||||
<48 4>; /* NFC */
|
||||
|
|
|
|||
1410
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
Normal file
1410
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -24,6 +24,18 @@ chosen {
|
|||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
dp0-connector {
|
||||
compatible = "dp-connector";
|
||||
label = "DP0";
|
||||
type = "full-size";
|
||||
|
||||
port {
|
||||
dp0_connector_in: endpoint {
|
||||
remote-endpoint = <&mdss_dp0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
regulator-usb2-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "USB2_VBUS";
|
||||
|
|
@ -317,6 +329,68 @@ &iris {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dp0 {
|
||||
pinctrl-0 = <&dp_hot_plug_det>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dp0_out {
|
||||
data-lanes = <0 1 2 3>;
|
||||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
|
||||
remote-endpoint = <&dp0_connector_in>;
|
||||
};
|
||||
|
||||
&mdss_dp0_phy {
|
||||
vdda-phy-supply = <&vreg_l5a>;
|
||||
vdda-pll-supply = <&vreg_l4a>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-0 = <&pcie0_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcieport0 {
|
||||
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&pcie0_phy {
|
||||
vdda-phy-supply = <&vreg_l6a>;
|
||||
vdda-pll-supply = <&vreg_l5a>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
pinctrl-0 = <&pcie1_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcieport1 {
|
||||
reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&pcie1_phy {
|
||||
vdda-phy-supply = <&vreg_l6a>;
|
||||
vdda-pll-supply = <&vreg_l5a>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -362,6 +436,29 @@ &sdhc_1 {
|
|||
};
|
||||
|
||||
&tlmm {
|
||||
pcie0_default_state: pcie0-default-state {
|
||||
wake-pins {
|
||||
pins = "gpio0";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
clkreq-pins {
|
||||
pins = "gpio1";
|
||||
function = "pcie0_clkreq";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-pins {
|
||||
pins = "gpio2";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet0_default: ethernet0-default-state {
|
||||
ethernet0_mdc: ethernet0-mdc-pins {
|
||||
pins = "gpio5";
|
||||
|
|
@ -377,6 +474,35 @@ ethernet0_mdio: ethernet0-mdio-pins {
|
|||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_default_state: pcie1-default-state {
|
||||
wake-pins {
|
||||
pins = "gpio21";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
clkreq-pins {
|
||||
pins = "gpio22";
|
||||
function = "pcie1_clkreq";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-pins {
|
||||
pins = "gpio23";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
dp_hot_plug_det: dp-hot-plug-det-state {
|
||||
pins = "gpio94";
|
||||
function = "edp0_hot";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
|
|
|
|||
|
|
@ -366,6 +366,22 @@ &pm8550b_eusb2_repeater {
|
|||
vdd3-supply = <&vreg_l5b_3p1>;
|
||||
};
|
||||
|
||||
&pm8550vs_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_d {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_e {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_g {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sleep_clk {
|
||||
clock-frequency = <32764>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1592,7 +1592,7 @@ cpufreq_hw: cpufreq@17d90000 {
|
|||
|
||||
gem_noc: interconnect@19100000 {
|
||||
compatible = "qcom,qdu1000-gem-noc";
|
||||
reg = <0x0 0x19100000 0x0 0xB8080>;
|
||||
reg = <0x0 0x19100000 0x0 0xb8080>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
#interconnect-cells = <2>;
|
||||
};
|
||||
|
|
|
|||
459
arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts
Normal file
459
arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts
Normal file
|
|
@ -0,0 +1,459 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) 2025, Arduino SRL
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include "agatti.dtsi"
|
||||
#include "pm4125.dtsi"
|
||||
|
||||
/delete-node/ &cont_splash_memory;
|
||||
|
||||
/ {
|
||||
model = "Arduino UnoQ";
|
||||
compatible = "arduino,imola", "qcom,qrb2210", "qcom,qcm2290";
|
||||
chassis-type = "embedded";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
sdhc1 = &sdhc_1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
label = "gpio-keys";
|
||||
pinctrl-0 = <&key_volp_n>, <&key_vold_n>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
key-volume-up {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
|
||||
debounce-interval = <15>;
|
||||
linux,can-disable;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
key-volume-down {
|
||||
label = "Volume Down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
|
||||
debounce-interval = <15>;
|
||||
linux,can-disable;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
leds: leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-bt {
|
||||
label = "unoq:bt-blue2";
|
||||
function = LED_FUNCTION_BLUETOOTH;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "bluetooth-power";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-panic {
|
||||
label = "unoq:panic-red2";
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "none";
|
||||
default-state = "off";
|
||||
panic-indicator;
|
||||
};
|
||||
|
||||
led-wlan {
|
||||
label = "unoq:wlan-green2";
|
||||
function = LED_FUNCTION_WLAN;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "phy0tx";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
ledb: led-user-blue {
|
||||
label = "unoq:user-blue1";
|
||||
gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
};
|
||||
|
||||
ledg: led-user-green {
|
||||
label = "unoq:user-green1";
|
||||
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
ledr: led-user-red {
|
||||
label = "unoq:user-red1";
|
||||
gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
};
|
||||
|
||||
multi-led {
|
||||
compatible = "leds-group-multicolor";
|
||||
color = <LED_COLOR_ID_RGB>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
leds = <&ledr>, <&ledg>, <&ledb>;
|
||||
};
|
||||
|
||||
/* PM4125 charger out, supplied by VBAT */
|
||||
vph_pwr: regulator-vph-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&gpi_dma0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/qcm2290/a702_zap.mbn";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm4125_vbus {
|
||||
regulator-min-microamp = <500000>;
|
||||
regulator-max-microamp = <500000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/qcm2290/adsp.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_mpss {
|
||||
firmware-name = "qcom/qcm2290/modem.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rpm_requests {
|
||||
regulators {
|
||||
compatible = "qcom,rpm-pm2250-regulators";
|
||||
vdd_s3-supply = <&vph_pwr>;
|
||||
vdd_s4-supply = <&vph_pwr>;
|
||||
vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm4125_s3>;
|
||||
vdd_l4_l17_l18_l19_l20_l21_l22-supply = <&vph_pwr>;
|
||||
vdd_l13_l14_l15_l16-supply = <&pm4125_s4>;
|
||||
|
||||
pm4125_s3: s3 {
|
||||
/* 0.4V-1.6625V -> 1.3V (Power tree requirements) */
|
||||
regulator-min-microvolt = <1352000>;
|
||||
regulator-max-microvolt = <1352000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
pm4125_s4: s4 {
|
||||
/* 1.2V-2.35V -> 2.05V (Power tree requirements) */
|
||||
regulator-min-microvolt = <2072000>;
|
||||
regulator-max-microvolt = <2072000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
pm4125_l2: l2 {
|
||||
/* LPDDR4X VDD2 */
|
||||
regulator-min-microvolt = <1136000>;
|
||||
regulator-max-microvolt = <1136000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
pm4125_l3: l3 {
|
||||
/* LPDDR4X VDDQ */
|
||||
regulator-min-microvolt = <616000>;
|
||||
regulator-max-microvolt = <616000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
pm4125_l4: l4 {
|
||||
/* max = 3.05V -> max = 2.7 to disable 3V signaling (SDHCI2) */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
pm4125_l5: l5 {
|
||||
/* CSI/DSI */
|
||||
regulator-min-microvolt = <1232000>;
|
||||
regulator-max-microvolt = <1232000>;
|
||||
regulator-allow-set-load;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
pm4125_l6: l6 {
|
||||
/* DRAM PLL */
|
||||
regulator-min-microvolt = <928000>;
|
||||
regulator-max-microvolt = <928000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
pm4125_l7: l7 {
|
||||
/* Wi-Fi CX */
|
||||
regulator-min-microvolt = <664000>;
|
||||
regulator-max-microvolt = <664000>;
|
||||
};
|
||||
|
||||
pm4125_l10: l10 {
|
||||
/* Wi-Fi RFA */
|
||||
regulator-min-microvolt = <1304000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
};
|
||||
|
||||
pm4125_l11: l11 {
|
||||
/* ANX7625 DVDD1P0V/AVDD1P0V */
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
pm4125_l12: l12 {
|
||||
/* USB PHYs */
|
||||
regulator-min-microvolt = <928000>;
|
||||
regulator-max-microvolt = <928000>;
|
||||
regulator-allow-set-load;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
pm4125_l13: l13 {
|
||||
/* USB/QFPROM/PLLs */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-allow-set-load;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
pm4125_l14: l14 {
|
||||
/* SDHCI1 EMMC VCCQ */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-allow-set-load;
|
||||
/* Broken hardware, never turn it off! */
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
pm4125_l15: l15 {
|
||||
/* VDDIO */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-allow-set-load;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
pm4125_l20: l20 {
|
||||
/* SDHCI1 EMMC */
|
||||
regulator-min-microvolt = <2400000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
pm4125_l21: l21 {
|
||||
/* USB HS */
|
||||
regulator-min-microvolt = <2960000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-allow-set-load;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
pm4125_l22: l22 {
|
||||
/* Wi-Fi VDD */
|
||||
regulator-min-microvolt = <3312000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
vmmc-supply = <&pm4125_l20>;
|
||||
vqmmc-supply = <&pm4125_l14>;
|
||||
pinctrl-0 = <&sdc1_state_on>;
|
||||
pinctrl-1 = <&sdc1_state_off>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
supports-cqe;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi5 {
|
||||
status = "okay";
|
||||
|
||||
spidev@0 {
|
||||
reg = <0>;
|
||||
compatible = "arduino,unoq-mcu";
|
||||
pinctrl-0 = <&spidev_cs>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
spidev_cs: spidev-cs-state {
|
||||
pins = "gpio17";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
};
|
||||
|
||||
jmisc_gpio18: jmisc-gpio18-state {
|
||||
pins = "gpio18";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
jmisc_gpio28: jmisc-gpio28-state {
|
||||
pins = "gpio28";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
key_vold_n: key-vold-n-state {
|
||||
pins = "gpio36";
|
||||
function = "gpio";
|
||||
bias-pull-up;
|
||||
output-disable;
|
||||
};
|
||||
|
||||
key_volp_n: key-volp-n-state {
|
||||
pins = "gpio96";
|
||||
function = "gpio";
|
||||
bias-pull-up;
|
||||
output-disable;
|
||||
};
|
||||
|
||||
jmisc_gpio98: jmisc-gpio98-state {
|
||||
pins = "gpio98";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
jmisc_gpio99: jmisc-gpio99-state {
|
||||
pins = "gpio99";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
jmisc_gpio100: jmisc-gpio100-state {
|
||||
pins = "gpio100";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
jmisc_gpio101: jmisc-gpio101-state {
|
||||
pins = "gpio101";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* UART connected to Bluetooth */
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "qcom,wcn3988-bt";
|
||||
|
||||
vddio-supply = <&pm4125_l15>;
|
||||
vddxo-supply = <&pm4125_l13>;
|
||||
vddrf-supply = <&pm4125_l10>;
|
||||
vddch0-supply = <&pm4125_l22>;
|
||||
enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
|
||||
max-speed = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* UART exposed in JCTL */
|
||||
&uart4 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_hsphy {
|
||||
vdd-supply = <&pm4125_l12>;
|
||||
vdda-pll-supply = <&pm4125_l13>;
|
||||
vdda-phy-dpdm-supply = <&pm4125_l21>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_qmpphy {
|
||||
vdda-phy-supply = <&pm4125_l12>;
|
||||
vdda-pll-supply = <&pm4125_l13>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
vdd-0.8-cx-mx-supply = <&pm4125_l7>;
|
||||
vdd-1.8-xo-supply = <&pm4125_l13>;
|
||||
vdd-1.3-rfa-supply = <&pm4125_l10>;
|
||||
vdd-3.3-ch0-supply = <&pm4125_l22>;
|
||||
qcom,ath10k-calibration-variant = "ArduinoImola";
|
||||
firmware-name = "qcm2290";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xo_board {
|
||||
clock-frequency = <38400000>;
|
||||
};
|
||||
66
arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso
Normal file
66
arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
&pm8008 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&camss {
|
||||
status = "okay";
|
||||
|
||||
vdd-csiphy-1p2-supply = <&pm4125_l5>;
|
||||
vdd-csiphy-1p8-supply = <&pm4125_l13>;
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
csiphy0_ep: endpoint {
|
||||
data-lanes = <0 1>;
|
||||
remote-endpoint = <&ov9282_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cci_i2c1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Vision Mezzanine DIP3-1 must be ON (Selects camera CAM0A&B) */
|
||||
camera@60 {
|
||||
compatible = "ovti,ov9282";
|
||||
reg = <0x60>;
|
||||
|
||||
/* Reset is active-low, but driver applies inverted reset logic */
|
||||
reset-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&mclk3_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
clocks = <&gcc GCC_CAMSS_MCLK3_CLK>;
|
||||
assigned-clocks = <&gcc GCC_CAMSS_MCLK3_CLK>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
|
||||
avdd-supply = <&vreg_l3p>;
|
||||
dvdd-supply = <&vreg_l1p>;
|
||||
dovdd-supply = <&vreg_l7p>;
|
||||
|
||||
port {
|
||||
ov9282_ep: endpoint {
|
||||
link-frequencies = /bits/ 64 <400000000>;
|
||||
data-lanes = <1 2>;
|
||||
remote-endpoint = <&csiphy0_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -267,6 +267,81 @@ &gpu_zap_shader {
|
|||
firmware-name = "qcom/qcm2290/a702_zap.mbn";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
pm8008: pmic@8 {
|
||||
compatible = "qcom,pm8008";
|
||||
reg = <0x8>;
|
||||
|
||||
interrupts-extended = <&tlmm 25 IRQ_TYPE_EDGE_RISING>;
|
||||
reset-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vdd-l1-l2-supply = <&pm4125_s3>;
|
||||
vdd-l3-l4-supply = <&vph_pwr>;
|
||||
vdd-l5-supply = <&vph_pwr>;
|
||||
vdd-l6-supply = <&vph_pwr>;
|
||||
vdd-l7-supply = <&vph_pwr>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pm8008 0 0 2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
#thermal-sensor-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
regulators {
|
||||
vreg_l1p: ldo1 {
|
||||
regulator-name = "vreg_l1p";
|
||||
regulator-min-microvolt = <528000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
vreg_l2p: ldo2 {
|
||||
regulator-name = "vreg_l2p";
|
||||
regulator-min-microvolt = <528000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
vreg_l3p: ldo3 {
|
||||
regulator-name = "vreg_l3p";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
};
|
||||
|
||||
vreg_l4p: ldo4 {
|
||||
regulator-name = "vreg_l4p";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <3404000>;
|
||||
};
|
||||
|
||||
vreg_l5p: ldo5 {
|
||||
regulator-name = "vreg_l5p";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
};
|
||||
|
||||
vreg_l6p: ldo6 {
|
||||
regulator-name = "vreg_l6p";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
};
|
||||
|
||||
vreg_l7p: ldo7 {
|
||||
regulator-name = "vreg_l7p";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2_gpio {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -694,7 +694,7 @@ sdc2_card_det_n: sd-card-det-n-state {
|
|||
|
||||
&uart3 {
|
||||
interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&tlmm 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
<&tlmm 11 IRQ_TYPE_EDGE_FALLING>;
|
||||
pinctrl-0 = <&uart3_default>;
|
||||
pinctrl-1 = <&uart3_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
|
|
|||
|
|
@ -67,6 +67,11 @@ &lpass_hm {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&lpass_tlmm {
|
||||
/delete-property/ clocks;
|
||||
/delete-property/ clock-names;
|
||||
};
|
||||
|
||||
&lpasscc {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -3041,8 +3041,8 @@ swr1: soundwire@3210000 {
|
|||
qcom,dout-ports = <5>;
|
||||
|
||||
qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
|
||||
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
|
||||
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
|
||||
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
|
||||
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
|
||||
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
|
||||
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
|
||||
qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
|
||||
|
|
|
|||
|
|
@ -262,7 +262,7 @@ perf_cpu_sleep_1: cpu-sleep-1-1 {
|
|||
pwr_cluster_sleep_0: cluster-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "pwr-cluster-dynamic-retention";
|
||||
arm,psci-suspend-param = <0x400000F2>;
|
||||
arm,psci-suspend-param = <0x400000f2>;
|
||||
entry-latency-us = <284>;
|
||||
exit-latency-us = <384>;
|
||||
min-residency-us = <9987>;
|
||||
|
|
@ -272,7 +272,7 @@ pwr_cluster_sleep_0: cluster-sleep-0-0 {
|
|||
pwr_cluster_sleep_1: cluster-sleep-0-1 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "pwr-cluster-retention";
|
||||
arm,psci-suspend-param = <0x400000F3>;
|
||||
arm,psci-suspend-param = <0x400000f3>;
|
||||
entry-latency-us = <338>;
|
||||
exit-latency-us = <423>;
|
||||
min-residency-us = <9987>;
|
||||
|
|
@ -282,7 +282,7 @@ pwr_cluster_sleep_1: cluster-sleep-0-1 {
|
|||
pwr_cluster_sleep_2: cluster-sleep-0-2 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "pwr-cluster-retention";
|
||||
arm,psci-suspend-param = <0x400000F4>;
|
||||
arm,psci-suspend-param = <0x400000f4>;
|
||||
entry-latency-us = <515>;
|
||||
exit-latency-us = <1821>;
|
||||
min-residency-us = <9987>;
|
||||
|
|
@ -292,7 +292,7 @@ pwr_cluster_sleep_2: cluster-sleep-0-2 {
|
|||
perf_cluster_sleep_0: cluster-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "perf-cluster-dynamic-retention";
|
||||
arm,psci-suspend-param = <0x400000F2>;
|
||||
arm,psci-suspend-param = <0x400000f2>;
|
||||
entry-latency-us = <272>;
|
||||
exit-latency-us = <329>;
|
||||
min-residency-us = <9987>;
|
||||
|
|
@ -302,7 +302,7 @@ perf_cluster_sleep_0: cluster-sleep-1-0 {
|
|||
perf_cluster_sleep_1: cluster-sleep-1-1 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "perf-cluster-retention";
|
||||
arm,psci-suspend-param = <0x400000F3>;
|
||||
arm,psci-suspend-param = <0x400000f3>;
|
||||
entry-latency-us = <332>;
|
||||
exit-latency-us = <368>;
|
||||
min-residency-us = <9987>;
|
||||
|
|
@ -312,7 +312,7 @@ perf_cluster_sleep_1: cluster-sleep-1-1 {
|
|||
perf_cluster_sleep_2: cluster-sleep-1-2 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "perf-cluster-retention";
|
||||
arm,psci-suspend-param = <0x400000F4>;
|
||||
arm,psci-suspend-param = <0x400000f4>;
|
||||
entry-latency-us = <545>;
|
||||
exit-latency-us = <1609>;
|
||||
min-residency-us = <9987>;
|
||||
|
|
@ -563,7 +563,7 @@ modem_smp2p_in: slave-kernel {
|
|||
};
|
||||
};
|
||||
|
||||
soc@0 {
|
||||
soc: soc@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
|
|
@ -598,8 +598,8 @@ qusb2_hstx_trim: hstx-trim@240 {
|
|||
};
|
||||
|
||||
gpu_speed_bin: gpu-speed-bin@41a0 {
|
||||
reg = <0x41a2 0x1>;
|
||||
bits = <5 7>;
|
||||
reg = <0x41a2 0x2>;
|
||||
bits = <5 8>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -1217,6 +1217,11 @@ lpass_smmu: iommu@5100000 {
|
|||
reg = <0x05100000 0x40000>;
|
||||
#iommu-cells = <1>;
|
||||
|
||||
clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
|
||||
clock-names = "bus";
|
||||
|
||||
power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
|
||||
|
||||
#global-interrupts = <2>;
|
||||
interrupts =
|
||||
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -1563,6 +1568,7 @@ mdss: display-subsystem@c900000 {
|
|||
reg-names = "mdss_phys", "vbif_phys";
|
||||
|
||||
power-domains = <&mmcc MDSS_GDSC>;
|
||||
resets = <&mmcc MDSS_BCR>;
|
||||
|
||||
clocks = <&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_AXI_CLK>,
|
||||
|
|
@ -2263,6 +2269,79 @@ mmss_smmu: iommu@cd00000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi_tlmm: pinctrl@15070000 {
|
||||
compatible = "qcom,sdm660-lpass-lpi-pinctrl";
|
||||
reg = <0x15070000 0x20000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&lpi_tlmm 0 0 32>;
|
||||
|
||||
cdc_pdm_default: cdc-pdm-default-state {
|
||||
clk-pins {
|
||||
pins = "gpio18";
|
||||
function = "pdm_clk";
|
||||
drive-strength = <8>;
|
||||
output-high;
|
||||
};
|
||||
|
||||
sync-pins {
|
||||
pins = "gpio19";
|
||||
function = "pdm_sync";
|
||||
drive-strength = <4>;
|
||||
output-high;
|
||||
};
|
||||
|
||||
tx-pins {
|
||||
pins = "gpio20";
|
||||
function = "pdm_tx";
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
rx-pins {
|
||||
pins = "gpio21", "gpio23", "gpio25";
|
||||
function = "pdm_rx";
|
||||
drive-strength = <4>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
cdc_comp_default: cdc-comp-default-state {
|
||||
pins = "gpio22", "gpio24";
|
||||
function = "comp_rx";
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
cdc_dmic_default: cdc-dmic-default-state {
|
||||
dmic1-clk-pins {
|
||||
pins = "gpio26";
|
||||
function = "dmic1_clk";
|
||||
drive-strength = <8>;
|
||||
output-high;
|
||||
};
|
||||
|
||||
dmic1-data-pins {
|
||||
pins = "gpio27";
|
||||
function = "dmic1_data";
|
||||
drive-strength = <8>;
|
||||
output-high;
|
||||
};
|
||||
|
||||
dmic2-clk-pins {
|
||||
pins = "gpio28";
|
||||
function = "dmic2_clk";
|
||||
drive-strength = <8>;
|
||||
input-enable;
|
||||
};
|
||||
|
||||
dmic2-data-pins {
|
||||
pins = "gpio29";
|
||||
function = "dmic2_data";
|
||||
drive-strength = <8>;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
adsp_pil: remoteproc@15700000 {
|
||||
compatible = "qcom,sdm660-adsp-pas";
|
||||
reg = <0x15700000 0x4040>;
|
||||
|
|
@ -2337,6 +2416,39 @@ q6routing: routing {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
label = "adsp";
|
||||
qcom,non-secure-domain;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <1>;
|
||||
iommus = <&lpass_smmu 3>;
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <2>;
|
||||
iommus = <&lpass_smmu 7>;
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&lpass_smmu 8>;
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&lpass_smmu 9>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -7,15 +7,20 @@
|
|||
|
||||
#include "sdm660.dtsi"
|
||||
|
||||
/*
|
||||
* According to the downstream DTS,
|
||||
* 636 is basically a 660 except for
|
||||
* different CPU frequencies, Adreno
|
||||
* 509 instead of 512 and lack of
|
||||
* turing IP. These differences will
|
||||
* be addressed when the aforementioned
|
||||
* peripherals will be enabled upstream.
|
||||
*/
|
||||
/delete-node/ &remoteproc_cdsp;
|
||||
/delete-node/ &cdsp_smmu;
|
||||
/delete-node/ &cdsp_region;
|
||||
|
||||
/ {
|
||||
/delete-node/ smp2p-cdsp;
|
||||
|
||||
reserved-memory {
|
||||
buffer_mem: tzbuffer@94a00000 {
|
||||
reg = <0x0 0x94a00000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adreno_gpu {
|
||||
compatible = "qcom,adreno-509.0", "qcom,adreno";
|
||||
|
|
|
|||
|
|
@ -9,6 +9,37 @@
|
|||
|
||||
#include "sdm630.dtsi"
|
||||
|
||||
/delete-node/ &buffer_mem;
|
||||
|
||||
/ {
|
||||
smp2p-cdsp {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <94>, <432>;
|
||||
interrupts = <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&apcs_glb 30>;
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <5>;
|
||||
|
||||
cdsp_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
cdsp_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
cdsp_region: cdsp@94a00000 {
|
||||
reg = <0x0 0x94a00000 0x00 0x600000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adreno_gpu {
|
||||
compatible = "qcom,adreno-512.0", "qcom,adreno";
|
||||
operating-points-v2 = <&gpu_sdm660_opp_table>;
|
||||
|
|
@ -247,6 +278,136 @@ &mmcc {
|
|||
<0>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
cdsp_smmu: iommu@5180000 {
|
||||
compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
|
||||
reg = <0x5180000 0x40000>;
|
||||
#iommu-cells = <1>;
|
||||
|
||||
#global-interrupts = <2>;
|
||||
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_HLOS1_VOTE_TURING_ADSP_SMMU_CLK>;
|
||||
clock-names = "bus";
|
||||
|
||||
power-domains = <&gcc HLOS1_VOTE_TURING_ADSP_GDSC>;
|
||||
|
||||
};
|
||||
|
||||
remoteproc_cdsp: remoteproc@1a300000 {
|
||||
compatible = "qcom,sdm660-cdsp-pas";
|
||||
reg = <0x1a300000 0x00100>;
|
||||
interrupts-extended = <&intc GIC_SPI 518 IRQ_TYPE_EDGE_RISING>,
|
||||
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "wdog",
|
||||
"fatal",
|
||||
"ready",
|
||||
"handover",
|
||||
"stop-ack";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
|
||||
clock-names = "xo";
|
||||
|
||||
memory-region = <&cdsp_region>;
|
||||
power-domains = <&rpmpd SDM660_VDDCX>;
|
||||
power-domain-names = "cx";
|
||||
|
||||
qcom,smem-states = <&cdsp_smp2p_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
|
||||
glink-edge {
|
||||
interrupts = <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
label = "cdsp";
|
||||
mboxes = <&apcs_glb 29>;
|
||||
qcom,remote-pid = <5>;
|
||||
|
||||
fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
label = "cdsp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&cdsp_smmu 3>;
|
||||
};
|
||||
|
||||
compute-cb@6 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
iommus = <&cdsp_smmu 4>;
|
||||
};
|
||||
|
||||
compute-cb@7 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <7>;
|
||||
iommus = <&cdsp_smmu 5>;
|
||||
};
|
||||
|
||||
compute-cb@8 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <8>;
|
||||
iommus = <&cdsp_smmu 6>;
|
||||
};
|
||||
|
||||
compute-cb@9 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <9>;
|
||||
iommus = <&cdsp_smmu 7>;
|
||||
};
|
||||
|
||||
compute-cb@10 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <10>;
|
||||
iommus = <&cdsp_smmu 8>;
|
||||
};
|
||||
|
||||
compute-cb@11 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <11>;
|
||||
iommus = <&cdsp_smmu 9>;
|
||||
};
|
||||
|
||||
compute-cb@12 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <12>;
|
||||
iommus = <&cdsp_smmu 10>;
|
||||
};
|
||||
|
||||
compute-cb@13 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <13>;
|
||||
iommus = <&cdsp_smmu 11>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
compatible = "qcom,sdm660-pinctrl";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -634,7 +634,7 @@ qfprom: qfprom@784000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
gpu_speed_bin: gpu_speed_bin@1a2 {
|
||||
gpu_speed_bin: gpu-speed-bin@1a2 {
|
||||
reg = <0x1a2 0x2>;
|
||||
bits = <5 8>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -379,6 +379,12 @@ vreg_l21a_2p95: ldo21 {
|
|||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l23a_3p3: ldo23 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l24a_3p075: ldo24 {
|
||||
regulator-min-microvolt = <3088000>;
|
||||
regulator-max-microvolt = <3088000>;
|
||||
|
|
@ -850,7 +856,6 @@ &spi0 {
|
|||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi0_default>;
|
||||
cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
|
||||
|
||||
can@0 {
|
||||
compatible = "microchip,mcp2517fd";
|
||||
|
|
@ -1156,6 +1161,7 @@ &wifi {
|
|||
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
|
||||
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
|
||||
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
|
||||
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
|
||||
|
||||
qcom,snoc-host-cap-8bit-quirk;
|
||||
qcom,calibration-variant = "Thundercomm_DB845C";
|
||||
|
|
|
|||
89
arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
Normal file
89
arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sdm845-google-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Pixel 3";
|
||||
compatible = "google,blueline", "qcom,sdm845";
|
||||
};
|
||||
|
||||
&battery {
|
||||
charge-full-design-microamp-hours = <2970000>;
|
||||
voltage-min-design-microvolt = <3600000>;
|
||||
voltage-max-design-microvolt = <4400000>;
|
||||
};
|
||||
|
||||
&framebuffer0 {
|
||||
width = <1080>;
|
||||
height = <2160>;
|
||||
stride = <(1080 * 4)>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <1000000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* ST,FTS @ 49 */
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-supply = <&vdda_mipi_dsi0_1p2>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
panel@0 {
|
||||
compatible = "lg,sw43408-lh546wf1-ed01", "lg,sw43408";
|
||||
reg = <0>;
|
||||
|
||||
vddi-supply = <&vreg_l14a_1p8>;
|
||||
vpnl-supply = <&vreg_l28a_3p0>;
|
||||
|
||||
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&panel_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_out {
|
||||
data-lanes = <0 1 2 3>;
|
||||
remote-endpoint = <&panel_in>;
|
||||
qcom,te-source = "mdp_vsync_e";
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
panel_default: panel-default-state {
|
||||
reset-pins {
|
||||
pins = "gpio6";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
te-pins {
|
||||
pins = "gpio12";
|
||||
function = "mdp_vsync";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wifi {
|
||||
qcom,calibration-variant = "Google_blueline";
|
||||
};
|
||||
536
arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
Normal file
536
arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
Normal file
|
|
@ -0,0 +1,536 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/arm/qcom,ids.h>
|
||||
#include <dt-bindings/dma/qcom-gpi.h>
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
|
||||
#include "sdm845.dtsi"
|
||||
#include "pm8998.dtsi"
|
||||
#include "pmi8998.dtsi"
|
||||
|
||||
/delete-node/ &mpss_region;
|
||||
/delete-node/ &venus_mem;
|
||||
/delete-node/ &cdsp_mem;
|
||||
/delete-node/ &mba_region;
|
||||
/delete-node/ &slpi_mem;
|
||||
/delete-node/ &spss_mem;
|
||||
/delete-node/ &rmtfs_mem;
|
||||
|
||||
/ {
|
||||
chassis-type = "handset";
|
||||
qcom,board-id = <0x00021505 0>;
|
||||
qcom,msm-id = <QCOM_ID_SDM845 0x20001>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart9;
|
||||
serial1 = &uart6;
|
||||
};
|
||||
|
||||
battery: battery {
|
||||
compatible = "simple-battery";
|
||||
};
|
||||
|
||||
chosen {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
stdout-path = "serial0:115200n8";
|
||||
|
||||
/* Use display framebuffer as setup by bootloader */
|
||||
framebuffer0: framebuffer-0 {
|
||||
compatible = "simple-framebuffer";
|
||||
memory-region = <&cont_splash_mem>;
|
||||
|
||||
format = "a8r8g8b8";
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
cont_splash_mem: splash@9d400000 {
|
||||
reg = <0 0x9d400000 0 0x02400000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mpss_region: memory@8e000000 {
|
||||
reg = <0 0x8e000000 0 0x9800000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
venus_mem: venus@97800000 {
|
||||
reg = <0 0x97800000 0 0x500000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
cdsp_mem: cdsp-mem@97D00000 {
|
||||
reg = <0 0x97D00000 0 0x800000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mba_region: mba@98500000 {
|
||||
reg = <0 0x98500000 0 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
slpi_mem: slpi@98700000 {
|
||||
reg = <0 0x98700000 0 0x1400000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
spss_mem: spss@99B00000 {
|
||||
reg = <0 0x99B00000 0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rmtfs_mem: rmtfs-region@f2700000 {
|
||||
compatible = "qcom,rmtfs-mem";
|
||||
reg = <0 0xf2700000 0 0x202000>;
|
||||
qcom,use-guard-pages;
|
||||
no-map;
|
||||
|
||||
qcom,client-id = <1>;
|
||||
qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
label = "Volume keys";
|
||||
autorepeat;
|
||||
|
||||
pinctrl-0 = <&volume_up_gpio>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
key-vol-up {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
|
||||
debounce-interval = <15>;
|
||||
};
|
||||
};
|
||||
|
||||
vph_pwr: regulator-vph-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
};
|
||||
|
||||
vreg_s4a_1p8: regulator-vreg-s4a-1p8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vreg_s4a_1p8";
|
||||
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
vin-supply = <&vph_pwr>;
|
||||
};
|
||||
};
|
||||
|
||||
&adsp_pas {
|
||||
firmware-name = "qcom/sdm845/Google/blueline/adsp.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
regulators-0 {
|
||||
compatible = "qcom,pm8998-rpmh-regulators";
|
||||
qcom,pmic-id = "a";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
vdd-s9-supply = <&vph_pwr>;
|
||||
vdd-s10-supply = <&vph_pwr>;
|
||||
vdd-s11-supply = <&vph_pwr>;
|
||||
vdd-s12-supply = <&vph_pwr>;
|
||||
vdd-s13-supply = <&vph_pwr>;
|
||||
vdd-l1-l27-supply = <&vreg_s7a_1p025>;
|
||||
vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
|
||||
vdd-l3-l11-supply = <&vreg_s7a_1p025>;
|
||||
vdd-l4-l5-supply = <&vreg_s7a_1p025>;
|
||||
vdd-l6-supply = <&vph_pwr>;
|
||||
vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
|
||||
vdd-l9-supply = <&vreg_bob>;
|
||||
vdd-l10-l23-l25-supply = <&vreg_bob>;
|
||||
vdd-l13-l19-l21-supply = <&vreg_bob>;
|
||||
vdd-l16-l28-supply = <&vreg_bob>;
|
||||
vdd-l18-l22-supply = <&vreg_bob>;
|
||||
vdd-l20-l24-supply = <&vreg_bob>;
|
||||
vdd-l26-supply = <&vreg_s3a_1p35>;
|
||||
vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
|
||||
|
||||
vreg_s3a_1p35: smps3 {
|
||||
regulator-min-microvolt = <1352000>;
|
||||
regulator-max-microvolt = <1352000>;
|
||||
};
|
||||
|
||||
vreg_s5a_2p04: smps5 {
|
||||
regulator-min-microvolt = <1904000>;
|
||||
regulator-max-microvolt = <2040000>;
|
||||
};
|
||||
|
||||
vreg_s7a_1p025: smps7 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1028000>;
|
||||
};
|
||||
|
||||
vdda_mipi_dsi0_pll:
|
||||
vreg_l1a_0p875: ldo1 {
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_l5a_0p8: ldo5 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l12a_1p8: ldo12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7a_1p8: ldo7 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l13a_2p95: ldo13 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l14a_1p8: ldo14 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-boot-on;
|
||||
/*
|
||||
* We can't properly bring the panel back if it gets turned off
|
||||
* so keep it's regulators always on for now.
|
||||
*/
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vreg_l17a_1p3: ldo17 {
|
||||
regulator-min-microvolt = <1304000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l19a_3p3: ldo19 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
/*
|
||||
* The touchscreen needs this to be 3.3v, which is apparently
|
||||
* quite close to the hardware limit for this LDO (3.312v)
|
||||
* It must be kept in high power mode to prevent TS brownouts
|
||||
*/
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l20a_2p95: ldo20 {
|
||||
regulator-min-microvolt = <2960000>;
|
||||
regulator-max-microvolt = <2968000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l21a_2p95: ldo21 {
|
||||
regulator-min-microvolt = <2960000>;
|
||||
regulator-max-microvolt = <2968000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l24a_3p075: ldo24 {
|
||||
regulator-min-microvolt = <3088000>;
|
||||
regulator-max-microvolt = <3088000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l25a_3p3: ldo25 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vdda_mipi_dsi0_1p2:
|
||||
vreg_l26a_1p2: ldo26 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_l28a_3p0: ldo28 {
|
||||
regulator-min-microvolt = <2856000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
regulator-boot-on;
|
||||
/*
|
||||
* We can't properly bring the panel back if it gets turned off
|
||||
* so keep it's regulators always on for now.
|
||||
*/
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-1 {
|
||||
compatible = "qcom,pmi8998-rpmh-regulators";
|
||||
qcom,pmic-id = "b";
|
||||
|
||||
vdd-bob-supply = <&vph_pwr>;
|
||||
|
||||
vreg_bob: bob {
|
||||
regulator-min-microvolt = <3312000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-bypass;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-2 {
|
||||
compatible = "qcom,pm8005-rpmh-regulators";
|
||||
qcom,pmic-id = "c";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s3c_0p6: smps3 {
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <600000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cci_i2c1 {
|
||||
/* actuator @0c */
|
||||
|
||||
/* front camera, imx355 @1a */
|
||||
|
||||
/* eeprom @50, at24 driver says 8K */
|
||||
};
|
||||
|
||||
&cdsp_pas {
|
||||
firmware-name = "qcom/sdm845/Google/blueline/cdsp.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
|
||||
};
|
||||
|
||||
&gpi_dma0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpi_dma1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/sdm845/Google/blueline/a630_zap.mbn";
|
||||
};
|
||||
|
||||
&i2c12 {
|
||||
/* Bottom spkr (right) CS35L36 @ 40 */
|
||||
|
||||
/* Top spkr (left) CS35L36 @ 41 */
|
||||
};
|
||||
|
||||
&ipa {
|
||||
firmware-name = "qcom/sdm845/Google/blueline/ipa_fws.mbn";
|
||||
memory-region = <&ipa_fw_mem>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mss_pil {
|
||||
firmware-name = "qcom/sdm845/Google/blueline/mba.mbn",
|
||||
"qcom/sdm845/Google/blueline/modem.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8998_gpios {
|
||||
volume_up_gpio: vol-up-active-state {
|
||||
pins = "gpio6";
|
||||
function = "normal";
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
qcom,drive-strength = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pm8998_resin {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmi8998_charger {
|
||||
monitored-battery = <&battery>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qup_uart9_rx {
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
&qup_uart9_tx {
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = < 0 4>, /* SPI (Intel MNH Pixel Visual Core) */
|
||||
<81 4>; /* SPI (most likely Fingerprint Cards FPC1075) */
|
||||
|
||||
touchscreen_reset: ts-reset-state {
|
||||
pins = "gpio99";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
touchscreen_pins: ts-pins-gpio-state {
|
||||
pins = "gpio125";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
touchscreen_i2c_pins: qup-i2c2-gpio-state {
|
||||
pins = "gpio27", "gpio28";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&uart6 {
|
||||
pinctrl-0 = <&qup_uart6_4pin>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "qcom,wcn3990-bt";
|
||||
|
||||
vddio-supply = <&vreg_s4a_1p8>;
|
||||
vddxo-supply = <&vreg_l7a_1p8>;
|
||||
vddrf-supply = <&vreg_l17a_1p3>;
|
||||
vddch0-supply = <&vreg_l25a_3p3>;
|
||||
max-speed = <3200000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart9 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_mem_hc {
|
||||
reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vcc-supply = <&vreg_l20a_2p95>;
|
||||
vcc-max-microamp = <800000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_mem_phy {
|
||||
vdda-phy-supply = <&vreg_l1a_0p875>;
|
||||
vdda-pll-supply = <&vreg_l26a_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_dwc3 {
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
vdd-supply = <&vreg_l1a_0p875>;
|
||||
vdda-pll-supply = <&vreg_l12a_1p8>;
|
||||
vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
|
||||
|
||||
qcom,imp-res-offset-value = <8>;
|
||||
qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
|
||||
qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
|
||||
qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_qmpphy {
|
||||
vdda-phy-supply = <&vreg_l26a_1p2>;
|
||||
vdda-pll-supply = <&vreg_l1a_0p875>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&venus {
|
||||
firmware-name = "qcom/sdm845/Google/blueline/venus.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
|
||||
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
|
||||
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
|
||||
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
|
||||
|
||||
qcom,snoc-host-cap-8bit-quirk;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
36
arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
Normal file
36
arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sdm845-google-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Pixel 3 XL";
|
||||
compatible = "google,crosshatch", "qcom,sdm845";
|
||||
};
|
||||
|
||||
&battery {
|
||||
charge-full-design-microamp-hours = <3480000>;
|
||||
voltage-min-design-microvolt = <3600000>;
|
||||
voltage-max-design-microvolt = <4400000>;
|
||||
};
|
||||
|
||||
&dispcc {
|
||||
/* Disable for now so simple-framebuffer continues working */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&framebuffer0 {
|
||||
width = <1440>;
|
||||
height = <2960>;
|
||||
stride = <(1440 * 4)>;
|
||||
};
|
||||
|
||||
&mdss {
|
||||
/* Disable for now so simple-framebuffer continues working */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
qcom,calibration-variant = "Google_crosshatch";
|
||||
};
|
||||
|
|
@ -31,7 +31,20 @@ aliases {
|
|||
};
|
||||
|
||||
chosen {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
stdout-path = "serial0:115200n8";
|
||||
|
||||
framebuffer: framebuffer@9d400000 {
|
||||
compatible = "simple-framebuffer";
|
||||
memory-region = <&cont_splash_mem>;
|
||||
|
||||
format = "a8r8g8b8";
|
||||
stride = <(1080 * 4)>;
|
||||
width = <1080>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-hall-sensor {
|
||||
|
|
@ -75,6 +88,11 @@ key-vol-up {
|
|||
};
|
||||
|
||||
reserved-memory {
|
||||
cont_splash_mem: splash@9d400000 {
|
||||
reg = <0 0x9d400000 0 0x02400000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
/*
|
||||
* The rmtfs memory region in downstream is 'dynamically allocated'
|
||||
* but given the same address every time. Hard code it as this address is
|
||||
|
|
@ -148,7 +166,6 @@ ts_1p8_supply: ts-1p8-regulator {
|
|||
|
||||
gpio = <&tlmm 88 0>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
panel_vci_3v3: panel-vci-3v3-regulator {
|
||||
|
|
@ -181,8 +198,9 @@ panel_vddi_poc_1p8: panel-vddi-poc-regulator {
|
|||
};
|
||||
|
||||
&adsp_pas {
|
||||
firmware-name = "qcom/sdm845/OnePlus/enchilada/adsp.mbn";
|
||||
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/oneplus6/adsp.mbn";
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
|
|
@ -273,7 +291,7 @@ vreg_l14a_1p88: ldo14 {
|
|||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_l17a_1p3: ldo17 {
|
||||
|
|
@ -353,8 +371,9 @@ vreg_s3c_0p6: smps3 {
|
|||
};
|
||||
|
||||
&cdsp_pas {
|
||||
firmware-name = "qcom/sdm845/OnePlus/enchilada/cdsp.mbn";
|
||||
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/oneplus6/cdsp.mbn";
|
||||
};
|
||||
|
||||
&gcc {
|
||||
|
|
@ -370,7 +389,7 @@ &gpu {
|
|||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/sdm845/oneplus6/a630_zap.mbn";
|
||||
firmware-name = "qcom/sdm845/OnePlus/enchilada/a630_zap.mbn";
|
||||
};
|
||||
|
||||
&i2c10 {
|
||||
|
|
@ -422,7 +441,8 @@ rmi4_f12: rmi4-f12@12 {
|
|||
&ipa {
|
||||
qcom,gsi-loader = "self";
|
||||
memory-region = <&ipa_fw_mem>;
|
||||
firmware-name = "qcom/sdm845/oneplus6/ipa_fws.mbn";
|
||||
firmware-name = "qcom/sdm845/OnePlus/enchilada/ipa_fws.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -474,8 +494,10 @@ &mdss_dsi0_phy {
|
|||
|
||||
/* Modem/wifi */
|
||||
&mss_pil {
|
||||
firmware-name = "qcom/sdm845/OnePlus/enchilada/mba.mbn",
|
||||
"qcom/sdm845/OnePlus/enchilada/modem.mbn";
|
||||
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/oneplus6/mba.mbn", "qcom/sdm845/oneplus6/modem.mbn";
|
||||
};
|
||||
|
||||
&pm8998_gpios {
|
||||
|
|
@ -593,7 +615,8 @@ &qup_uart9_tx {
|
|||
};
|
||||
|
||||
&slpi_pas {
|
||||
firmware-name = "qcom/sdm845/oneplus6/slpi.mbn";
|
||||
firmware-name = "qcom/sdm845/OnePlus/enchilada/slpi.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -744,7 +767,7 @@ bluetooth {
|
|||
* This path is relative to the qca/
|
||||
* subdir under lib/firmware.
|
||||
*/
|
||||
firmware-name = "oneplus6/crnv21.bin";
|
||||
firmware-name = "OnePlus/enchilada/crnv21.bin";
|
||||
|
||||
vddio-supply = <&vreg_s4a_1p8>;
|
||||
vddxo-supply = <&vreg_l7a_1p8>;
|
||||
|
|
@ -906,8 +929,9 @@ speaker_default: speaker-default-state {
|
|||
};
|
||||
|
||||
&venus {
|
||||
firmware-name = "qcom/sdm845/OnePlus/enchilada/venus.mbn";
|
||||
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/oneplus6/venus.mbn";
|
||||
};
|
||||
|
||||
&wcd9340 {
|
||||
|
|
@ -929,5 +953,6 @@ &wifi {
|
|||
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
|
||||
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
|
||||
|
||||
qcom,calibration-variant = "oneplus_sdm845";
|
||||
qcom,snoc-host-cap-8bit-quirk;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -30,14 +30,18 @@ battery: battery {
|
|||
};
|
||||
};
|
||||
|
||||
&bq27441_fg {
|
||||
monitored-battery = <&battery>;
|
||||
};
|
||||
|
||||
&display_panel {
|
||||
status = "okay";
|
||||
|
||||
compatible = "samsung,sofef00";
|
||||
};
|
||||
|
||||
&bq27441_fg {
|
||||
monitored-battery = <&battery>;
|
||||
&framebuffer {
|
||||
height = <2280>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
|
|
|
|||
|
|
@ -35,6 +35,10 @@ &display_panel {
|
|||
compatible = "samsung,s6e3fc2x01-ams641rw", "samsung,s6e3fc2x01";
|
||||
};
|
||||
|
||||
&framebuffer {
|
||||
height = <2340>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
/* nxp,tfa9894 @ 0x34 */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -254,7 +254,7 @@ &gpu {
|
|||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/sdm845/starqltechn/a630_zap.mbn";
|
||||
firmware-name = "qcom/sdm845/Samsung/starqltechn/a630_zap.mbn";
|
||||
};
|
||||
|
||||
&mdss {
|
||||
|
|
@ -699,7 +699,8 @@ touchscreen@48 {
|
|||
};
|
||||
|
||||
&adsp_pas {
|
||||
firmware-name = "qcom/sdm845/starqltechn/adsp.mbn";
|
||||
firmware-name = "qcom/sdm845/Samsung/starqltechn/adsp.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -904,20 +905,22 @@ &wcd9340 {
|
|||
};
|
||||
|
||||
&mss_pil {
|
||||
firmware-name = "qcom/sdm845/starqltechn/mba.mbn",
|
||||
"qcom/sdm845/starqltechn/modem.mbn";
|
||||
firmware-name = "qcom/sdm845/Samsung/starqltechn/mba.mbn",
|
||||
"qcom/sdm845/Samsung/starqltechn/modem.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ipa {
|
||||
qcom,gsi-loader = "self";
|
||||
memory-region = <&ipa_fw_mem>;
|
||||
firmware-name = "qcom/sdm845/starqltechn/ipa_fws.mbn";
|
||||
firmware-name = "qcom/sdm845/Samsung/starqltechn/ipa_fws.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&slpi_pas {
|
||||
firmware-name = "qcom/sdm845/starqltechn/slpi.mbn";
|
||||
firmware-name = "qcom/sdm845/Samsung/starqltechn/slpi.mbn";
|
||||
cx-supply = <&slpi_regulator>;
|
||||
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -108,8 +108,9 @@ vreg_s4a_1p8: pm8998-smps4 {
|
|||
};
|
||||
|
||||
&adsp_pas {
|
||||
firmware-name = "qcom/sdm845/SHIFT/axolotl/adsp.mbn";
|
||||
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/axolotl/adsp.mbn";
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
|
|
@ -409,8 +410,9 @@ vreg_s3c_0p6: smps3 {
|
|||
};
|
||||
|
||||
&cdsp_pas {
|
||||
firmware-name = "qcom/sdm845/SHIFT/axolotl/cdsp.mbn";
|
||||
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/axolotl/cdsp.mbn";
|
||||
};
|
||||
|
||||
&gcc {
|
||||
|
|
@ -426,7 +428,7 @@ &gpu {
|
|||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/sdm845/axolotl/a630_zap.mbn";
|
||||
firmware-name = "qcom/sdm845/SHIFT/axolotl/a630_zap.mbn";
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
|
|
@ -458,7 +460,8 @@ &i2c10 {
|
|||
&ipa {
|
||||
qcom,gsi-loader = "self";
|
||||
memory-region = <&ipa_fw_mem>;
|
||||
firmware-name = "qcom/sdm845/axolotl/ipa_fws.mbn";
|
||||
firmware-name = "qcom/sdm845/SHIFT/axolotl/ipa_fws.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -502,8 +505,9 @@ &mdss_dsi0_phy {
|
|||
};
|
||||
|
||||
&mss_pil {
|
||||
firmware-name = "qcom/sdm845/SHIFT/axolotl/mba.mbn", "qcom/sdm845/SHIFT/axolotl/modem.mbn";
|
||||
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/axolotl/mba.mbn", "qcom/sdm845/axolotl/modem.mbn";
|
||||
};
|
||||
|
||||
&pm8998_gpios {
|
||||
|
|
@ -597,7 +601,8 @@ &qupv3_id_1 {
|
|||
};
|
||||
|
||||
&slpi_pas {
|
||||
firmware-name = "qcom/sdm845/axolotl/slpi.mbn";
|
||||
firmware-name = "qcom/sdm845/SHIFT/axolotl/slpi.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -673,7 +678,7 @@ bluetooth {
|
|||
* This path is relative to the qca/
|
||||
* subdir under lib/firmware.
|
||||
*/
|
||||
firmware-name = "axolotl/crnv21.bin";
|
||||
firmware-name = "SHIFT/axolotl/crnv21.bin";
|
||||
|
||||
vddio-supply = <&vreg_s4a_1p8>;
|
||||
vddxo-supply = <&vreg_l7a_1p8>;
|
||||
|
|
@ -727,8 +732,9 @@ &usb_1_qmpphy {
|
|||
};
|
||||
|
||||
&venus {
|
||||
firmware-name = "qcom/sdm845/SHIFT/axolotl/venus.mbn";
|
||||
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/axolotl/venus.mbn";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
|
|
@ -740,5 +746,6 @@ &wifi {
|
|||
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
|
||||
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
|
||||
|
||||
qcom,calibration-variant = "shift_axolotl";
|
||||
qcom,snoc-host-cap-8bit-quirk;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -136,7 +136,7 @@ vreg_s4a_1p8: vreg-s4a-1p8 {
|
|||
|
||||
&adsp_pas {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/beryllium/adsp.mbn";
|
||||
firmware-name = "qcom/sdm845/Xiaomi/beryllium/adsp.mbn";
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
|
|
@ -227,9 +227,15 @@ vreg_l26a_1p2: ldo26 {
|
|||
};
|
||||
};
|
||||
|
||||
&cci_i2c0 {
|
||||
status = "okay";
|
||||
|
||||
/* IMX363 @ 10 */
|
||||
};
|
||||
|
||||
&cdsp_pas {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/beryllium/cdsp.mbn";
|
||||
firmware-name = "qcom/sdm845/Xiaomi/beryllium/cdsp.mbn";
|
||||
};
|
||||
|
||||
&gcc {
|
||||
|
|
@ -249,7 +255,7 @@ &gpu {
|
|||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/sdm845/beryllium/a630_zap.mbn";
|
||||
firmware-name = "qcom/sdm845/Xiaomi/beryllium/a630_zap.mbn";
|
||||
};
|
||||
|
||||
&ibb {
|
||||
|
|
@ -261,6 +267,22 @@ &ibb {
|
|||
qcom,discharge-resistor-kohms = <300>;
|
||||
};
|
||||
|
||||
&ipa {
|
||||
qcom,gsi-loader = "self";
|
||||
memory-region = <&ipa_fw_mem>;
|
||||
firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* TAS2559 @ 4C */
|
||||
};
|
||||
|
||||
&lab {
|
||||
regulator-min-microvolt = <4600000>;
|
||||
regulator-max-microvolt = <6000000>;
|
||||
|
|
@ -308,14 +330,8 @@ &mdss_dsi0_phy {
|
|||
|
||||
&mss_pil {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/beryllium/mba.mbn", "qcom/sdm845/beryllium/modem.mbn";
|
||||
};
|
||||
|
||||
&ipa {
|
||||
qcom,gsi-loader = "self";
|
||||
memory-region = <&ipa_fw_mem>;
|
||||
firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn";
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/Xiaomi/beryllium/mba.mbn",
|
||||
"qcom/sdm845/Xiaomi/beryllium/modem.mbn";
|
||||
};
|
||||
|
||||
&pm8998_gpios {
|
||||
|
|
@ -425,6 +441,12 @@ &sdhc_2 {
|
|||
cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&slpi_pas {
|
||||
firmware-name = "qcom/sdm845/Xiaomi/beryllium/slpi.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sound {
|
||||
compatible = "qcom,db845c-sndcard", "qcom,sdm845-sndcard";
|
||||
pinctrl-0 = <&quat_mi2s_active
|
||||
|
|
@ -612,7 +634,7 @@ &usb_1_qmpphy {
|
|||
|
||||
&venus {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/beryllium/venus.mbn";
|
||||
firmware-name = "qcom/sdm845/Xiaomi/beryllium/venus.mbn";
|
||||
};
|
||||
|
||||
&wcd9340 {
|
||||
|
|
@ -636,4 +658,7 @@ &wifi {
|
|||
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
|
||||
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
|
||||
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
|
||||
|
||||
qcom,calibration-variant = "xiaomi_beryllium";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -370,7 +370,8 @@ vreg_smp3c_0p6: smps3 {
|
|||
};
|
||||
|
||||
&cdsp_pas {
|
||||
firmware-name = "qcom/sdm845/polaris/cdsp.mbn";
|
||||
firmware-name = "qcom/sdm845/Xiaomi/polaris/cdsp.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -395,7 +396,7 @@ &gpu {
|
|||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/sdm845/polaris/a630_zap.mbn";
|
||||
firmware-name = "qcom/sdm845/Xiaomi/polaris/a630_zap.mbn";
|
||||
};
|
||||
|
||||
&ibb {
|
||||
|
|
@ -410,7 +411,8 @@ &ibb {
|
|||
&ipa {
|
||||
qcom,gsi-loader = "self";
|
||||
memory-region = <&ipa_fw_mem>;
|
||||
firmware-name = "qcom/sdm845/polaris/ipa_fws.mbn";
|
||||
firmware-name = "qcom/sdm845/Xiaomi/polaris/ipa_fws.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -502,7 +504,9 @@ &mdss_dsi0_phy {
|
|||
};
|
||||
|
||||
&mss_pil {
|
||||
firmware-name = "qcom/sdm845/polaris/mba.mbn", "qcom/sdm845/polaris/modem.mbn";
|
||||
firmware-name = "qcom/sdm845/Xiaomi/polaris/mba.mbn",
|
||||
"qcom/sdm845/Xiaomi/polaris/modem.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -623,7 +627,7 @@ bluetooth {
|
|||
compatible = "qcom,wcn3990-bt";
|
||||
|
||||
/* This path is relative to the qca/ subdir under lib/firmware. */
|
||||
firmware-name = "polaris/crnv21.bin";
|
||||
firmware-name = "Xiaomi/polaris/crnv21.bin";
|
||||
|
||||
vddio-supply = <&vreg_s4a_1p8>;
|
||||
vddxo-supply = <&vreg_l7a_1p8>;
|
||||
|
|
@ -683,7 +687,8 @@ &ufs_mem_phy {
|
|||
};
|
||||
|
||||
&venus {
|
||||
firmware-name = "qcom/sdm845/polaris/venus.mbn";
|
||||
firmware-name = "qcom/sdm845/Xiaomi/polaris/venus.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -30,9 +30,7 @@
|
|||
/delete-node/ &ipa_fw_mem;
|
||||
/delete-node/ &ipa_gsi_mem;
|
||||
/delete-node/ &gpu_mem;
|
||||
/delete-node/ &adsp_mem;
|
||||
/delete-node/ &wlan_msa_mem;
|
||||
/delete-node/ &slpi_mem;
|
||||
|
||||
/ {
|
||||
model = "Huawei MateBook E 2019";
|
||||
|
|
@ -145,22 +143,13 @@ wlan_msa_mem: wlan-msa@8c400000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
adsp_mem: adsp@8c500000 {
|
||||
reg = <0 0x8c500000 0 0x1a00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
ipa_fw_mem: ipa-fw@8df00000 {
|
||||
reg = <0 0x8df00000 0 0x100000>;
|
||||
reg = <0 0x8df00000 0 0x5a000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
slpi_mem: slpi@96700000 {
|
||||
reg = <0 0x96700000 0 0x1200000>;
|
||||
};
|
||||
|
||||
gpu_mem: gpu@97900000 {
|
||||
reg = <0 0x97900000 0 0x5000>;
|
||||
gpu_mem: gpu@8df5a000 {
|
||||
reg = <0 0x8df5a000 0 0x5000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -870,7 +870,7 @@ cryptobam: dma-controller@1b04000 {
|
|||
<&apps_smmu 0x94 0x11>,
|
||||
<&apps_smmu 0x96 0x11>,
|
||||
<&apps_smmu 0x98 0x1>,
|
||||
<&apps_smmu 0x9F 0>;
|
||||
<&apps_smmu 0x9f 0>;
|
||||
};
|
||||
|
||||
crypto: crypto@1b3a000 {
|
||||
|
|
@ -885,7 +885,7 @@ crypto: crypto@1b3a000 {
|
|||
<&apps_smmu 0x94 0x11>,
|
||||
<&apps_smmu 0x96 0x11>,
|
||||
<&apps_smmu 0x98 0x1>,
|
||||
<&apps_smmu 0x9F 0>;
|
||||
<&apps_smmu 0x9f 0>;
|
||||
};
|
||||
|
||||
usb_qmpphy: phy@1615000 {
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ / {
|
|||
chassis-type = "handset";
|
||||
|
||||
/* required for bootloader to select correct board */
|
||||
qcom,msm-id = <QCOM_ID_SM6125>;
|
||||
qcom,msm-id = <QCOM_ID_SM6125 0x10000>;
|
||||
qcom,board-id = <22 0>;
|
||||
|
||||
chosen {
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ / {
|
|||
compatible = "sony,pdx213", "qcom,sm6350";
|
||||
chassis-type = "handset";
|
||||
qcom,msm-id = <434 0x10000>, <459 0x10000>;
|
||||
qcom,board-id = <0x1000B 0>;
|
||||
qcom,board-id = <0x1000b 0>;
|
||||
|
||||
chosen {
|
||||
#address-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -246,6 +246,46 @@ active-config0 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
vreg_32m_cam_dvdd_1p05: regulator-32m-cam-dvdd-1p05 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "32M_CAM_DVDD_1P05";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
gpio = <&pm6150l_gpios 2 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
vin-supply = <&vreg_s8e>;
|
||||
};
|
||||
|
||||
vreg_48m_ois_avdd0_1p8: regulator-48m-ois-avdd0-1p8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "48M_OIS_AVDD0_1P8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
gpio = <&pm6150l_gpios 4 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
vin-supply = <&vreg_bob>;
|
||||
};
|
||||
|
||||
vreg_48m_uw_avdd0_1p8: regulator-48m-uw-avdd0-1p8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "48M_UW_AVDD0_1P8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
gpio = <&pm6150l_gpios 3 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
vin-supply = <&vreg_bob>;
|
||||
};
|
||||
|
||||
vreg_ois_2p8: regulator-ois-2p8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "OIS_2P8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
vin-supply = <&vreg_bob>;
|
||||
};
|
||||
};
|
||||
|
||||
&adsp {
|
||||
|
|
@ -512,11 +552,28 @@ &cci0 {
|
|||
};
|
||||
|
||||
&cci0_i2c0 {
|
||||
/* IMX582 @ 0x1a */
|
||||
/* Main cam (Sony IMX582) @ 0x1a */
|
||||
/* VCM driver (Onsemi LC898219XI) @ 0x28 */
|
||||
/* OIS driver (CML CM401) @ 0x30 */
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "giantec,gt24p128e", "atmel,24c128";
|
||||
reg = <0x50>;
|
||||
vcc-supply = <&vreg_l6p>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
&cci0_i2c1 {
|
||||
/* IMX582 @ 0x1a */
|
||||
/* VCM driver (Dongwoon DW9800W) @ 0xc */
|
||||
/* Ultra-wide cam (Sony IMX582) @ 0x1a */
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "giantec,gt24p64a", "atmel,24c64";
|
||||
reg = <0x50>;
|
||||
vcc-supply = <&vreg_l6p>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
&cci1 {
|
||||
|
|
@ -524,7 +581,14 @@ &cci1 {
|
|||
};
|
||||
|
||||
&cci1_i2c0 {
|
||||
/* IMX576 @ 0x10 */
|
||||
/* Front cam (Sony IMX576) @ 0x10 */
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "giantec,gt24p64a", "atmel,24c64";
|
||||
reg = <0x50>;
|
||||
vcc-supply = <&vreg_l6p>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
&cdsp {
|
||||
|
|
@ -629,6 +693,8 @@ vreg_l6p: ldo6 {
|
|||
regulator-name = "vreg_l6p";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
/* Pull-up for CCI I2C busses */
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vreg_l7p: ldo7 {
|
||||
|
|
|
|||
|
|
@ -387,6 +387,10 @@ &gpu {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/sm8150/a640_zap.mbn";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -358,6 +358,10 @@ &gpu {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/sm8150/a640_zap.mbn";
|
||||
};
|
||||
|
||||
&pon {
|
||||
mode-bootloader = <0x2>;
|
||||
mode-recovery = <0x1>;
|
||||
|
|
|
|||
|
|
@ -1693,6 +1693,15 @@ spi13: spi@c8c000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart13: serial@c8c000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00c8c000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c14: i2c@c90000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00c90000 0 0x4000>;
|
||||
|
|
@ -2381,7 +2390,7 @@ tlmm: pinctrl@3100000 {
|
|||
reg = <0x0 0x03100000 0x0 0x300000>,
|
||||
<0x0 0x03500000 0x0 0x300000>,
|
||||
<0x0 0x03900000 0x0 0x300000>,
|
||||
<0x0 0x03D00000 0x0 0x300000>;
|
||||
<0x0 0x03d00000 0x0 0x300000>;
|
||||
reg-names = "west", "east", "north", "south";
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-ranges = <&tlmm 0 0 176>;
|
||||
|
|
|
|||
|
|
@ -373,6 +373,10 @@ &gpu {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/sm8250/a650_zap.mbn";
|
||||
};
|
||||
|
||||
&pon {
|
||||
mode-bootloader = <0x2>;
|
||||
mode-recovery = <0x1>;
|
||||
|
|
|
|||
|
|
@ -52,14 +52,13 @@ sensor@10 {
|
|||
pinctrl-0 = <&cam3_default>;
|
||||
pinctrl-names = "default";
|
||||
afvdd-supply = <&vreg_l7n_2p96>;
|
||||
avdd-supply = <&vreg_l4m_2p8>;
|
||||
dovdd-supply = <&vreg_l5n_1p8>;
|
||||
dvdd-supply = <&vreg_l2m_1p056>;
|
||||
vdda-supply = <&vreg_l4m_2p8>;
|
||||
vddd-supply = <&vreg_l2m_1p056>;
|
||||
vddio-supply = <&vreg_l5n_1p8>;
|
||||
|
||||
port {
|
||||
cam_tele: endpoint {
|
||||
link-frequencies = /bits/ 64 <602500000>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
remote-endpoint = <&csiphy3_ep>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1107,6 +1107,22 @@ &pm8550b_eusb2_repeater {
|
|||
vdd3-supply = <&vreg_l5b_3p1>;
|
||||
};
|
||||
|
||||
&pm8550vs_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_d {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_e {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_g {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -789,6 +789,22 @@ &pm8550b_eusb2_repeater {
|
|||
vdd3-supply = <&vreg_l5b_3p1>;
|
||||
};
|
||||
|
||||
&pm8550vs_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_d {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_e {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_g {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -748,14 +748,13 @@ sensor@10 {
|
|||
pinctrl-0 = <&cam3_default>;
|
||||
pinctrl-names = "default";
|
||||
afvdd-supply = <&vreg_l7n_2p96>;
|
||||
avdd-supply = <&vreg_l4m_2p8>;
|
||||
dovdd-supply = <&vreg_l5n_1p8>;
|
||||
dvdd-supply = <&vreg_l2m_1p056>;
|
||||
vdda-supply = <&vreg_l4m_2p8>;
|
||||
vddd-supply = <&vreg_l2m_1p056>;
|
||||
vddio-supply = <&vreg_l5n_1p8>;
|
||||
|
||||
port {
|
||||
cam_tele: endpoint {
|
||||
link-frequencies = /bits/ 64 <602500000>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
remote-endpoint = <&csiphy3_ep>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1003,6 +1002,22 @@ &pm8550b_eusb2_repeater {
|
|||
vdd3-supply = <&vreg_l5b_3p1>;
|
||||
};
|
||||
|
||||
&pm8550vs_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_d {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_e {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_g {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -533,6 +533,22 @@ volume_up_n: volume-up-n-state {
|
|||
};
|
||||
};
|
||||
|
||||
&pm8550vs_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_d {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_e {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_g {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -661,6 +661,22 @@ focus_n: focus-n-state {
|
|||
};
|
||||
};
|
||||
|
||||
&pm8550vs_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_d {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_e {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_g {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_g_gpios {
|
||||
cam_pwr_a_cs: cam-pwr-a-cs-state {
|
||||
pins = "gpio4";
|
||||
|
|
|
|||
88
arch/arm64/boot/dts/qcom/sm8650-hdk-rear-camera-card.dtso
Normal file
88
arch/arm64/boot/dts/qcom/sm8650-hdk-rear-camera-card.dtso
Normal file
|
|
@ -0,0 +1,88 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* SM8650-HDK Rear Camera Card overlay
|
||||
*
|
||||
* Copyright (c) 2025, Linaro Limited
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/qcom,sm8650-camcc.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&camss {
|
||||
vdd-csiphy35-0p9-supply = <&vreg_l2i_0p88>;
|
||||
vdd-csiphy35-1p2-supply = <&vreg_l3i_1p2>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
|
||||
csiphy3_ep: endpoint {
|
||||
data-lanes = <0 1 2 3>;
|
||||
remote-endpoint = <&cam_tele>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cci1_i2c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sensor@56 {
|
||||
compatible = "samsung,s5kjn1";
|
||||
reg = <0x56>;
|
||||
clocks = <&camcc CAM_CC_MCLK3_CLK>;
|
||||
assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
reset-gpios = <&tlmm 109 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&cam3_default>;
|
||||
pinctrl-names = "default";
|
||||
afvdd-supply = <&vreg_l7m_2p96>;
|
||||
vdda-supply = <&vreg_l4m_2p8>;
|
||||
vddd-supply = <&vreg_l2m_1p056>;
|
||||
vddio-supply = <&vreg_l3n_1p8>;
|
||||
|
||||
port {
|
||||
cam_tele: endpoint {
|
||||
link-frequencies = /bits/ 64 <700000000>;
|
||||
remote-endpoint = <&csiphy3_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pm8550_flash {
|
||||
status = "okay";
|
||||
|
||||
led-0 {
|
||||
function = LED_FUNCTION_FLASH;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
led-sources = <1>, <4>;
|
||||
led-max-microamp = <500000>;
|
||||
flash-max-microamp = <2000000>;
|
||||
flash-max-timeout-us = <1280000>;
|
||||
function-enumerator = <0>;
|
||||
};
|
||||
|
||||
led-1 {
|
||||
function = LED_FUNCTION_FLASH;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
led-sources = <2>, <3>;
|
||||
led-max-microamp = <500000>;
|
||||
flash-max-microamp = <2000000>;
|
||||
flash-max-timeout-us = <1280000>;
|
||||
function-enumerator = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1046,6 +1046,22 @@ &pm8550b_eusb2_repeater {
|
|||
vdd3-supply = <&vreg_l5b_3p1>;
|
||||
};
|
||||
|
||||
&pm8550vs_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_d {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_e {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_g {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -692,6 +692,22 @@ &pm8550b_eusb2_repeater {
|
|||
vdd3-supply = <&vreg_l5b_3p1>;
|
||||
};
|
||||
|
||||
&pm8550vs_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_d {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_e {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_g {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -741,6 +741,49 @@ vreg_l7n_3p3: ldo7 {
|
|||
};
|
||||
};
|
||||
|
||||
&camss {
|
||||
vdd-csiphy35-0p9-supply = <&vreg_l2i_0p88>;
|
||||
vdd-csiphy35-1p2-supply = <&vreg_l3i_1p2>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@3 {
|
||||
csiphy3_ep: endpoint {
|
||||
data-lanes = <0 1 2 3>;
|
||||
remote-endpoint = <&cam_tele>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cci1_i2c0 {
|
||||
sensor@56 {
|
||||
compatible = "samsung,s5kjn1";
|
||||
reg = <0x56>;
|
||||
clocks = <&camcc CAM_CC_MCLK3_CLK>;
|
||||
assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
reset-gpios = <&tlmm 109 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&cam3_default>;
|
||||
pinctrl-names = "default";
|
||||
afvdd-supply = <&vreg_l7m_2p96>;
|
||||
vdda-supply = <&vreg_l4m_2p8>;
|
||||
vddd-supply = <&vreg_l2m_1p056>;
|
||||
vddio-supply = <&vreg_l3n_1p8>;
|
||||
|
||||
port {
|
||||
cam_tele: endpoint {
|
||||
link-frequencies = /bits/ 64 <700000000>;
|
||||
remote-endpoint = <&csiphy3_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpi_dma1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1002,6 +1045,22 @@ &pm8550b_eusb2_repeater {
|
|||
vdd3-supply = <&vreg_l5b_3p1>;
|
||||
};
|
||||
|
||||
&pm8550vs_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_d {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_e {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550vs_g {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qup_i2c3_data_clk {
|
||||
/* Use internal I2C pull-up */
|
||||
bias-pull-up = <2200>;
|
||||
|
|
|
|||
|
|
@ -5380,6 +5380,193 @@ cci2_i2c1: i2c-bus@1 {
|
|||
};
|
||||
};
|
||||
|
||||
camss: isp@acb6000 {
|
||||
compatible = "qcom,sm8650-camss";
|
||||
|
||||
reg = <0 0x0acb6000 0 0x1000>,
|
||||
<0 0x0acb8000 0 0x1000>,
|
||||
<0 0x0acba000 0 0x1000>,
|
||||
<0 0x0acbc000 0 0x1000>,
|
||||
<0 0x0accb000 0 0x1000>,
|
||||
<0 0x0acd0000 0 0x1000>,
|
||||
<0 0x0ace4000 0 0x2000>,
|
||||
<0 0x0ace6000 0 0x2000>,
|
||||
<0 0x0ace8000 0 0x2000>,
|
||||
<0 0x0acea000 0 0x2000>,
|
||||
<0 0x0acec000 0 0x2000>,
|
||||
<0 0x0acee000 0 0x2000>,
|
||||
<0 0x0ac62000 0 0xf000>,
|
||||
<0 0x0ac71000 0 0xf000>,
|
||||
<0 0x0ac80000 0 0xf000>,
|
||||
<0 0x0accc000 0 0x2000>,
|
||||
<0 0x0acd1000 0 0x2000>;
|
||||
reg-names = "csid_wrapper",
|
||||
"csid0",
|
||||
"csid1",
|
||||
"csid2",
|
||||
"csid_lite0",
|
||||
"csid_lite1",
|
||||
"csiphy0",
|
||||
"csiphy1",
|
||||
"csiphy2",
|
||||
"csiphy3",
|
||||
"csiphy4",
|
||||
"csiphy5",
|
||||
"vfe0",
|
||||
"vfe1",
|
||||
"vfe2",
|
||||
"vfe_lite0",
|
||||
"vfe_lite1";
|
||||
|
||||
clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
|
||||
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
||||
<&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
|
||||
<&camcc CAM_CC_CPAS_IFE_0_CLK>,
|
||||
<&camcc CAM_CC_CPAS_IFE_1_CLK>,
|
||||
<&camcc CAM_CC_CPAS_IFE_2_CLK>,
|
||||
<&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
|
||||
<&camcc CAM_CC_CSID_CLK>,
|
||||
<&camcc CAM_CC_CSIPHY0_CLK>,
|
||||
<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
|
||||
<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
|
||||
<&camcc CAM_CC_CSIPHY1_CLK>,
|
||||
<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
|
||||
<&camcc CAM_CC_CSIPHY2_CLK>,
|
||||
<&camcc CAM_CC_CSI3PHYTIMER_CLK>,
|
||||
<&camcc CAM_CC_CSIPHY3_CLK>,
|
||||
<&camcc CAM_CC_CSI4PHYTIMER_CLK>,
|
||||
<&camcc CAM_CC_CSIPHY4_CLK>,
|
||||
<&camcc CAM_CC_CSI5PHYTIMER_CLK>,
|
||||
<&camcc CAM_CC_CSIPHY5_CLK>,
|
||||
<&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
|
||||
<&gcc GCC_CAMERA_HF_AXI_CLK>,
|
||||
<&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
|
||||
<&camcc CAM_CC_IFE_0_CLK>,
|
||||
<&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
|
||||
<&camcc CAM_CC_IFE_1_CLK>,
|
||||
<&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
|
||||
<&camcc CAM_CC_IFE_2_CLK>,
|
||||
<&camcc CAM_CC_IFE_2_FAST_AHB_CLK>,
|
||||
<&camcc CAM_CC_IFE_LITE_CLK>,
|
||||
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
|
||||
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
|
||||
<&camcc CAM_CC_IFE_LITE_CSID_CLK>;
|
||||
clock-names = "camnoc_axi",
|
||||
"cpas_ahb",
|
||||
"cpas_fast_ahb",
|
||||
"cpas_vfe0",
|
||||
"cpas_vfe1",
|
||||
"cpas_vfe2",
|
||||
"cpas_vfe_lite",
|
||||
"csid",
|
||||
"csiphy0",
|
||||
"csiphy0_timer",
|
||||
"csiphy1",
|
||||
"csiphy1_timer",
|
||||
"csiphy2",
|
||||
"csiphy2_timer",
|
||||
"csiphy3",
|
||||
"csiphy3_timer",
|
||||
"csiphy4",
|
||||
"csiphy4_timer",
|
||||
"csiphy5",
|
||||
"csiphy5_timer",
|
||||
"csiphy_rx",
|
||||
"gcc_axi_hf",
|
||||
"qdss_debug_xo",
|
||||
"vfe0",
|
||||
"vfe0_fast_ahb",
|
||||
"vfe1",
|
||||
"vfe1_fast_ahb",
|
||||
"vfe2",
|
||||
"vfe2_fast_ahb",
|
||||
"vfe_lite",
|
||||
"vfe_lite_ahb",
|
||||
"vfe_lite_cphy_rx",
|
||||
"vfe_lite_csid";
|
||||
|
||||
interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 603 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 431 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 605 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 376 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 122 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 89 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 602 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 604 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 688 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 606 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<GIC_SPI 377 IRQ_TYPE_EDGE_RISING 0>;
|
||||
interrupt-names = "csid0",
|
||||
"csid1",
|
||||
"csid2",
|
||||
"csid_lite0",
|
||||
"csid_lite1",
|
||||
"csiphy0",
|
||||
"csiphy1",
|
||||
"csiphy2",
|
||||
"csiphy3",
|
||||
"csiphy4",
|
||||
"csiphy5",
|
||||
"vfe0",
|
||||
"vfe1",
|
||||
"vfe2",
|
||||
"vfe_lite0",
|
||||
"vfe_lite1";
|
||||
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC 0
|
||||
&config_noc SLAVE_CAMERA_CFG 0>,
|
||||
<&mmss_noc MASTER_CAMNOC_HF 0
|
||||
&mc_virt SLAVE_EBI1 0>;
|
||||
interconnect-names = "ahb",
|
||||
"hf_mnoc";
|
||||
|
||||
iommus = <&apps_smmu 0x800 0x20>,
|
||||
<&apps_smmu 0x18a0 0x40>,
|
||||
<&apps_smmu 0x1860 0x00>;
|
||||
|
||||
power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
|
||||
<&camcc CAM_CC_IFE_1_GDSC>,
|
||||
<&camcc CAM_CC_IFE_2_GDSC>,
|
||||
<&camcc CAM_CC_TITAN_TOP_GDSC>;
|
||||
power-domain-names = "ife0", "ife1", "ife2", "top";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
camcc: clock-controller@ade0000 {
|
||||
compatible = "qcom,sm8650-camcc";
|
||||
reg = <0 0x0ade0000 0 0x20000>;
|
||||
|
|
@ -5922,6 +6109,118 @@ tlmm: pinctrl@f100000 {
|
|||
|
||||
wakeup-parent = <&pdc>;
|
||||
|
||||
cam0_default: cam0-default-state {
|
||||
pins = "gpio100";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cam0_sleep: cam0-sleep-state {
|
||||
pins = "gpio100";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cam1_default: cam1-default-state {
|
||||
pins = "gpio101";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cam1_sleep: cam1-sleep-state {
|
||||
pins = "gpio101";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cam2_default: cam2-default-state {
|
||||
pins = "gpio102";
|
||||
function = "cam_aon_mclk2";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cam2_sleep: cam2-sleep-state {
|
||||
pins = "gpio102";
|
||||
function = "cam_aon_mclk2";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cam3_default: cam3-default-state {
|
||||
pins = "gpio103";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cam3_sleep: cam3-sleep-state {
|
||||
pins = "gpio103";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cam4_default: cam4-default-state {
|
||||
pins = "gpio104";
|
||||
function = "cam_aon_mclk4";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cam4_sleep: cam4-sleep-state {
|
||||
pins = "gpio104";
|
||||
function = "cam_aon_mclk4";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cam5_default: cam5-default-state {
|
||||
pins = "gpio105";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cam5_sleep: cam5-sleep-state {
|
||||
pins = "gpio105";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cam6_default: cam6-default-state {
|
||||
pins = "gpio108";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cam6_sleep: cam6-sleep-state {
|
||||
pins = "gpio108";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cam7_default: cam7-default-state {
|
||||
pins = "gpio106";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cam7_sleep: cam7-sleep-state {
|
||||
pins = "gpio106";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cci0_0_default: cci0-0-default-state {
|
||||
sda-pins {
|
||||
pins = "gpio113";
|
||||
|
|
|
|||
|
|
@ -925,6 +925,10 @@ vreg_l7n_3p3: ldo7 {
|
|||
};
|
||||
};
|
||||
|
||||
&iris {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpass_vamacro {
|
||||
pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -1039,10 +1043,14 @@ wifi@0 {
|
|||
};
|
||||
|
||||
&pmih0108_eusb2_repeater {
|
||||
status = "okay";
|
||||
qcom,tune-usb2-preem = /bits/ 8 <0x3>;
|
||||
qcom,tune-usb2-amplitude = /bits/ 8 <0xa>;
|
||||
qcom,squelch-detector-bp = <(-2000)>;
|
||||
|
||||
vdd18-supply = <&vreg_l15b_1p8>;
|
||||
vdd3-supply = <&vreg_l5b_3p1>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_1 {
|
||||
|
|
@ -1075,6 +1083,22 @@ &remoteproc_mpss {
|
|||
status = "fail";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vmmc-supply = <&vreg_l9b_2p9>;
|
||||
vqmmc-supply = <&vreg_l8b_1p8>;
|
||||
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
|
||||
pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
|
||||
pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -1194,6 +1218,13 @@ sw-ctrl-pins {
|
|||
};
|
||||
};
|
||||
|
||||
sdc2_card_det_n: sd-card-det-n-state {
|
||||
pins = "gpio55";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
wcd_default: wcd-reset-n-active-state {
|
||||
pins = "gpio101";
|
||||
function = "gpio";
|
||||
|
|
|
|||
|
|
@ -858,6 +858,10 @@ vreg_l7n_3p3: ldo7 {
|
|||
};
|
||||
};
|
||||
|
||||
&iris {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8550_flash {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -961,6 +965,22 @@ &remoteproc_mpss {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vmmc-supply = <&vreg_l9b_2p9>;
|
||||
vqmmc-supply = <&vreg_l8b_1p8>;
|
||||
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
|
||||
pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
|
||||
pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -1053,6 +1073,13 @@ &tlmm {
|
|||
/* reserved for secure world */
|
||||
gpio-reserved-ranges = <36 4>, <74 1>;
|
||||
|
||||
sdc2_card_det_n: sd-card-det-n-state {
|
||||
pins = "gpio55";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
spkr_0_sd_n_active: spkr-0-sd-n-active-state {
|
||||
pins = "gpio76";
|
||||
function = "gpio";
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,sm8750-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
|
||||
#include <dt-bindings/clock/qcom,sm8750-videocc.h>
|
||||
#include <dt-bindings/dma/qcom-gpi.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interconnect/qcom,icc.h>
|
||||
|
|
@ -35,8 +36,8 @@ cpu0: cpu@0 {
|
|||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2_0>;
|
||||
power-domains = <&cpu_pd0>;
|
||||
power-domain-names = "psci";
|
||||
power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
|
||||
power-domain-names = "psci", "perf";
|
||||
|
||||
l2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -51,8 +52,8 @@ cpu1: cpu@100 {
|
|||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2_0>;
|
||||
power-domains = <&cpu_pd1>;
|
||||
power-domain-names = "psci";
|
||||
power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
|
||||
power-domain-names = "psci", "perf";
|
||||
};
|
||||
|
||||
cpu2: cpu@200 {
|
||||
|
|
@ -61,8 +62,8 @@ cpu2: cpu@200 {
|
|||
reg = <0x0 0x200>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2_0>;
|
||||
power-domains = <&cpu_pd2>;
|
||||
power-domain-names = "psci";
|
||||
power-domains = <&cpu_pd2>, <&scmi_dvfs 0>;
|
||||
power-domain-names = "psci", "perf";
|
||||
};
|
||||
|
||||
cpu3: cpu@300 {
|
||||
|
|
@ -71,8 +72,8 @@ cpu3: cpu@300 {
|
|||
reg = <0x0 0x300>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2_0>;
|
||||
power-domains = <&cpu_pd3>;
|
||||
power-domain-names = "psci";
|
||||
power-domains = <&cpu_pd3>, <&scmi_dvfs 0>;
|
||||
power-domain-names = "psci", "perf";
|
||||
};
|
||||
|
||||
cpu4: cpu@400 {
|
||||
|
|
@ -81,8 +82,8 @@ cpu4: cpu@400 {
|
|||
reg = <0x0 0x400>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2_0>;
|
||||
power-domains = <&cpu_pd4>;
|
||||
power-domain-names = "psci";
|
||||
power-domains = <&cpu_pd4>, <&scmi_dvfs 0>;
|
||||
power-domain-names = "psci", "perf";
|
||||
};
|
||||
|
||||
cpu5: cpu@500 {
|
||||
|
|
@ -91,8 +92,8 @@ cpu5: cpu@500 {
|
|||
reg = <0x0 0x500>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2_0>;
|
||||
power-domains = <&cpu_pd5>;
|
||||
power-domain-names = "psci";
|
||||
power-domains = <&cpu_pd5>, <&scmi_dvfs 0>;
|
||||
power-domain-names = "psci", "perf";
|
||||
};
|
||||
|
||||
cpu6: cpu@10000 {
|
||||
|
|
@ -101,8 +102,8 @@ cpu6: cpu@10000 {
|
|||
reg = <0x0 0x10000>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2_1>;
|
||||
power-domains = <&cpu_pd6>;
|
||||
power-domain-names = "psci";
|
||||
power-domains = <&cpu_pd6>, <&scmi_dvfs 1>;
|
||||
power-domain-names = "psci", "perf";
|
||||
|
||||
l2_1: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -117,8 +118,8 @@ cpu7: cpu@10100 {
|
|||
reg = <0x0 0x10100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2_1>;
|
||||
power-domains = <&cpu_pd7>;
|
||||
power-domain-names = "psci";
|
||||
power-domains = <&cpu_pd7>, <&scmi_dvfs 1>;
|
||||
power-domain-names = "psci", "perf";
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
|
|
@ -206,6 +207,21 @@ scm: scm {
|
|||
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
};
|
||||
|
||||
scmi {
|
||||
compatible = "arm,scmi";
|
||||
mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>;
|
||||
mbox-names = "tx", "rx";
|
||||
shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
scmi_dvfs: protocol@13 {
|
||||
reg = <0x13>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clk_virt: interconnect-0 {
|
||||
|
|
@ -2073,6 +2089,8 @@ cryptobam: dma-controller@1dc4000 {
|
|||
<&apps_smmu 0x481 0>;
|
||||
|
||||
qcom,ee = <0>;
|
||||
qcom,num-ees = <4>;
|
||||
num-channels = <20>;
|
||||
qcom,controlled-remotely;
|
||||
};
|
||||
|
||||
|
|
@ -2582,6 +2600,60 @@ data-pins {
|
|||
};
|
||||
};
|
||||
|
||||
sdhc_2: mmc@8804000 {
|
||||
compatible = "qcom,sm8750-sdhci", "qcom,sdhci-msm-v5";
|
||||
reg = <0x0 0x08804000 0x0 0x1000>;
|
||||
|
||||
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq",
|
||||
"pwr_irq";
|
||||
|
||||
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
||||
<&gcc GCC_SDCC2_APPS_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface",
|
||||
"core",
|
||||
"xo";
|
||||
|
||||
interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
||||
interconnect-names = "sdhc-ddr",
|
||||
"cpu-sdhc";
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_CX>;
|
||||
operating-points-v2 = <&sdhc2_opp_table>;
|
||||
|
||||
qcom,dll-config = <0x0007442c>;
|
||||
qcom,ddr-config = <0x80040868>;
|
||||
|
||||
iommus = <&apps_smmu 0x540 0x0>;
|
||||
dma-coherent;
|
||||
|
||||
bus-width = <4>;
|
||||
max-sd-hs-hz = <37500000>;
|
||||
|
||||
resets = <&gcc GCC_SDCC2_BCR>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
sdhc2_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-202000000 {
|
||||
opp-hz = /bits/ 64 <202000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb_hsphy: phy@88e3000 {
|
||||
compatible = "qcom,sm8750-m31-eusb2-phy";
|
||||
reg = <0x0 0x88e3000 0x0 0x29c>;
|
||||
|
|
@ -2740,6 +2812,126 @@ usb_dwc3_ss: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
iris: video-codec@aa00000 {
|
||||
compatible = "qcom,sm8750-iris";
|
||||
reg = <0x0 0x0aa00000 0x0 0xf0000>;
|
||||
|
||||
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
|
||||
<&videocc VIDEO_CC_MVS0C_CLK>,
|
||||
<&videocc VIDEO_CC_MVS0_CLK>,
|
||||
<&gcc GCC_VIDEO_AXI1_CLK>,
|
||||
<&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
|
||||
<&videocc VIDEO_CC_MVS0_FREERUN_CLK>;
|
||||
clock-names = "iface",
|
||||
"core",
|
||||
"vcodec0_core",
|
||||
"iface1",
|
||||
"core_freerun",
|
||||
"vcodec0_core_freerun";
|
||||
|
||||
dma-coherent;
|
||||
iommus = <&apps_smmu 0x1940 0>,
|
||||
<&apps_smmu 0x1947 0>;
|
||||
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
|
||||
<&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "cpu-cfg",
|
||||
"video-mem";
|
||||
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
memory-region = <&video_mem>;
|
||||
|
||||
operating-points-v2 = <&iris_opp_table>;
|
||||
|
||||
power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
|
||||
<&videocc VIDEO_CC_MVS0_GDSC>,
|
||||
<&rpmhpd RPMHPD_MXC>,
|
||||
<&rpmhpd RPMHPD_MMCX>;
|
||||
power-domain-names = "venus",
|
||||
"vcodec0",
|
||||
"mxc",
|
||||
"mmcx";
|
||||
|
||||
resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
|
||||
<&gcc GCC_VIDEO_AXI1_CLK_ARES>,
|
||||
<&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
|
||||
<&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>;
|
||||
reset-names = "bus0",
|
||||
"bus1",
|
||||
"core",
|
||||
"vcodec0_core";
|
||||
|
||||
/*
|
||||
* IRIS firmware is signed by vendors, only
|
||||
* enable in boards where the proper signed firmware
|
||||
* is available.
|
||||
*/
|
||||
status = "disabled";
|
||||
|
||||
iris_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-240000000 {
|
||||
opp-hz = /bits/ 64 <240000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs_d1>,
|
||||
<&rpmhpd_opp_low_svs_d1>;
|
||||
};
|
||||
|
||||
opp-338000000 {
|
||||
opp-hz = /bits/ 64 <338000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>,
|
||||
<&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-420000000 {
|
||||
opp-hz = /bits/ 64 <420000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>,
|
||||
<&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-444000000 {
|
||||
opp-hz = /bits/ 64 <444000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>,
|
||||
<&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-533333334 {
|
||||
opp-hz = /bits/ 64 <533333334>;
|
||||
required-opps = <&rpmhpd_opp_nom>,
|
||||
<&rpmhpd_opp_nom>;
|
||||
};
|
||||
|
||||
opp-570000000 {
|
||||
opp-hz = /bits/ 64 <570000000>;
|
||||
required-opps = <&rpmhpd_opp_nom_l1>,
|
||||
<&rpmhpd_opp_nom_l1>;
|
||||
};
|
||||
|
||||
opp-630000000 {
|
||||
opp-hz = /bits/ 64 <630000000>;
|
||||
required-opps = <&rpmhpd_opp_turbo>,
|
||||
<&rpmhpd_opp_turbo>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
videocc: clock-controller@aaf0000 {
|
||||
compatible = "qcom,sm8750-videocc";
|
||||
reg = <0x0 0x0aaf0000 0x0 0x10000>;
|
||||
clocks = <&bi_tcxo_div2>,
|
||||
<&gcc GCC_VIDEO_AHB_CLK>;
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>,
|
||||
<&rpmhpd RPMHPD_MXC>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>,
|
||||
<&rpmhpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
pdc: interrupt-controller@b220000 {
|
||||
compatible = "qcom,sm8750-pdc", "qcom,pdc";
|
||||
reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
|
||||
|
|
@ -3471,7 +3663,7 @@ pcie0: pcie@1c00000 {
|
|||
<0x0 0x40000f20 0x0 0xa8>,
|
||||
<0x0 0x40001000 0x0 0x1000>,
|
||||
<0x0 0x40100000 0x0 0x100000>,
|
||||
<0x0 0x01C03000 0x0 0x1000>;
|
||||
<0x0 0x01c03000 0x0 0x1000>;
|
||||
reg-names = "parf",
|
||||
"dbi",
|
||||
"elbi",
|
||||
|
|
@ -3743,6 +3935,13 @@ opp-403000000 {
|
|||
};
|
||||
};
|
||||
|
||||
cpucp_mbox: mailbox@16430000 {
|
||||
compatible = "qcom,sm8750-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
|
||||
reg = <0x0 0x16430000 0x0 0x8000>, <0x0 0x17830000 0x0 0x8000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
apps_rsc: rsc@16500000 {
|
||||
compatible = "qcom,rpmh-rsc";
|
||||
reg = <0x0 0x16500000 0x0 0x10000>,
|
||||
|
|
@ -3954,6 +4153,25 @@ frame@1680d000 {
|
|||
};
|
||||
};
|
||||
|
||||
sram: sram@17b4e000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x0 0x17b4e000 0x0 0x400>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x17b4e000 0x400>;
|
||||
|
||||
cpu_scp_lpri0: scp-sram-section@0 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x0 0x200>;
|
||||
};
|
||||
|
||||
cpu_scp_lpri1: scp-sram-section@200 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x200 0x200>;
|
||||
};
|
||||
};
|
||||
|
||||
/* cluster0 */
|
||||
pmu@240b3400 {
|
||||
compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon";
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
#include <dt-bindings/interconnect/qcom,osm-l3.h>
|
||||
#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/phy/phy-qcom-qmp.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
||||
|
|
@ -479,12 +480,6 @@ camnoc_virt: interconnect-0 {
|
|||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
ipa_virt: interconnect-1 {
|
||||
compatible = "qcom,qcs615-ipa-virt";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
mc_virt: interconnect-2 {
|
||||
compatible = "qcom,qcs615-mc-virt";
|
||||
#interconnect-cells = <2>;
|
||||
|
|
@ -494,7 +489,7 @@ mc_virt: interconnect-2 {
|
|||
smp2p-adsp {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <443>, <429>;
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING 0>;
|
||||
/* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */
|
||||
mboxes = <&apss_shared 26>;
|
||||
|
||||
|
|
@ -516,7 +511,7 @@ adsp_smp2p_in: slave-kernel {
|
|||
smp2p-cdsp {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <94>, <432>;
|
||||
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING 0>;
|
||||
mboxes = <&apss_shared 6>;
|
||||
|
||||
qcom,local-pid = <0>;
|
||||
|
|
@ -555,6 +550,16 @@ opp-128000000 {
|
|||
};
|
||||
};
|
||||
|
||||
pmu-a55 {
|
||||
compatible = "arm,cortex-a55-pmu";
|
||||
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
|
||||
};
|
||||
|
||||
pmu-a76 {
|
||||
compatible = "arm,cortex-a76-pmu";
|
||||
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
|
|
@ -694,8 +699,8 @@ sdhc_1: mmc@7c4000 {
|
|||
"cqhci",
|
||||
"ice";
|
||||
|
||||
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "hc_irq",
|
||||
"pwr_irq";
|
||||
|
||||
|
|
@ -756,14 +761,14 @@ gpi_dma0: dma-controller@800000 {
|
|||
compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
|
||||
reg = <0x0 0x800000 0x0 0x60000>;
|
||||
#dma-cells = <3>;
|
||||
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
dma-channels = <8>;
|
||||
dma-channel-mask = <0xf>;
|
||||
iommus = <&apps_smmu 0xd6 0x0>;
|
||||
|
|
@ -790,7 +795,7 @@ uart0: serial@880000 {
|
|||
clock-names = "se";
|
||||
pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>;
|
||||
pinctrl-names = "default";
|
||||
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
|
|
@ -807,7 +812,7 @@ i2c1: i2c@884000 {
|
|||
reg = <0x0 0x884000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
||||
clock-names = "se";
|
||||
pinctrl-0 = <&qup_i2c1_data_clk>;
|
||||
|
|
@ -835,7 +840,7 @@ i2c2: i2c@888000 {
|
|||
reg = <0x0 0x888000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
clock-names = "se";
|
||||
pinctrl-0 = <&qup_i2c2_data_clk>;
|
||||
|
|
@ -861,7 +866,7 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|||
spi2: spi@888000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0x0 0x00888000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
clock-names = "se";
|
||||
pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
|
||||
|
|
@ -886,7 +891,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|||
uart2: serial@888000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0x0 0x00888000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
clock-names = "se";
|
||||
pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>,
|
||||
|
|
@ -908,7 +913,7 @@ i2c3: i2c@88c000 {
|
|||
reg = <0x0 0x88c000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
||||
clock-names = "se";
|
||||
pinctrl-0 = <&qup_i2c3_data_clk>;
|
||||
|
|
@ -936,14 +941,14 @@ gpi_dma1: dma-controller@a00000 {
|
|||
compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
|
||||
reg = <0x0 0xa00000 0x0 0x60000>;
|
||||
#dma-cells = <3>;
|
||||
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
dma-channels = <8>;
|
||||
dma-channel-mask = <0xf>;
|
||||
iommus = <&apps_smmu 0x376 0x0>;
|
||||
|
|
@ -970,7 +975,7 @@ i2c4: i2c@a80000 {
|
|||
clock-names = "se";
|
||||
pinctrl-0 = <&qup_i2c4_data_clk>;
|
||||
pinctrl-names = "default";
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
|
||||
|
|
@ -998,7 +1003,7 @@ spi4: spi@a80000 {
|
|||
clock-names = "se";
|
||||
pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
|
||||
pinctrl-names = "default";
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
|
||||
|
|
@ -1024,7 +1029,7 @@ uart4: serial@a80000 {
|
|||
pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>,
|
||||
<&qup_uart4_tx>, <&qup_uart4_rx>;
|
||||
pinctrl-names = "default";
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
|
|
@ -1043,7 +1048,7 @@ i2c5: i2c@a84000 {
|
|||
clock-names = "se";
|
||||
pinctrl-0 = <&qup_i2c5_data_clk>;
|
||||
pinctrl-names = "default";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
|
||||
|
|
@ -1071,7 +1076,7 @@ i2c6: i2c@a88000 {
|
|||
clock-names = "se";
|
||||
pinctrl-0 = <&qup_i2c6_data_clk>;
|
||||
pinctrl-names = "default";
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
|
||||
|
|
@ -1099,7 +1104,7 @@ spi6: spi@a88000 {
|
|||
clock-names = "se";
|
||||
pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
|
||||
pinctrl-names = "default";
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
|
||||
|
|
@ -1125,7 +1130,7 @@ uart6: serial@a88000 {
|
|||
pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>,
|
||||
<&qup_uart6_tx>, <&qup_uart6_rx>;
|
||||
pinctrl-names = "default";
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
|
|
@ -1144,7 +1149,7 @@ i2c7: i2c@a8c000 {
|
|||
clock-names = "se";
|
||||
pinctrl-0 = <&qup_i2c7_data_clk>;
|
||||
pinctrl-names = "default";
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
|
||||
|
|
@ -1172,7 +1177,7 @@ spi7: spi@a8c000 {
|
|||
clock-names = "se";
|
||||
pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
|
||||
pinctrl-names = "default";
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
|
||||
|
|
@ -1198,7 +1203,7 @@ uart7: serial@a8c000 {
|
|||
pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>,
|
||||
<&qup_uart7_tx>, <&qup_uart7_rx>;
|
||||
pinctrl-names = "default";
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
|
|
@ -1265,15 +1270,15 @@ pcie: pcie@1c08000 {
|
|||
linux,pci-domain = <0>;
|
||||
num-lanes = <1>;
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "msi0",
|
||||
"msi1",
|
||||
"msi2",
|
||||
|
|
@ -1286,10 +1291,10 @@ pcie: pcie@1c08000 {
|
|||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
|
|
@ -1393,7 +1398,7 @@ ufs_mem_hc: ufshc@1d84000 {
|
|||
reg-names = "std",
|
||||
"ice";
|
||||
|
||||
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
||||
|
|
@ -1502,7 +1507,7 @@ ufs_mem_phy: phy@1d87000 {
|
|||
cryptobam: dma-controller@1dc4000 {
|
||||
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
|
||||
reg = <0x0 0x01dc4000 0x0 0x24000>;
|
||||
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
qcom,controlled-remotely;
|
||||
|
|
@ -1541,7 +1546,7 @@ tlmm: pinctrl@3100000 {
|
|||
reg-names = "east",
|
||||
"west",
|
||||
"south";
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
gpio-ranges = <&tlmm 0 0 124>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -3468,7 +3473,7 @@ remoteproc_cdsp: remoteproc@8300000 {
|
|||
compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas";
|
||||
reg = <0x0 0x08300000 0x0 0x4040>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
|
||||
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
|
|
@ -3495,7 +3500,7 @@ remoteproc_cdsp: remoteproc@8300000 {
|
|||
status = "disabled";
|
||||
|
||||
glink-edge {
|
||||
interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING 0>;
|
||||
mboxes = <&apss_shared 4>;
|
||||
label = "cdsp";
|
||||
qcom,remote-pid = <5>;
|
||||
|
|
@ -3555,7 +3560,7 @@ compute-cb@6 {
|
|||
pmu@90b6300 {
|
||||
compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon";
|
||||
reg = <0x0 0x090b6300 0x0 0x600>;
|
||||
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
|
||||
|
||||
|
|
@ -3577,7 +3582,7 @@ opp-1 {
|
|||
pmu@90cd000 {
|
||||
compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
|
||||
reg = <0x0 0x090cd000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
||||
|
||||
|
|
@ -3629,8 +3634,8 @@ sdhc_2: mmc@8804000 {
|
|||
reg = <0x0 0x08804000 0x0 0x1000>;
|
||||
reg-names = "hc";
|
||||
|
||||
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "hc_irq",
|
||||
"pwr_irq";
|
||||
|
||||
|
|
@ -3703,7 +3708,7 @@ gem_noc: interconnect@9680000 {
|
|||
venus: video-codec@aa00000 {
|
||||
compatible = "qcom,qcs615-venus", "qcom,sc7180-venus";
|
||||
reg = <0x0 0x0aa00000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
|
||||
<&videocc VIDEO_CC_VENUS_AHB_CLK>,
|
||||
|
|
@ -3814,7 +3819,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
|
|
@ -3855,6 +3860,7 @@ port@0 {
|
|||
reg = <0>;
|
||||
|
||||
dpu_intf0_out: endpoint {
|
||||
remote-endpoint = <&mdss_dp0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -3887,6 +3893,89 @@ opp-307200000 {
|
|||
};
|
||||
};
|
||||
|
||||
mdss_dp0: displayport-controller@ae90000 {
|
||||
compatible = "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp";
|
||||
|
||||
reg = <0x0 0x0ae90000 0x0 0x200>,
|
||||
<0x0 0x0ae90200 0x0 0x200>,
|
||||
<0x0 0x0ae90400 0x0 0x600>,
|
||||
<0x0 0x0ae90a00 0x0 0x600>,
|
||||
<0x0 0x0ae91000 0x0 0x600>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <12>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
phys = <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>;
|
||||
phy-names = "dp";
|
||||
|
||||
operating-points-v2 = <&dp_opp_table>;
|
||||
power-domains = <&rpmhpd RPMHPD_CX>;
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
mdss_dp0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mdss_dp0_out: endpoint {
|
||||
data-lanes = <3 2 0 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-270000000 {
|
||||
opp-hz = /bits/ 64 <270000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-540000000 {
|
||||
opp-hz = /bits/ 64 <540000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi0: dsi@ae94000 {
|
||||
compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0 0x0ae94000 0x0 0x400>;
|
||||
|
|
@ -3982,8 +4071,8 @@ dispcc: clock-controller@af00000 {
|
|||
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
|
||||
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>;
|
||||
<&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
|
@ -4003,7 +4092,7 @@ pdc: interrupt-controller@b220000 {
|
|||
aoss_qmp: power-management@c300000 {
|
||||
compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp";
|
||||
reg = <0x0 0x0c300000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING 0>;
|
||||
mboxes = <&apss_shared 0>;
|
||||
|
||||
#clock-cells = <0>;
|
||||
|
|
@ -4035,71 +4124,71 @@ apps_smmu: iommu@15000000 {
|
|||
#global-interrupts = <1>;
|
||||
dma-coherent;
|
||||
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
};
|
||||
|
||||
spmi_bus: spmi@c440000 {
|
||||
|
|
@ -4128,12 +4217,22 @@ intc: interrupt-controller@17a00000 {
|
|||
compatible = "arm,gic-v3";
|
||||
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
|
||||
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <3>;
|
||||
#interrupt-cells = <4>;
|
||||
interrupt-controller;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x20000>;
|
||||
|
||||
ppi-partitions {
|
||||
ppi_cluster0: interrupt-partition-0 {
|
||||
affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
|
||||
};
|
||||
|
||||
ppi_cluster1: interrupt-partition-1 {
|
||||
affinity = <&cpu6 &cpu7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
apss_shared: mailbox@17c00000 {
|
||||
|
|
@ -4146,7 +4245,7 @@ apss_shared: mailbox@17c00000 {
|
|||
watchdog: watchdog@17c10000 {
|
||||
compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt";
|
||||
reg = <0x0 0x17c10000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&sleep_clk>;
|
||||
};
|
||||
|
||||
|
|
@ -4161,49 +4260,49 @@ frame@17c21000 {
|
|||
reg = <0x17c21000 0x1000>,
|
||||
<0x17c22000 0x1000>;
|
||||
frame-number = <0>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
};
|
||||
|
||||
frame@17c23000 {
|
||||
reg = <0x17c23000 0x1000>;
|
||||
frame-number = <1>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c25000 {
|
||||
reg = <0x17c25000 0x1000>;
|
||||
frame-number = <2>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c27000 {
|
||||
reg = <0x17c27000 0x1000>;
|
||||
frame-number = <3>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c29000 {
|
||||
reg = <0x17c29000 0x1000>;
|
||||
frame-number = <4>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c2b000 {
|
||||
reg = <0x17c2b000 0x1000>;
|
||||
frame-number = <5>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17c2d000 {
|
||||
reg = <0x17c2d000 0x1000>;
|
||||
frame-number = <6>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -4217,9 +4316,9 @@ apps_rsc: rsc@18200000 {
|
|||
"drv-1",
|
||||
"drv-2";
|
||||
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
qcom,drv-id = <2>;
|
||||
qcom,tcs-offset = <0xd00>;
|
||||
|
|
@ -4362,6 +4461,32 @@ usb_qmpphy: phy@88e6000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_qmpphy_2: phy@88e8000 {
|
||||
compatible = "qcom,qcs615-qmp-usb3-dp-phy";
|
||||
reg = <0x0 0x088e8000 0x0 0x2000>;
|
||||
|
||||
clocks = <&gcc GCC_USB2_SEC_PHY_AUX_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
|
||||
<&gcc GCC_AHB2PHY_WEST_CLK>,
|
||||
<&gcc GCC_USB2_SEC_PHY_PIPE_CLK>;
|
||||
clock-names = "aux",
|
||||
"ref",
|
||||
"cfg_ahb",
|
||||
"pipe";
|
||||
|
||||
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >,
|
||||
<&gcc GCC_USB3_DP_PHY_SEC_BCR>;
|
||||
reset-names = "phy_phy",
|
||||
"dp_phy";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <1>;
|
||||
|
||||
qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_1: usb@a6f8800 {
|
||||
compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
|
||||
reg = <0x0 0x0a6f8800 0x0 0x400>;
|
||||
|
|
@ -4383,8 +4508,8 @@ usb_1: usb@a6f8800 {
|
|||
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>, <200000000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<&pdc 9 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -4410,7 +4535,7 @@ usb_1_dwc3: usb@a600000 {
|
|||
reg = <0x0 0x0a600000 0x0 0xcd00>;
|
||||
|
||||
iommus = <&apps_smmu 0x140 0x0>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
phys = <&usb_1_hsphy>, <&usb_qmpphy>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
|
|
@ -4447,8 +4572,8 @@ usb_2: usb@a8f8800 {
|
|||
<&gcc GCC_USB20_SEC_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>, <200000000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<&pdc 11 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 10 IRQ_TYPE_EDGE_BOTH>;
|
||||
interrupt-names = "pwr_event",
|
||||
|
|
@ -4474,7 +4599,7 @@ usb_2_dwc3: usb@a800000 {
|
|||
reg = <0x0 0x0a800000 0x0 0xcd00>;
|
||||
|
||||
iommus = <&apps_smmu 0xe0 0x0>;
|
||||
interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
phys = <&usb_hsphy_2>;
|
||||
phy-names = "usb2-phy";
|
||||
|
|
@ -4493,8 +4618,8 @@ tsens0: thermal-sensor@c263000 {
|
|||
compatible = "qcom,qcs615-tsens", "qcom,tsens-v2";
|
||||
reg = <0x0 0x0c263000 0x0 0x1000>,
|
||||
<0x0 0x0c222000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "uplow", "critical";
|
||||
#qcom,sensors = <16>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
|
|
@ -4504,7 +4629,7 @@ remoteproc_adsp: remoteproc@62400000 {
|
|||
compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas";
|
||||
reg = <0x0 0x62400000 0x0 0x4040>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
|
||||
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING 0>,
|
||||
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
|
|
@ -4531,7 +4656,7 @@ remoteproc_adsp: remoteproc@62400000 {
|
|||
status = "disabled";
|
||||
|
||||
glink_edge: glink-edge {
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING 0>;
|
||||
mboxes = <&apss_shared 24>;
|
||||
label = "lpass";
|
||||
qcom,remote-pid = <2>;
|
||||
|
|
@ -4590,10 +4715,10 @@ cpufreq_hw: cpufreq@18323000 {
|
|||
|
||||
arch_timer: timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
|
||||
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
|
||||
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
|
||||
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
|
|
|
|||
1322
arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi
Normal file
1322
arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -1003,9 +1003,6 @@ &mdss_dp2_out {
|
|||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
|
@ -1019,10 +1016,12 @@ &pcie4_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie5 {
|
||||
perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
|
||||
&pcie4_port0 {
|
||||
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pcie5 {
|
||||
vddpe-3v3-supply = <&vreg_wwan>;
|
||||
|
||||
pinctrl-0 = <&pcie5_default>;
|
||||
|
|
@ -1038,10 +1037,12 @@ &pcie5_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
&pcie5_port0 {
|
||||
reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pcie6a {
|
||||
vddpe-3v3-supply = <&vreg_nvme>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -1057,6 +1058,11 @@ &pcie6a_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a_port0 {
|
||||
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pm8550_gpios {
|
||||
rtmr0_default: rtmr0-reset-n-active-state {
|
||||
pins = "gpio10";
|
||||
|
|
|
|||
|
|
@ -62,6 +62,45 @@ switch-lid {
|
|||
};
|
||||
};
|
||||
|
||||
hdmi-bridge {
|
||||
compatible = "realtek,rtd2171";
|
||||
|
||||
pinctrl-0 = <&hdmi_hpd_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi_bridge_dp_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hdmi_bridge_tmds_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con: endpoint {
|
||||
remote-endpoint = <&hdmi_bridge_tmds_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmic-glink {
|
||||
compatible = "qcom,x1e80100-pmic-glink",
|
||||
"qcom,sm8550-pmic-glink",
|
||||
|
|
@ -351,6 +390,54 @@ sound {
|
|||
"VA DMIC1", "VA MIC BIAS1",
|
||||
"TX SWR_INPUT1", "ADC2_OUTPUT";
|
||||
|
||||
displayport-0-dai-link {
|
||||
link-name = "DisplayPort0 Playback";
|
||||
|
||||
codec {
|
||||
sound-dai = <&mdss_dp0>;
|
||||
};
|
||||
|
||||
cpu {
|
||||
sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>;
|
||||
};
|
||||
|
||||
platform {
|
||||
sound-dai = <&q6apm>;
|
||||
};
|
||||
};
|
||||
|
||||
displayport-1-dai-link {
|
||||
link-name = "DisplayPort1 Playback";
|
||||
|
||||
codec {
|
||||
sound-dai = <&mdss_dp1>;
|
||||
};
|
||||
|
||||
cpu {
|
||||
sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>;
|
||||
};
|
||||
|
||||
platform {
|
||||
sound-dai = <&q6apm>;
|
||||
};
|
||||
};
|
||||
|
||||
displayport-2-dai-link {
|
||||
link-name = "DisplayPort2 Playback";
|
||||
|
||||
codec {
|
||||
sound-dai = <&mdss_dp2>;
|
||||
};
|
||||
|
||||
cpu {
|
||||
sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>;
|
||||
};
|
||||
|
||||
platform {
|
||||
sound-dai = <&q6apm>;
|
||||
};
|
||||
};
|
||||
|
||||
wcd-playback-dai-link {
|
||||
link-name = "WCD Playback";
|
||||
|
||||
|
|
@ -1028,6 +1115,14 @@ &mdss_dp1_out {
|
|||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
|
||||
};
|
||||
|
||||
&mdss_dp2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dp2_out {
|
||||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
|
||||
};
|
||||
|
||||
&mdss_dp3 {
|
||||
/delete-property/ #sound-dai-cells;
|
||||
|
||||
|
|
@ -1065,9 +1160,6 @@ &mdss_dp3_phy {
|
|||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
|
@ -1081,10 +1173,12 @@ &pcie4_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie5 {
|
||||
perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
|
||||
&pcie4_port0 {
|
||||
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pcie5 {
|
||||
vddpe-3v3-supply = <&vreg_wwan>;
|
||||
|
||||
pinctrl-0 = <&pcie5_default>;
|
||||
|
|
@ -1100,10 +1194,12 @@ &pcie5_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
&pcie5_port0 {
|
||||
reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pcie6a {
|
||||
vddpe-3v3-supply = <&vreg_nvme>;
|
||||
|
||||
pinctrl-0 = <&pcie6a_default>;
|
||||
|
|
@ -1119,6 +1215,11 @@ &pcie6a_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a_port0 {
|
||||
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pm8550_gpios {
|
||||
rtmr0_default: rtmr0-reset-n-active-state {
|
||||
pins = "gpio10";
|
||||
|
|
@ -1317,6 +1418,12 @@ eusb6_reset_n: eusb6-reset-n-state {
|
|||
output-low;
|
||||
};
|
||||
|
||||
hdmi_hpd_default: hdmi-hpd-default-state {
|
||||
pins = "gpio126";
|
||||
function = "usb2_dp";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
tpad_default: tpad-default-state {
|
||||
pins = "gpio3";
|
||||
function = "gpio";
|
||||
|
|
@ -1548,6 +1655,34 @@ &usb_1_ss1_qmpphy_out {
|
|||
remote-endpoint = <&retimer_ss1_ss_in>;
|
||||
};
|
||||
|
||||
&usb_1_ss2_qmpphy {
|
||||
vdda-phy-supply = <&vreg_l2j_1p2>;
|
||||
vdda-pll-supply = <&vreg_l2d_0p9>;
|
||||
|
||||
/delete-property/ mode-switch;
|
||||
/delete-property/ orientation-switch;
|
||||
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/delete-node/ endpoint;
|
||||
|
||||
usb_1_ss2_qmpphy_out_dp: endpoint@0 {
|
||||
reg = <0>;
|
||||
|
||||
data-lanes = <3 2 1 0>;
|
||||
remote-endpoint = <&hdmi_bridge_dp_in>;
|
||||
};
|
||||
|
||||
/* No USB3 lanes connected */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -37,6 +37,45 @@ switch-lid {
|
|||
};
|
||||
};
|
||||
|
||||
hdmi-bridge {
|
||||
compatible = "parade,ps185hdm";
|
||||
|
||||
pinctrl-0 = <&hdmi_hpd_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi_bridge_dp_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hdmi_bridge_tmds_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con: endpoint {
|
||||
remote-endpoint = <&hdmi_bridge_tmds_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmic-glink {
|
||||
compatible = "qcom,x1e80100-pmic-glink",
|
||||
"qcom,sm8550-pmic-glink",
|
||||
|
|
@ -69,7 +108,15 @@ port@1 {
|
|||
reg = <1>;
|
||||
|
||||
pmic_glink_ss0_ss_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss0_qmpphy_out>;
|
||||
remote-endpoint = <&retimer_ss0_ss_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
pmic_glink_ss0_con_sbu_in: endpoint {
|
||||
remote-endpoint = <&retimer_ss0_con_sbu_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -98,7 +145,15 @@ port@1 {
|
|||
reg = <1>;
|
||||
|
||||
pmic_glink_ss1_ss_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss1_qmpphy_out>;
|
||||
remote-endpoint = <&retimer_ss1_ss_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
pmic_glink_ss1_con_sbu_in: endpoint {
|
||||
remote-endpoint = <&retimer_ss1_con_sbu_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -147,6 +202,102 @@ vreg_nvme: regulator-nvme {
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_RTMR0_1P15";
|
||||
regulator-min-microvolt = <1150000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
|
||||
gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&usb0_pwr_1p15_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_RTMR0_1P8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&usb0_1p8_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_RTMR0_3P3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&usb0_3p3_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_RTMR1_1P15";
|
||||
regulator-min-microvolt = <1150000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
|
||||
gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&usb1_pwr_1p15_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_RTMR1_1P8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&usb1_pwr_1p8_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_RTMR1_3P3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&usb1_pwr_3p3_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vph_pwr: regulator-vph-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
|
|
@ -506,15 +657,62 @@ touchpad@15 {
|
|||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
/* PS8830 USB4 Retimer? @ 0x8 */
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
/* PS8830 USB4 Retimer? @ 0x8 */
|
||||
typec-mux@8 {
|
||||
compatible = "parade,ps8830";
|
||||
reg = <0x08>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_RF_CLK3>;
|
||||
|
||||
vdd-supply = <&vreg_rtmr0_1p15>;
|
||||
vdd33-supply = <&vreg_rtmr0_3p3>;
|
||||
vdd33-cap-supply = <&vreg_rtmr0_3p3>;
|
||||
vddar-supply = <&vreg_rtmr0_1p15>;
|
||||
vddat-supply = <&vreg_rtmr0_1p15>;
|
||||
vddio-supply = <&vreg_rtmr0_1p8>;
|
||||
|
||||
reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&rtmr0_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
orientation-switch;
|
||||
retimer-switch;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
retimer_ss0_ss_out: endpoint {
|
||||
remote-endpoint = <&pmic_glink_ss0_ss_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
retimer_ss0_ss_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss0_qmpphy_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
retimer_ss0_con_sbu_out: endpoint {
|
||||
remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
|
|
@ -583,13 +781,91 @@ &i2c7 {
|
|||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
/* PS8830 USB4 Retimer? @ 0x8 */
|
||||
typec-mux@8 {
|
||||
compatible = "parade,ps8830";
|
||||
reg = <0x8>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_RF_CLK4>;
|
||||
|
||||
vdd-supply = <&vreg_rtmr1_1p15>;
|
||||
vdd33-supply = <&vreg_rtmr1_3p3>;
|
||||
vdd33-cap-supply = <&vreg_rtmr1_3p3>;
|
||||
vddar-supply = <&vreg_rtmr1_1p15>;
|
||||
vddat-supply = <&vreg_rtmr1_1p15>;
|
||||
vddio-supply = <&vreg_rtmr1_1p8>;
|
||||
|
||||
reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&rtmr1_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
retimer-switch;
|
||||
orientation-switch;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
retimer_ss1_ss_out: endpoint {
|
||||
remote-endpoint = <&pmic_glink_ss1_ss_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
retimer_ss1_ss_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss1_qmpphy_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
retimer_ss1_con_sbu_out: endpoint {
|
||||
remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iris {
|
||||
firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcvss8380.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dp0_out {
|
||||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
|
||||
};
|
||||
|
||||
&mdss_dp1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dp1_out {
|
||||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
|
||||
};
|
||||
|
||||
&mdss_dp2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dp2_out {
|
||||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
|
||||
};
|
||||
|
||||
&mdss_dp3 {
|
||||
/delete-property/ #sound-dai-cells;
|
||||
|
||||
|
|
@ -631,9 +907,6 @@ &mdss_dp3_phy {
|
|||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
|
@ -648,6 +921,9 @@ &pcie4_phy {
|
|||
};
|
||||
|
||||
&pcie4_port0 {
|
||||
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
wifi@0 {
|
||||
compatible = "pci17cb,1107";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
|
|
@ -665,9 +941,6 @@ wifi@0 {
|
|||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vddpe-3v3-supply = <&vreg_nvme>;
|
||||
|
||||
pinctrl-0 = <&pcie6a_default>;
|
||||
|
|
@ -683,6 +956,42 @@ &pcie6a_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a_port0 {
|
||||
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pm8550_gpios {
|
||||
rtmr0_default: rtmr0-reset-n-active-state {
|
||||
pins = "gpio10";
|
||||
function = "normal";
|
||||
power-source = <1>; /* 1.8V */
|
||||
bias-disable;
|
||||
input-disable;
|
||||
output-enable;
|
||||
};
|
||||
|
||||
usb0_3p3_reg_en: usb0-3p3-reg-en-state {
|
||||
pins = "gpio11";
|
||||
function = "normal";
|
||||
power-source = <1>; /* 1.8V */
|
||||
bias-disable;
|
||||
input-disable;
|
||||
output-enable;
|
||||
};
|
||||
};
|
||||
|
||||
&pm8550ve_9_gpios {
|
||||
usb0_1p8_reg_en: usb0-1p8-reg-en-state {
|
||||
pins = "gpio8";
|
||||
function = "normal";
|
||||
power-source = <1>; /* 1.8V */
|
||||
bias-disable;
|
||||
input-disable;
|
||||
output-enable;
|
||||
};
|
||||
};
|
||||
|
||||
&pmc8380_3_gpios {
|
||||
edp_bl_en: edp-bl-en-state {
|
||||
pins = "gpio4";
|
||||
|
|
@ -695,6 +1004,17 @@ edp_bl_en: edp-bl-en-state {
|
|||
};
|
||||
};
|
||||
|
||||
&pmc8380_5_gpios {
|
||||
usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state {
|
||||
pins = "gpio8";
|
||||
function = "normal";
|
||||
power-source = <1>; /* 1.8V */
|
||||
bias-disable;
|
||||
input-disable;
|
||||
output-enable;
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -781,6 +1101,12 @@ hall_int_n_default: hall-int-n-state {
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
hdmi_hpd_default: hdmi-hpd-default-state {
|
||||
pins = "gpio126";
|
||||
function = "usb2_dp";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
kybd_default: kybd-default-state {
|
||||
pins = "gpio67";
|
||||
function = "gpio";
|
||||
|
|
@ -840,12 +1166,40 @@ wake-n-pins {
|
|||
};
|
||||
};
|
||||
|
||||
rtmr1_default: rtmr1-reset-n-active-state {
|
||||
pins = "gpio176";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
tpad_default: tpad-default-state {
|
||||
pins = "gpio3";
|
||||
function = "gpio";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state {
|
||||
pins = "gpio188";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state {
|
||||
pins = "gpio175";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state {
|
||||
pins = "gpio186";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
wcn_bt_en: wcn-bt-en-state {
|
||||
pins = "gpio116";
|
||||
function = "gpio";
|
||||
|
|
@ -914,7 +1268,7 @@ &usb_1_ss0_dwc3_hs {
|
|||
};
|
||||
|
||||
&usb_1_ss0_qmpphy_out {
|
||||
remote-endpoint = <&pmic_glink_ss0_ss_in>;
|
||||
remote-endpoint = <&retimer_ss0_ss_in>;
|
||||
};
|
||||
|
||||
&usb_1_ss1_hsphy {
|
||||
|
|
@ -946,7 +1300,35 @@ &usb_1_ss1_dwc3_hs {
|
|||
};
|
||||
|
||||
&usb_1_ss1_qmpphy_out {
|
||||
remote-endpoint = <&pmic_glink_ss1_ss_in>;
|
||||
remote-endpoint = <&retimer_ss1_ss_in>;
|
||||
};
|
||||
|
||||
&usb_1_ss2_qmpphy {
|
||||
vdda-phy-supply = <&vreg_l2j_1p2>;
|
||||
vdda-pll-supply = <&vreg_l2d_0p9>;
|
||||
|
||||
/delete-property/ mode-switch;
|
||||
/delete-property/ orientation-switch;
|
||||
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/delete-node/ endpoint;
|
||||
|
||||
usb_1_ss2_qmpphy_out_dp: endpoint@0 {
|
||||
reg = <0>;
|
||||
|
||||
data-lanes = <3 2 1 0>;
|
||||
remote-endpoint = <&hdmi_bridge_dp_in>;
|
||||
};
|
||||
|
||||
/* No USB3 lanes connected */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb_2 {
|
||||
|
|
|
|||
|
|
@ -82,6 +82,9 @@ &gpu_zap_shader {
|
|||
};
|
||||
|
||||
&pcie4_port0 {
|
||||
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
wifi@0 {
|
||||
compatible = "pci17cb,1107";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
|
|
|
|||
|
|
@ -941,9 +941,6 @@ &mdss_dp3_phy {
|
|||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
|
@ -958,6 +955,9 @@ &pcie4_phy {
|
|||
};
|
||||
|
||||
&pcie4_port0 {
|
||||
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
wifi@0 {
|
||||
compatible = "pci17cb,1107";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
|
|
@ -975,9 +975,6 @@ wifi@0 {
|
|||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vddpe-3v3-supply = <&vreg_nvme>;
|
||||
|
||||
pinctrl-0 = <&pcie6a_default>;
|
||||
|
|
@ -993,6 +990,11 @@ &pcie6a_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a_port0 {
|
||||
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pm8550_gpios {
|
||||
rtmr0_default: rtmr0-reset-n-active-state {
|
||||
pins = "gpio10";
|
||||
|
|
|
|||
|
|
@ -1160,9 +1160,6 @@ wifi@0 {
|
|||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vddpe-3v3-supply = <&vreg_nvme>;
|
||||
|
||||
pinctrl-0 = <&pcie6a_default>;
|
||||
|
|
@ -1178,6 +1175,11 @@ &pcie6a_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a_port0 {
|
||||
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pm8550_gpios {
|
||||
rtmr0_default: rtmr0-reset-n-active-state {
|
||||
pins = "gpio10";
|
||||
|
|
|
|||
1515
arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts
Normal file
1515
arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts
Normal file
File diff suppressed because it is too large
Load Diff
19
arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts
Normal file
19
arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2025 Dale Whinham <daleyo@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "hamoa.dtsi"
|
||||
#include "x1-microsoft-denali.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Microsoft Surface Pro 11th Edition (OLED)";
|
||||
compatible = "microsoft,denali-oled", "microsoft,denali",
|
||||
"qcom,x1e80100";
|
||||
};
|
||||
|
||||
&panel {
|
||||
compatible = "samsung,atna30dw01", "samsung,atna33xc20";
|
||||
};
|
||||
|
|
@ -1094,9 +1094,6 @@ &mdss_dp3_phy {
|
|||
};
|
||||
|
||||
&pcie3 {
|
||||
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&pcie3_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
|
@ -1112,6 +1109,11 @@ &pcie3_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3_port0 {
|
||||
reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1124,6 +1126,9 @@ &pcie4_phy {
|
|||
};
|
||||
|
||||
&pcie4_port0 {
|
||||
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
wifi@0 {
|
||||
compatible = "pci17cb,1107";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
|
|
@ -1141,9 +1146,6 @@ wifi@0 {
|
|||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vddpe-3v3-supply = <&vreg_nvme>;
|
||||
|
||||
pinctrl-0 = <&pcie6a_default>;
|
||||
|
|
@ -1159,6 +1161,11 @@ &pcie6a_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a_port0 {
|
||||
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pm8550_gpios {
|
||||
rtmr0_default: rtmr0-reset-n-active-state {
|
||||
pins = "gpio10";
|
||||
|
|
|
|||
|
|
@ -979,8 +979,6 @@ pm_sde7_main_3p3_en: pcie-main-3p3-default-state {
|
|||
&pcie3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie3_default>;
|
||||
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -992,16 +990,16 @@ &pcie3_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3_port {
|
||||
&pcie3_port0 {
|
||||
vpcie12v-supply = <&vreg_pcie_12v>;
|
||||
vpcie3v3-supply = <&vreg_pcie_3v3>;
|
||||
vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>;
|
||||
|
||||
reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
|
@ -1016,6 +1014,9 @@ &pcie4_phy {
|
|||
};
|
||||
|
||||
&pcie4_port0 {
|
||||
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
wifi@0 {
|
||||
compatible = "pci17cb,1107";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
|
|
@ -1033,9 +1034,6 @@ wifi@0 {
|
|||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vddpe-3v3-supply = <&vreg_nvme>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -1051,6 +1049,11 @@ &pcie6a_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a_port0 {
|
||||
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&qupv3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -78,6 +78,47 @@ camera {
|
|||
vdd-supply = <&vreg_cam_5p0>;
|
||||
};
|
||||
|
||||
hdmi-bridge {
|
||||
compatible = "realtek,rtd2171";
|
||||
|
||||
enable-gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&hdmi_hpd_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi_bridge_dp_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hdmi_bridge_tmds_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con: endpoint {
|
||||
remote-endpoint = <&hdmi_bridge_tmds_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
|
@ -1038,6 +1079,14 @@ &mdss_dp1_out {
|
|||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
|
||||
};
|
||||
|
||||
&mdss_dp2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dp2_out {
|
||||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
|
||||
};
|
||||
|
||||
&mdss_dp3 {
|
||||
/delete-property/ #sound-dai-cells;
|
||||
|
||||
|
|
@ -1327,6 +1376,19 @@ hall_int_n_default: hall-int-n-state {
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
hdmi_bridge_en: hdmi-bridge-en-state {
|
||||
pins = "gpio120";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
hdmi_hpd_default: hdmi-hpd-default-state {
|
||||
pins = "gpio126";
|
||||
function = "usb2_dp";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
kybd_default: kybd-default-state {
|
||||
pins = "gpio67";
|
||||
function = "gpio";
|
||||
|
|
@ -1560,6 +1622,8 @@ &usb_1_ss2_dwc3 {
|
|||
maximum-speed = "high-speed";
|
||||
phys = <&usb_1_ss2_hsphy>;
|
||||
phy-names = "usb2-phy";
|
||||
|
||||
/delete-property/ port@1;
|
||||
};
|
||||
|
||||
&usb_1_ss2_hsphy {
|
||||
|
|
@ -1571,6 +1635,32 @@ &usb_1_ss2_hsphy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss2_qmpphy {
|
||||
vdda-phy-supply = <&vreg_l2j_1p2>;
|
||||
vdda-pll-supply = <&vreg_l2d_0p9>;
|
||||
|
||||
/delete-property/ mode-switch;
|
||||
/delete-property/ orientation-switch;
|
||||
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/delete-node/ endpoint;
|
||||
|
||||
usb_1_ss2_qmpphy_out_dp: endpoint@0 {
|
||||
reg = <0>;
|
||||
|
||||
data-lanes = <0 1 2 3>;
|
||||
remote-endpoint = <&hdmi_bridge_dp_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user