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pinctrl: renesas: Updates for v6.20
- Add support for GPIO IRQs on RZ/T2H and RZ/N2H. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCaWoT+gAKCRCKwlD9ZEnx cEo+AP4qLfOTmmOU3TD2z5OHCUcoOczfGVtYTZWT2XD/w5Z67QEA0c8I5JbSaI0S zr6RbyfNx0QTyqEuuENnPzOVo5OrTQY= =2Zkc -----END PGP SIGNATURE----- Merge tag 'renesas-pinctrl-for-v6.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.20 - Add support for GPIO IRQs on RZ/T2H and RZ/N2H. Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Linus Walleij
commit
43519f5457
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@ -49,6 +49,17 @@ properties:
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gpio-ranges:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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description:
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The first cell contains the global GPIO port index, constructed using the
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RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
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and the second cell is used to specify the flag.
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E.g. "interrupts = <RZT2H_GPIO(8, 6) IRQ_TYPE_EDGE_FALLING>;" if P08_6 is
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being used as an interrupt.
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clocks:
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maxItems: 1
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@ -139,6 +150,8 @@ examples:
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 288>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&cpg>;
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serial0-pins {
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@ -308,9 +308,11 @@ config PINCTRL_RZT2H
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bool "pin control support for RZ/N2H and RZ/T2H" if COMPILE_TEST
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depends on 64BIT && OF
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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select GENERIC_PINCTRL_GROUPS
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select GENERIC_PINMUX_FUNCTIONS
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select GENERIC_PINCONF
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select IRQ_DOMAIN_HIERARCHY
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help
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This selects GPIO and pinctrl driver for Renesas RZ/T2H
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platforms.
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@ -18,6 +18,7 @@
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spinlock.h>
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@ -51,6 +52,7 @@
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#define PFC_MASK GENMASK_ULL(5, 0)
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#define PFC_PIN_MASK(pin) (PFC_MASK << ((pin) * 8))
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#define PFC_FUNC_INTERRUPT 0
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/*
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* Use 16 lower bits [15:0] for pin identifier
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@ -64,6 +66,9 @@
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#define RZT2H_MAX_SAFETY_PORTS 12
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#define RZT2H_INTERRUPTS_START 16
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#define RZT2H_INTERRUPTS_NUM 17
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struct rzt2h_pinctrl_data {
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unsigned int n_port_pins;
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const u8 *port_pin_configs;
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@ -79,9 +84,11 @@ struct rzt2h_pinctrl {
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struct device *dev;
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struct gpio_chip gpio_chip;
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struct pinctrl_gpio_range gpio_range;
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DECLARE_BITMAP(used_irqs, RZT2H_INTERRUPTS_NUM);
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spinlock_t lock; /* lock read/write registers */
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struct mutex mutex; /* serialize adding groups and functions */
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bool safety_port_enabled;
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atomic_t wakeup_path;
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};
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#define RZT2H_GET_BASE(pctrl, port) \
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@ -119,6 +126,19 @@ static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int offset)
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return (pincfg & BIT(pin)) ? 0 : -EINVAL;
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}
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static void rzt2h_pinctrl_set_gpio_en(struct rzt2h_pinctrl *pctrl,
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u8 port, u8 pin, bool en)
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{
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u8 reg = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
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if (en)
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reg &= ~BIT(pin);
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else
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reg |= BIT(pin);
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rzt2h_pinctrl_writeb(pctrl, port, reg, PMC(port));
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}
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static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl,
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u8 port, u8 pin, u8 func)
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{
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@ -133,8 +153,7 @@ static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl,
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rzt2h_pinctrl_writew(pctrl, port, reg16, PM(port));
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/* Temporarily switch to GPIO mode with PMC register */
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reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
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rzt2h_pinctrl_writeb(pctrl, port, reg16 & ~BIT(pin), PMC(port));
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rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true);
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/* Select Pin function mode with PFC register */
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reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port));
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@ -142,8 +161,7 @@ static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl,
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rzt2h_pinctrl_writeq(pctrl, port, reg64 | ((u64)func << (pin * 8)), PFC(port));
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/* Switch to Peripheral pin function with PMC register */
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reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
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rzt2h_pinctrl_writeb(pctrl, port, reg16 | BIT(pin), PMC(port));
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rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false);
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}
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static int rzt2h_pinctrl_set_mux(struct pinctrl_dev *pctldev,
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@ -447,7 +465,6 @@ static int rzt2h_gpio_request(struct gpio_chip *chip, unsigned int offset)
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u8 port = RZT2H_PIN_ID_TO_PORT(offset);
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u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
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int ret;
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u8 reg;
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ret = rzt2h_validate_pin(pctrl, offset);
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if (ret)
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@ -460,9 +477,7 @@ static int rzt2h_gpio_request(struct gpio_chip *chip, unsigned int offset)
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guard(spinlock_irqsave)(&pctrl->lock);
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/* Select GPIO mode in PMC Register */
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reg = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
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reg &= ~BIT(bit);
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rzt2h_pinctrl_writeb(pctrl, port, reg, PMC(port));
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rzt2h_pinctrl_set_gpio_en(pctrl, port, bit, true);
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return 0;
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}
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@ -486,6 +501,7 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
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struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
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u8 port = RZT2H_PIN_ID_TO_PORT(offset);
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u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
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u64 reg64;
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u16 reg;
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int ret;
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@ -493,8 +509,25 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
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if (ret)
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return ret;
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if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit))
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guard(spinlock_irqsave)(&pctrl->lock);
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if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) {
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/*
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* When a GPIO is being requested as an IRQ, the pinctrl
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* framework expects to be able to read the GPIO's direction.
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* IRQ function is separate from GPIO, and enabling it takes the
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* pin out of GPIO mode.
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* At this point, .child_to_parent_hwirq() has already been
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* called to enable the IRQ function.
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* Default to input direction for IRQ function.
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*/
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reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port));
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reg64 = (reg64 >> (bit * 8)) & PFC_MASK;
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if (reg64 == PFC_FUNC_INTERRUPT)
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return GPIO_LINE_DIRECTION_IN;
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return -EINVAL;
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}
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reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
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reg = (reg >> (bit * 2)) & PM_MASK;
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@ -617,14 +650,185 @@ static const char * const rzt2h_gpio_names[] = {
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"P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7",
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};
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/*
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* Interrupts 0-15 are for INTCPUn, which are not exposed externally.
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* Interrupts 16-31 are for IRQn. SEI is 32.
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* This table matches the information found in User Manual's Section
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* 17.5, Multiplexed Pin Configurations, Tables 17.5 to 17.40, on the
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* Interrupt rows.
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* RZ/N2H has the same GPIO to IRQ mapping, except for the pins which
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* are not present.
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*/
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static const u8 rzt2h_gpio_irq_map[] = {
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32, 16, 17, 18, 19, 0, 20, 21,
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22, 0, 0, 0, 0, 0, 0, 0,
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23, 24, 25, 26, 27, 0, 0, 0,
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0, 0, 28, 29, 30, 31, 0, 0,
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0, 0, 0, 0, 0, 32, 16, 17,
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18, 19, 20, 21, 22, 0, 0, 0,
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0, 0, 24, 25, 26, 27, 0, 28,
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29, 30, 31, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 24, 32, 16,
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0, 0, 0, 0, 0, 0, 0, 0,
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20, 23, 17, 18, 19, 0, 16, 25,
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29, 20, 21, 22, 23, 0, 0, 0,
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0, 0, 0, 0, 17, 0, 0, 18,
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0, 0, 19, 0, 0, 20, 0, 30,
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21, 0, 0, 22, 0, 0, 24, 25,
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0, 0, 0, 0, 0, 16, 17, 0,
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18, 0, 0, 26, 27, 0, 0, 0,
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28, 29, 30, 31, 0, 0, 0, 0,
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23, 31, 32, 16, 17, 18, 19, 20,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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27, 0, 0, 21, 22, 23, 24, 25,
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26, 0, 0, 0, 0, 0, 0, 0,
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27, 28, 29, 30, 31, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 28, 32, 16,
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17, 18, 19, 0, 0, 0, 0, 20,
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21, 22, 23, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 24, 25, 0, 0,
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0, 0, 26, 27, 0, 0, 0, 30,
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0, 29, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 28, 29, 30, 31, 0,
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0, 0, 0, 0, 0, 0, 0, 30,
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0, 0, 0, 0, 0, 0, 0, 0,
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};
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static void rzt2h_gpio_irq_disable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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unsigned int hwirq = irqd_to_hwirq(d);
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irq_chip_disable_parent(d);
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gpiochip_disable_irq(gc, hwirq);
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}
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static void rzt2h_gpio_irq_enable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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unsigned int hwirq = irqd_to_hwirq(d);
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gpiochip_enable_irq(gc, hwirq);
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irq_chip_enable_parent(d);
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}
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static int rzt2h_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct rzt2h_pinctrl *pctrl = container_of(gc, struct rzt2h_pinctrl, gpio_chip);
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int ret;
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ret = irq_chip_set_wake_parent(d, on);
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if (ret)
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return ret;
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/*
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* If any of the IRQs are in use, put the entire pin controller on the
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* device wakeup path.
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*/
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if (on)
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atomic_inc(&pctrl->wakeup_path);
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else
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atomic_dec(&pctrl->wakeup_path);
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return 0;
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}
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static const struct irq_chip rzt2h_gpio_irqchip = {
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.name = "rzt2h-gpio",
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.irq_disable = rzt2h_gpio_irq_disable,
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.irq_enable = rzt2h_gpio_irq_enable,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_set_type = irq_chip_set_type_parent,
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.irq_set_wake = rzt2h_gpio_irq_set_wake,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static int rzt2h_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
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unsigned int child,
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unsigned int child_type,
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unsigned int *parent,
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unsigned int *parent_type)
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{
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struct rzt2h_pinctrl *pctrl = gpiochip_get_data(gc);
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u8 port = RZT2H_PIN_ID_TO_PORT(child);
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u8 pin = RZT2H_PIN_ID_TO_PIN(child);
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u8 parent_irq;
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parent_irq = rzt2h_gpio_irq_map[child];
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if (parent_irq < RZT2H_INTERRUPTS_START)
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return -EINVAL;
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if (test_and_set_bit(parent_irq - RZT2H_INTERRUPTS_START,
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pctrl->used_irqs))
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return -EBUSY;
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rzt2h_pinctrl_set_pfc_mode(pctrl, port, pin, PFC_FUNC_INTERRUPT);
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*parent = parent_irq;
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*parent_type = child_type;
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return 0;
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}
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static void rzt2h_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct rzt2h_pinctrl *pctrl = container_of(gc, struct rzt2h_pinctrl, gpio_chip);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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u8 port = RZT2H_PIN_ID_TO_PORT(hwirq);
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u8 pin = RZT2H_PIN_ID_TO_PIN(hwirq);
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if (test_and_clear_bit(hwirq - RZT2H_INTERRUPTS_START, pctrl->used_irqs))
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rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false);
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irq_domain_free_irqs_common(domain, virq, nr_irqs);
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}
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static void rzt2h_gpio_init_irq_valid_mask(struct gpio_chip *gc,
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unsigned long *valid_mask,
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unsigned int ngpios)
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{
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struct rzt2h_pinctrl *pctrl = gpiochip_get_data(gc);
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unsigned int offset;
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for (offset = 0; offset < ngpios; offset++) {
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if (!rzt2h_gpio_irq_map[offset] || rzt2h_validate_pin(pctrl, offset))
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clear_bit(offset, valid_mask);
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}
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}
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static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl)
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{
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struct pinctrl_gpio_range *range = &pctrl->gpio_range;
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struct gpio_chip *chip = &pctrl->gpio_chip;
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struct device_node *np = pctrl->dev->of_node;
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struct irq_domain *parent_domain;
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struct device *dev = pctrl->dev;
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struct of_phandle_args of_args;
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struct device_node *parent_np;
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struct gpio_irq_chip *girq;
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int ret;
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parent_np = of_irq_find_parent(np);
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if (!parent_np)
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return -ENXIO;
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parent_domain = irq_find_host(parent_np);
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of_node_put(parent_np);
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if (!parent_domain)
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return -EPROBE_DEFER;
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ret = of_parse_phandle_with_fixed_args(dev->of_node, "gpio-ranges", 3, 0, &of_args);
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if (ret)
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return dev_err_probe(dev, ret, "Unable to parse gpio-ranges\n");
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|
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@ -648,6 +852,17 @@ static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl)
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chip->set = rzt2h_gpio_set;
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chip->label = dev_name(dev);
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if (of_property_present(np, "interrupt-controller")) {
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girq = &chip->irq;
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gpio_irq_chip_set_chip(girq, &rzt2h_gpio_irqchip);
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girq->fwnode = dev_fwnode(pctrl->dev);
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girq->parent_domain = parent_domain;
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girq->child_to_parent_hwirq = rzt2h_gpio_child_to_parent_hwirq;
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girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell;
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girq->child_irq_domain_ops.free = rzt2h_gpio_irq_domain_free;
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girq->init_valid_mask = rzt2h_gpio_init_irq_valid_mask;
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}
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range->id = 0;
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range->pin_base = 0;
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range->base = 0;
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|
|
@ -792,10 +1007,25 @@ static const struct of_device_id rzt2h_pinctrl_of_table[] = {
|
|||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int rzt2h_pinctrl_suspend_noirq(struct device *dev)
|
||||
{
|
||||
struct rzt2h_pinctrl *pctrl = dev_get_drvdata(dev);
|
||||
|
||||
if (atomic_read(&pctrl->wakeup_path))
|
||||
device_set_wakeup_path(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops rzt2h_pinctrl_pm_ops = {
|
||||
NOIRQ_SYSTEM_SLEEP_PM_OPS(rzt2h_pinctrl_suspend_noirq, NULL)
|
||||
};
|
||||
|
||||
static struct platform_driver rzt2h_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.of_match_table = of_match_ptr(rzt2h_pinctrl_of_table),
|
||||
.pm = pm_sleep_ptr(&rzt2h_pinctrl_pm_ops),
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = rzt2h_pinctrl_probe,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user