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Merge "pwm: pwm-qti-lpg: Add Support for high resolution PWM"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
42fbe3bc58
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@ -1773,10 +1773,47 @@ static int adc5_gen3_exit(struct platform_device *pdev)
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return 0;
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}
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static int adc5_gen3_freeze(struct device *dev)
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{
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struct adc5_chip *adc = dev_get_drvdata(dev);
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int i = 0;
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mutex_lock(&adc->lock);
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for (i = 0; i < adc->num_sdams; i++)
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devm_free_irq(dev, adc->base[i].irq, adc);
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mutex_unlock(&adc->lock);
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return 0;
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}
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static int adc5_gen3_restore(struct device *dev)
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{
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struct adc5_chip *adc = dev_get_drvdata(dev);
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int i = 0;
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int ret = 0;
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for (i = 0; i < adc->num_sdams; i++) {
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ret = devm_request_irq(dev, adc->base[i].irq, adc5_gen3_isr,
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0, adc->base[i].irq_name, adc);
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if (ret < 0)
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return ret;
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}
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return ret;
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}
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static const struct dev_pm_ops adc5_gen3_pm_ops = {
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.freeze = adc5_gen3_freeze,
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.restore = adc5_gen3_restore,
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};
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static struct platform_driver adc5_gen3_driver = {
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.driver = {
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.name = "qcom-spmi-adc5-gen3",
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.of_match_table = adc5_match_table,
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.pm = &adc5_gen3_pm_ops,
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},
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.probe = adc5_gen3_probe,
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.remove = adc5_gen3_exit,
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@ -62,14 +62,18 @@
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/* REG_LPG_PERPH_SUBTYPE */
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#define SUBTYPE_PWM 0x0b
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#define SUBTYPE_HI_RES_PWM 0x0c
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#define SUBTYPE_LPG_LITE 0x11
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/* REG_LPG_PWM_SIZE_CLK */
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#define LPG_PWM_SIZE_LPG_MASK BIT(4)
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#define LPG_PWM_SIZE_PWM_MASK BIT(2)
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#define LPG_PWM_SIZE_PWM_HI_RES_MASK GENMASK(6, 4)
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#define LPG_PWM_SIZE_LPG_SHIFT 4
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#define LPG_PWM_SIZE_PWM_SHIFT 2
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#define LPG_PWM_SIZE_PWM_HI_RES_SHIFT 4
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#define LPG_PWM_CLK_FREQ_SEL_MASK GENMASK(1, 0)
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#define LPG_PWM_HI_RES_CLK_FREQ_SEL_MASK GENMASK(2, 0)
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/* REG_LPG_PWM_FREQ_PREDIV_CLK */
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#define LPG_PWM_FREQ_PREDIV_MASK GENMASK(6, 5)
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@ -84,6 +88,7 @@
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/* REG_LPG_PWM_VALUE_MSB */
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#define LPG_PWM_VALUE_MSB_MASK BIT(0)
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#define LPG_PWM_HI_RES_VALUE_MSB_MASK GENMASK(7, 0)
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/* REG_LPG_ENABLE_CONTROL */
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#define LPG_EN_LPG_OUT_BIT BIT(7)
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@ -97,7 +102,9 @@
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#define LPG_PWM_VALUE_SYNC BIT(0)
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#define NUM_PWM_SIZE 2
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#define NUM_PWM_HI_RES_SIZE 8
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#define NUM_PWM_CLK 3
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#define NUM_PWM_HI_RES_CLK 4
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#define NUM_CLK_PREDIV 4
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#define NUM_PWM_EXP 8
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@ -147,9 +154,12 @@ enum ppg_num_nvmems {
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};
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static const int pwm_size[NUM_PWM_SIZE] = {6, 9};
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static const int pwm_hi_res_size[NUM_PWM_HI_RES_SIZE] = {8, 9, 10, 11, 12, 13, 14, 15};
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static const int clk_freq_hz[NUM_PWM_CLK] = {1024, 32768, 19200000};
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static const int clk_freq_hz_hi_res[NUM_PWM_HI_RES_CLK] = {1024, 32768, 19200000, 76800000};
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/* clk_period_ns = NSEC_PER_SEC / clk_freq_hz */
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static const int clk_period_ns[NUM_PWM_CLK] = {976562, 30517, 52};
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static const int clk_period_ns_hi_res[NUM_PWM_HI_RES_CLK] = {976562, 30517, 52, 13};
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static const int clk_prediv[NUM_CLK_PREDIV] = {1, 3, 5, 6};
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static const int pwm_exponent[NUM_PWM_EXP] = {0, 1, 2, 3, 4, 5, 6, 7};
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@ -428,10 +438,18 @@ static int qpnp_lpg_set_pwm_config(struct qpnp_lpg_channel *lpg)
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u8 val, mask, shift;
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int pwm_size_idx, pwm_clk_idx, prediv_idx, clk_exp_idx;
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pwm_size_idx = __find_index_in_array(lpg->pwm_config.pwm_size,
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pwm_size, ARRAY_SIZE(pwm_size));
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pwm_clk_idx = __find_index_in_array(lpg->pwm_config.pwm_clk,
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clk_freq_hz, ARRAY_SIZE(clk_freq_hz));
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if (lpg->subtype == SUBTYPE_HI_RES_PWM) {
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pwm_size_idx = __find_index_in_array(lpg->pwm_config.pwm_size,
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pwm_hi_res_size, ARRAY_SIZE(pwm_hi_res_size));
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pwm_clk_idx = __find_index_in_array(lpg->pwm_config.pwm_clk,
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clk_freq_hz_hi_res, ARRAY_SIZE(clk_freq_hz_hi_res));
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} else {
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pwm_size_idx = __find_index_in_array(lpg->pwm_config.pwm_size,
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pwm_size, ARRAY_SIZE(pwm_size));
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pwm_clk_idx = __find_index_in_array(lpg->pwm_config.pwm_clk,
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clk_freq_hz, ARRAY_SIZE(clk_freq_hz));
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}
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prediv_idx = __find_index_in_array(lpg->pwm_config.prediv,
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clk_prediv, ARRAY_SIZE(clk_prediv));
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clk_exp_idx = __find_index_in_array(lpg->pwm_config.clk_exp,
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@ -445,14 +463,16 @@ static int qpnp_lpg_set_pwm_config(struct qpnp_lpg_channel *lpg)
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pwm_clk_idx += 1;
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if (lpg->subtype == SUBTYPE_PWM) {
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shift = LPG_PWM_SIZE_PWM_SHIFT;
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mask = LPG_PWM_SIZE_PWM_MASK;
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mask = LPG_PWM_SIZE_PWM_MASK | LPG_PWM_CLK_FREQ_SEL_MASK;
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} else if (lpg->subtype == SUBTYPE_HI_RES_PWM) {
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shift = LPG_PWM_SIZE_PWM_HI_RES_SHIFT;
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mask = LPG_PWM_SIZE_PWM_HI_RES_MASK | LPG_PWM_HI_RES_CLK_FREQ_SEL_MASK;
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} else {
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shift = LPG_PWM_SIZE_LPG_SHIFT;
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mask = LPG_PWM_SIZE_LPG_MASK;
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mask = LPG_PWM_SIZE_LPG_MASK | LPG_PWM_CLK_FREQ_SEL_MASK;
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}
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val = pwm_size_idx << shift | pwm_clk_idx;
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mask |= LPG_PWM_CLK_FREQ_SEL_MASK;
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rc = qpnp_lpg_masked_write(lpg, REG_LPG_PWM_SIZE_CLK, mask, val);
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if (rc < 0) {
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dev_err(lpg->chip->dev, "Write LPG_PWM_SIZE_CLK failed, rc=%d\n",
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@ -473,7 +493,10 @@ static int qpnp_lpg_set_pwm_config(struct qpnp_lpg_channel *lpg)
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return 0;
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val = lpg->pwm_config.pwm_value >> 8;
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mask = LPG_PWM_VALUE_MSB_MASK;
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if (lpg->subtype == SUBTYPE_HI_RES_PWM)
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mask = LPG_PWM_HI_RES_VALUE_MSB_MASK;
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else
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mask = LPG_PWM_VALUE_MSB_MASK;
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rc = qpnp_lpg_masked_write(lpg, REG_LPG_PWM_VALUE_MSB, mask, val);
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if (rc < 0) {
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dev_err(lpg->chip->dev, "Write LPG_PWM_VALUE_MSB failed, rc=%d\n",
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@ -506,8 +529,13 @@ static int qpnp_lpg_set_pfm_config(struct qpnp_lpg_channel *lpg)
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u8 val, mask;
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int pwm_clk_idx, clk_exp_idx;
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pwm_clk_idx = __find_index_in_array(lpg->pwm_config.pwm_clk,
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clk_freq_hz, ARRAY_SIZE(clk_freq_hz));
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if (lpg->subtype == SUBTYPE_HI_RES_PWM)
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pwm_clk_idx = __find_index_in_array(lpg->pwm_config.pwm_clk,
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clk_freq_hz_hi_res, ARRAY_SIZE(clk_freq_hz_hi_res));
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else
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pwm_clk_idx = __find_index_in_array(lpg->pwm_config.pwm_clk,
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clk_freq_hz, ARRAY_SIZE(clk_freq_hz));
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clk_exp_idx = __find_index_in_array(lpg->pwm_config.clk_exp,
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pwm_exponent, ARRAY_SIZE(pwm_exponent));
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@ -518,7 +546,11 @@ static int qpnp_lpg_set_pfm_config(struct qpnp_lpg_channel *lpg)
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pwm_clk_idx += 1;
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val = pwm_clk_idx;
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mask = LPG_PWM_CLK_FREQ_SEL_MASK;
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if (lpg->subtype == SUBTYPE_HI_RES_PWM)
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mask = LPG_PWM_HI_RES_CLK_FREQ_SEL_MASK;
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else
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mask = LPG_PWM_CLK_FREQ_SEL_MASK;
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rc = qpnp_lpg_masked_write(lpg, REG_LPG_PWM_SIZE_CLK, mask, val);
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if (rc < 0) {
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dev_err(lpg->chip->dev, "Write LPG_PWM_SIZE_CLK failed, rc=%d\n",
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@ -837,13 +869,14 @@ static int __qpnp_lpg_calc_pwm_period(u64 period_ns,
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{
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struct qpnp_lpg_channel *lpg = container_of(pwm_config,
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struct qpnp_lpg_channel, pwm_config);
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struct lpg_pwm_config configs[NUM_PWM_SIZE];
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struct lpg_pwm_config configs[NUM_PWM_HI_RES_SIZE];
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int i, j, m, n;
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u64 tmp1, tmp2;
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u64 clk_period_ns = 0, pwm_clk_period_ns;
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u64 clk_delta_ns = U64_MAX, min_clk_delta_ns = U64_MAX;
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u64 pwm_period_delta = U64_MAX, min_pwm_period_delta = U64_MAX;
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int pwm_size_step;
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int pwm_size_step, clk_len, pwm_size_len;
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const int *pwm_size_arr, *clk_freq_hz_arr;
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/*
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* (2^pwm_size) * (2^pwm_exp) * prediv * NSEC_PER_SEC
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@ -852,20 +885,34 @@ static int __qpnp_lpg_calc_pwm_period(u64 period_ns,
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*
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* Searching the closest settings for the requested PWM period.
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*/
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if (lpg->chip->use_sdam)
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if (lpg->subtype == SUBTYPE_HI_RES_PWM) {
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pwm_size_arr = pwm_hi_res_size;
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pwm_size_len = NUM_PWM_HI_RES_SIZE;
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clk_freq_hz_arr = clk_freq_hz_hi_res;
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clk_len = NUM_PWM_HI_RES_CLK;
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} else {
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pwm_size_arr = pwm_size;
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pwm_size_len = NUM_PWM_SIZE;
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clk_freq_hz_arr = clk_freq_hz;
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clk_len = NUM_PWM_CLK;
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}
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if (lpg->chip->use_sdam) {
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/* SDAM pattern control can only use 9 bit resolution */
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n = 1;
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pwm_size_len = 2;
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}
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else
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n = 0;
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for (; n < ARRAY_SIZE(pwm_size); n++) {
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pwm_clk_period_ns = period_ns >> pwm_size[n];
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for (i = ARRAY_SIZE(clk_freq_hz) - 1; i >= 0; i--) {
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for (j = 0; j < ARRAY_SIZE(clk_prediv); j++) {
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for (; n < pwm_size_len; n++) {
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pwm_clk_period_ns = period_ns >> pwm_size_arr[n];
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for (i = clk_len - 1; i >= 0; i--) {
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for (j = 0; j < clk_len; j++) {
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for (m = 0; m < ARRAY_SIZE(pwm_exponent); m++) {
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tmp1 = 1 << pwm_exponent[m];
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tmp1 *= clk_prediv[j];
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tmp2 = NSEC_PER_SEC;
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do_div(tmp2, clk_freq_hz[i]);
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do_div(tmp2, clk_freq_hz_arr[i]);
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clk_period_ns = tmp1 * tmp2;
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@ -879,13 +926,13 @@ static int __qpnp_lpg_calc_pwm_period(u64 period_ns,
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min_clk_delta_ns
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= clk_delta_ns;
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configs[n].pwm_clk
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= clk_freq_hz[i];
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= clk_freq_hz_arr[i];
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configs[n].prediv
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= clk_prediv[j];
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configs[n].clk_exp
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= pwm_exponent[m];
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configs[n].pwm_size
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= pwm_size[n];
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= pwm_size_arr[n];
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configs[n].best_period_ns
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= clk_period_ns;
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}
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@ -893,9 +940,9 @@ static int __qpnp_lpg_calc_pwm_period(u64 period_ns,
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}
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}
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configs[n].best_period_ns *= 1 << pwm_size[n];
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configs[n].best_period_ns *= 1 << pwm_size_arr[n];
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/* Find the closest setting for PWM period */
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pwm_period_delta = min_clk_delta_ns << pwm_size[n];
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pwm_period_delta = min_clk_delta_ns << pwm_size_arr[n];
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if (pwm_period_delta < min_pwm_period_delta) {
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min_pwm_period_delta = pwm_period_delta;
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memcpy(pwm_config, &configs[n],
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@ -904,12 +951,12 @@ static int __qpnp_lpg_calc_pwm_period(u64 period_ns,
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}
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/* Larger PWM size can achieve better resolution for PWM duty */
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for (n = ARRAY_SIZE(pwm_size) - 1; n > 0; n--) {
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if (pwm_config->pwm_size >= pwm_size[n])
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for (n = pwm_size_len - 1; n > 0; n--) {
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if (pwm_config->pwm_size >= pwm_size_arr[n])
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break;
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pwm_size_step = pwm_size[n] - pwm_config->pwm_size;
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pwm_size_step = pwm_size_arr[n] - pwm_config->pwm_size;
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if (pwm_config->clk_exp >= pwm_size_step) {
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pwm_config->pwm_size = pwm_size[n];
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pwm_config->pwm_size = pwm_size_arr[n];
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pwm_config->clk_exp -= pwm_size_step;
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}
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}
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@ -939,10 +986,13 @@ static void __qpnp_lpg_calc_pwm_duty(u64 period_ns, u64 duty_ns,
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static int __qpnp_lpg_calc_pfm_period(u64 period_ns,
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struct lpg_pwm_config *pwm_config)
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{
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int clk, exp, lsb;
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struct qpnp_lpg_channel *lpg = container_of(pwm_config,
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struct qpnp_lpg_channel, pwm_config);
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int clk, exp, lsb, clk_len;
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int best_clk = 0, best_exp = 0, best_lsb = -EINVAL;
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u64 lsb_tmp, period_tmp, curr_p_err, last_p_err = 0;
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u64 min_p_err = U64_MAX;
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const int *clk_freq_hz_arr, *clk_period_ns_arr;
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/*
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* 2 * (pwm_value_lsb + 1) * (2^pwm_exp) * NSEC_PER_SEC
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@ -954,16 +1004,27 @@ static int __qpnp_lpg_calc_pfm_period(u64 period_ns,
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* period. Store the triplet values that yield the closest value to
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* desired period.
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*/
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for (clk = 0; clk < NUM_PWM_CLK; clk++) {
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if (lpg->subtype == SUBTYPE_HI_RES_PWM) {
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clk_freq_hz_arr = clk_freq_hz_hi_res;
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clk_period_ns_arr = clk_period_ns_hi_res;
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clk_len = NUM_PWM_HI_RES_CLK;
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} else {
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clk_freq_hz_arr = clk_freq_hz;
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clk_period_ns_arr = clk_period_ns;
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clk_len = NUM_PWM_CLK;
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}
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for (clk = 0; clk < clk_len; clk++) {
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last_p_err = U64_MAX;
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for (exp = 0; exp < NUM_PWM_EXP; exp++) {
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lsb_tmp = div_u64(period_ns, clk_period_ns[clk]);
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lsb_tmp = div_u64(period_ns, clk_period_ns_arr[clk]);
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lsb_tmp >>= (exp + 1);
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lsb = lsb_tmp - 1;
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if (lsb >= 0 && lsb <= U8_MAX) {
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period_tmp = (lsb + 1);
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period_tmp <<= (exp + 1);
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period_tmp *= clk_period_ns[clk];
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period_tmp *= clk_period_ns_arr[clk];
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curr_p_err = abs(period_ns - period_tmp);
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if (curr_p_err < min_p_err) {
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@ -994,7 +1055,7 @@ static int __qpnp_lpg_calc_pfm_period(u64 period_ns,
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return -EINVAL;
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}
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pwm_config->pwm_clk = clk_freq_hz[best_clk];
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pwm_config->pwm_clk = clk_freq_hz_arr[best_clk];
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pwm_config->clk_exp = pwm_exponent[best_exp];
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pwm_config->pwm_value = best_lsb;
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@ -1794,7 +1855,8 @@ static int qpnp_lpg_parse_pfm_support(struct qpnp_lpg_chip *chip)
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chan_idx--; /* zero-based indexing */
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if (chip->lpgs[chan_idx].subtype == SUBTYPE_PWM) {
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if (chip->lpgs[chan_idx].subtype == SUBTYPE_PWM ||
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chip->lpgs[chan_idx].subtype == SUBTYPE_HI_RES_PWM) {
|
||||
rc = qpnp_lpg_read(&chip->lpgs[chan_idx],
|
||||
REG_PWM_STATUS1, &val);
|
||||
if (rc < 0) {
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __QCOM_RPMH_REGULATOR_LEVELS_H
|
||||
|
|
@ -9,8 +10,11 @@
|
|||
/* These levels may be used for ARC type RPMh regulators. */
|
||||
#define RPMH_REGULATOR_LEVEL_RETENTION 16
|
||||
#define RPMH_REGULATOR_LEVEL_MIN_SVS 48
|
||||
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52
|
||||
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56
|
||||
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60
|
||||
#define RPMH_REGULATOR_LEVEL_LOW_SVS 64
|
||||
#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72
|
||||
#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80
|
||||
#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96
|
||||
#define RPMH_REGULATOR_LEVEL_SVS 128
|
||||
|
|
@ -18,6 +22,7 @@
|
|||
#define RPMH_REGULATOR_LEVEL_SVS_L1 192
|
||||
#define RPMH_REGULATOR_LEVEL_SVS_L2 224
|
||||
#define RPMH_REGULATOR_LEVEL_NOM 256
|
||||
#define RPMH_REGULATOR_LEVEL_NOM_L0 288
|
||||
#define RPMH_REGULATOR_LEVEL_NOM_L1 320
|
||||
#define RPMH_REGULATOR_LEVEL_NOM_L2 336
|
||||
#define RPMH_REGULATOR_LEVEL_TURBO 384
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user