mirror of
https://github.com/torvalds/linux.git
synced 2026-05-25 23:52:08 +02:00
Two nouveau interrupt handling fixes, one race fix for ivpu, a race fix
for drm_sched, and a clock fix for ti-sn65dsi86. -----BEGIN PGP SIGNATURE----- iJUEABMJAB0WIQTkHFbLp4ejekA/qfgnX84Zoj2+dgUCaLf0wgAKCRAnX84Zoj2+ dhZ1AX95UvkV276OjU0moCzodrCpVLR7eYI/Mbr1/LHeLKzK/aMAmsDHZnxuVucp ivkzcIYBf3T2RJkpavIkpUrEg9uSljr7h3UGdUJo6rnIcSw5Q8WZk5YsJXc/EquJ mROdGn7m7g== =MIoE -----END PGP SIGNATURE----- Merge tag 'drm-misc-fixes-2025-09-03' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes Two nouveau interrupt handling fixes, one race fix for ivpu, a race fix for drm_sched, and a clock fix for ti-sn65dsi86. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maxime Ripard <mripard@redhat.com> Link: https://lore.kernel.org/r/qc2rd7bskgufjtyspbjflyjpswcnhyja6s7nm2yb67j7hezyey@yfn2w6n5trff
This commit is contained in:
Dave Airlie
commit
42e0a73bf7
|
|
@ -7820,7 +7820,7 @@ Q: https://patchwork.freedesktop.org/project/nouveau/
|
|||
Q: https://gitlab.freedesktop.org/drm/nouveau/-/merge_requests
|
||||
B: https://gitlab.freedesktop.org/drm/nouveau/-/issues
|
||||
C: irc://irc.oftc.net/nouveau
|
||||
T: git https://gitlab.freedesktop.org/drm/nouveau.git
|
||||
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
|
||||
F: drivers/gpu/drm/nouveau/
|
||||
F: include/uapi/drm/nouveau_drm.h
|
||||
|
||||
|
|
|
|||
|
|
@ -677,7 +677,7 @@ static void ivpu_bo_unbind_all_user_contexts(struct ivpu_device *vdev)
|
|||
static void ivpu_dev_fini(struct ivpu_device *vdev)
|
||||
{
|
||||
ivpu_jobs_abort_all(vdev);
|
||||
ivpu_pm_cancel_recovery(vdev);
|
||||
ivpu_pm_disable_recovery(vdev);
|
||||
ivpu_pm_disable(vdev);
|
||||
ivpu_prepare_for_reset(vdev);
|
||||
ivpu_shutdown(vdev);
|
||||
|
|
|
|||
|
|
@ -417,10 +417,10 @@ void ivpu_pm_init(struct ivpu_device *vdev)
|
|||
ivpu_dbg(vdev, PM, "Autosuspend delay = %d\n", delay);
|
||||
}
|
||||
|
||||
void ivpu_pm_cancel_recovery(struct ivpu_device *vdev)
|
||||
void ivpu_pm_disable_recovery(struct ivpu_device *vdev)
|
||||
{
|
||||
drm_WARN_ON(&vdev->drm, delayed_work_pending(&vdev->pm->job_timeout_work));
|
||||
cancel_work_sync(&vdev->pm->recovery_work);
|
||||
disable_work_sync(&vdev->pm->recovery_work);
|
||||
}
|
||||
|
||||
void ivpu_pm_enable(struct ivpu_device *vdev)
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ struct ivpu_pm_info {
|
|||
void ivpu_pm_init(struct ivpu_device *vdev);
|
||||
void ivpu_pm_enable(struct ivpu_device *vdev);
|
||||
void ivpu_pm_disable(struct ivpu_device *vdev);
|
||||
void ivpu_pm_cancel_recovery(struct ivpu_device *vdev);
|
||||
void ivpu_pm_disable_recovery(struct ivpu_device *vdev);
|
||||
|
||||
int ivpu_pm_suspend_cb(struct device *dev);
|
||||
int ivpu_pm_resume_cb(struct device *dev);
|
||||
|
|
|
|||
|
|
@ -392,6 +392,17 @@ static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
|
|||
|
||||
gpiod_set_value_cansleep(pdata->enable_gpio, 1);
|
||||
|
||||
/*
|
||||
* After EN is deasserted and an external clock is detected, the bridge
|
||||
* will sample GPIO3:1 to determine its frequency. The driver will
|
||||
* overwrite this setting in ti_sn_bridge_set_refclk_freq(). But this is
|
||||
* racy. Thus we have to wait a couple of us. According to the datasheet
|
||||
* the GPIO lines has to be stable at least 5 us (td5) but it seems that
|
||||
* is not enough and the refclk frequency value is still lost or
|
||||
* overwritten by the bridge itself. Waiting for 20us seems to work.
|
||||
*/
|
||||
usleep_range(20, 30);
|
||||
|
||||
/*
|
||||
* If we have a reference clock we can enable communication w/ the
|
||||
* panel (including the aux channel) w/out any need for an input clock
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ gv100_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
|
|||
struct nvif_push *push = &chan->chan.push;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 8);
|
||||
ret = PUSH_WAIT(push, 13);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -32,6 +32,11 @@ gv100_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
|
|||
NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) |
|
||||
NVDEF(NVC36F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS));
|
||||
|
||||
PUSH_MTHD(push, NVC36F, MEM_OP_A, 0,
|
||||
MEM_OP_B, 0,
|
||||
MEM_OP_C, NVDEF(NVC36F, MEM_OP_C, MEMBAR_TYPE, SYS_MEMBAR),
|
||||
MEM_OP_D, NVDEF(NVC36F, MEM_OP_D, OPERATION, MEMBAR));
|
||||
|
||||
PUSH_MTHD(push, NVC36F, NON_STALL_INTERRUPT, 0);
|
||||
|
||||
PUSH_KICK(push);
|
||||
|
|
|
|||
|
|
@ -7,6 +7,91 @@
|
|||
|
||||
#define NVC36F_NON_STALL_INTERRUPT (0x00000020)
|
||||
#define NVC36F_NON_STALL_INTERRUPT_HANDLE 31:0
|
||||
// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
|
||||
// specifying the page address for a targeted TLB invalidate and the uTLB for
|
||||
// a targeted REPLAY_CANCEL for UVM.
|
||||
// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly
|
||||
// rearranged fields.
|
||||
#define NVC36F_MEM_OP_A (0x00000028)
|
||||
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED
|
||||
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type
|
||||
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED
|
||||
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL
|
||||
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11
|
||||
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001
|
||||
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000
|
||||
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12
|
||||
#define NVC36F_MEM_OP_B (0x0000002c)
|
||||
#define NVC36F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0
|
||||
#define NVC36F_MEM_OP_C (0x00000030)
|
||||
#define NVC36F_MEM_OP_C_MEMBAR_TYPE 2:0
|
||||
#define NVC36F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000
|
||||
#define NVC36F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003
|
||||
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE
|
||||
#define NVC36F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0
|
||||
// MEM_OP_D MUST be preceded by MEM_OPs A-C.
|
||||
#define NVC36F_MEM_OP_D (0x00000034)
|
||||
#define NVC36F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE
|
||||
#define NVC36F_MEM_OP_D_OPERATION 31:27
|
||||
#define NVC36F_MEM_OP_D_OPERATION_MEMBAR 0x00000005
|
||||
#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009
|
||||
#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a
|
||||
#define NVC36F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
|
||||
#define NVC36F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
|
||||
// CLEAN_LINES is an alias for Tegra/GPU IP usage
|
||||
#define NVC36F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e
|
||||
#define NVC36F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
|
||||
#define NVC36F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010
|
||||
#define NVC36F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015
|
||||
#define NVC36F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016
|
||||
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0
|
||||
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000
|
||||
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001
|
||||
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002
|
||||
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003
|
||||
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2
|
||||
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000
|
||||
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001
|
||||
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3
|
||||
#define NVC36F_SEM_ADDR_LO (0x0000005c)
|
||||
#define NVC36F_SEM_ADDR_LO_OFFSET 31:2
|
||||
#define NVC36F_SEM_ADDR_HI (0x00000060)
|
||||
|
|
|
|||
|
|
@ -350,6 +350,8 @@ nvkm_fifo_dtor(struct nvkm_engine *engine)
|
|||
nvkm_chid_unref(&fifo->chid);
|
||||
|
||||
nvkm_event_fini(&fifo->nonstall.event);
|
||||
if (fifo->func->nonstall_dtor)
|
||||
fifo->func->nonstall_dtor(fifo);
|
||||
mutex_destroy(&fifo->mutex);
|
||||
|
||||
if (fifo->func->dtor)
|
||||
|
|
|
|||
|
|
@ -517,19 +517,11 @@ ga100_fifo_nonstall_intr(struct nvkm_inth *inth)
|
|||
static void
|
||||
ga100_fifo_nonstall_block(struct nvkm_event *event, int type, int index)
|
||||
{
|
||||
struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event);
|
||||
struct nvkm_runl *runl = nvkm_runl_get(fifo, index, 0);
|
||||
|
||||
nvkm_inth_block(&runl->nonstall.inth);
|
||||
}
|
||||
|
||||
static void
|
||||
ga100_fifo_nonstall_allow(struct nvkm_event *event, int type, int index)
|
||||
{
|
||||
struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event);
|
||||
struct nvkm_runl *runl = nvkm_runl_get(fifo, index, 0);
|
||||
|
||||
nvkm_inth_allow(&runl->nonstall.inth);
|
||||
}
|
||||
|
||||
const struct nvkm_event_func
|
||||
|
|
@ -564,12 +556,26 @@ ga100_fifo_nonstall_ctor(struct nvkm_fifo *fifo)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
nvkm_inth_allow(&runl->nonstall.inth);
|
||||
|
||||
nr = max(nr, runl->id + 1);
|
||||
}
|
||||
|
||||
return nr;
|
||||
}
|
||||
|
||||
void
|
||||
ga100_fifo_nonstall_dtor(struct nvkm_fifo *fifo)
|
||||
{
|
||||
struct nvkm_runl *runl;
|
||||
|
||||
nvkm_runl_foreach(runl, fifo) {
|
||||
if (runl->nonstall.vector < 0)
|
||||
continue;
|
||||
nvkm_inth_block(&runl->nonstall.inth);
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
ga100_fifo_runl_ctor(struct nvkm_fifo *fifo)
|
||||
{
|
||||
|
|
@ -599,6 +605,7 @@ ga100_fifo = {
|
|||
.runl_ctor = ga100_fifo_runl_ctor,
|
||||
.mmu_fault = &tu102_fifo_mmu_fault,
|
||||
.nonstall_ctor = ga100_fifo_nonstall_ctor,
|
||||
.nonstall_dtor = ga100_fifo_nonstall_dtor,
|
||||
.nonstall = &ga100_fifo_nonstall,
|
||||
.runl = &ga100_runl,
|
||||
.runq = &ga100_runq,
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ ga102_fifo = {
|
|||
.runl_ctor = ga100_fifo_runl_ctor,
|
||||
.mmu_fault = &tu102_fifo_mmu_fault,
|
||||
.nonstall_ctor = ga100_fifo_nonstall_ctor,
|
||||
.nonstall_dtor = ga100_fifo_nonstall_dtor,
|
||||
.nonstall = &ga100_fifo_nonstall,
|
||||
.runl = &ga100_runl,
|
||||
.runq = &ga100_runq,
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@ struct nvkm_fifo_func {
|
|||
void (*start)(struct nvkm_fifo *, unsigned long *);
|
||||
|
||||
int (*nonstall_ctor)(struct nvkm_fifo *);
|
||||
void (*nonstall_dtor)(struct nvkm_fifo *);
|
||||
const struct nvkm_event_func *nonstall;
|
||||
|
||||
const struct nvkm_runl_func *runl;
|
||||
|
|
@ -200,6 +201,7 @@ u32 tu102_chan_doorbell_handle(struct nvkm_chan *);
|
|||
|
||||
int ga100_fifo_runl_ctor(struct nvkm_fifo *);
|
||||
int ga100_fifo_nonstall_ctor(struct nvkm_fifo *);
|
||||
void ga100_fifo_nonstall_dtor(struct nvkm_fifo *);
|
||||
extern const struct nvkm_event_func ga100_fifo_nonstall;
|
||||
extern const struct nvkm_runl_func ga100_runl;
|
||||
extern const struct nvkm_runq_func ga100_runq;
|
||||
|
|
|
|||
|
|
@ -601,6 +601,7 @@ r535_fifo_new(const struct nvkm_fifo_func *hw, struct nvkm_device *device,
|
|||
rm->chan.func = &r535_chan;
|
||||
rm->nonstall = &ga100_fifo_nonstall;
|
||||
rm->nonstall_ctor = ga100_fifo_nonstall_ctor;
|
||||
rm->nonstall_dtor = ga100_fifo_nonstall_dtor;
|
||||
|
||||
return nvkm_fifo_new_(rm, device, type, inst, pfifo);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -391,7 +391,8 @@ EXPORT_SYMBOL(drm_sched_entity_set_priority);
|
|||
* Add a callback to the current dependency of the entity to wake up the
|
||||
* scheduler when the entity becomes available.
|
||||
*/
|
||||
static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity)
|
||||
static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity,
|
||||
struct drm_sched_job *sched_job)
|
||||
{
|
||||
struct drm_gpu_scheduler *sched = entity->rq->sched;
|
||||
struct dma_fence *fence = entity->dependency;
|
||||
|
|
@ -421,6 +422,10 @@ static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity)
|
|||
entity->dependency = fence;
|
||||
}
|
||||
|
||||
if (trace_drm_sched_job_unschedulable_enabled() &&
|
||||
!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &entity->dependency->flags))
|
||||
trace_drm_sched_job_unschedulable(sched_job, entity->dependency);
|
||||
|
||||
if (!dma_fence_add_callback(entity->dependency, &entity->cb,
|
||||
drm_sched_entity_wakeup))
|
||||
return true;
|
||||
|
|
@ -461,10 +466,8 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity)
|
|||
|
||||
while ((entity->dependency =
|
||||
drm_sched_job_dependency(sched_job, entity))) {
|
||||
if (drm_sched_entity_add_dependency_cb(entity)) {
|
||||
trace_drm_sched_job_unschedulable(sched_job, entity->dependency);
|
||||
if (drm_sched_entity_add_dependency_cb(entity, sched_job))
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/* skip jobs from entity that marked guilty */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user