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drm/i915/dmc: Limit pipe DMC clock gating w/a to just ADL/DG2/MTL

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Supposedly nothing post-MTL (even BMG) needs the pipe DMC clock
gating w/a (Wa_16015201720), so don't apply it.

TODO: check if the ADL/DG2 "clock gating needed during DMC loading" part
      is actually needed, not seeing anything in the docs about it...

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250617170759.19552-2-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä 2025-06-17 20:07:51 +03:00
parent 266907bb49
commit 42a7bf8aa7
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/display/intel_dmc.c
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@ -488,7 +488,7 @@ static void mtl_pipedmc_clock_gating_wa(struct intel_display *display)
static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
{
if (DISPLAY_VER(display) >= 14 && enable)
if (display->platform.meteorlake && enable)
mtl_pipedmc_clock_gating_wa(display);
else if (DISPLAY_VER(display) == 13)
adlp_pipedmc_clock_gating_wa(display, enable);