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ARM: socfpga: dts: fix qspi node compatible

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[ Upstream commit cb25b11943 ]

The QSPI flash node needs to have the required "jedec,spi-nor" in the
compatible string.

Fixes: 1df99da895 ("ARM: dts: socfpga: Enable QSPI in Arria10 devkit")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Dinh Nguyen 2021-11-01 19:36:30 -05:00 committed by Greg Kroah-Hartman
parent 7b4cc168d9
commit 429bb01e4d
7 changed files with 8 additions and 8 deletions
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2
arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
View File

@ -12,7 +12,7 @@ &qspi {
flash0: n25q00@0 { flash0: n25q00@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "n25q00aa"; compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <100000000>; spi-max-frequency = <100000000>;

2
arch/arm/boot/dts/socfpga_arria5_socdk.dts
View File

@ -119,7 +119,7 @@ &qspi {
flash: flash@0 { flash: flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "n25q256a"; compatible = "micron,n25q256a", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <100000000>; spi-max-frequency = <100000000>;

2
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
View File

@ -124,7 +124,7 @@ &qspi {
flash0: n25q00@0 { flash0: n25q00@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "n25q00"; compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>; /* chip select */ reg = <0>; /* chip select */
spi-max-frequency = <100000000>; spi-max-frequency = <100000000>;

2
arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
View File

@ -169,7 +169,7 @@ &qspi {
flash: flash@0 { flash: flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "n25q00"; compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <100000000>; spi-max-frequency = <100000000>;

2
arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
View File

@ -80,7 +80,7 @@ &qspi {
flash: flash@0 { flash: flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "n25q256a"; compatible = "micron,n25q256a", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <100000000>; spi-max-frequency = <100000000>;
m25p,fast-read; m25p,fast-read;

2
arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
View File

@ -116,7 +116,7 @@ &qspi {
flash0: n25q512a@0 { flash0: n25q512a@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "n25q512a"; compatible = "micron,n25q512a", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <100000000>; spi-max-frequency = <100000000>;

4
arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
View File

@ -224,7 +224,7 @@ &qspi {
n25q128@0 { n25q128@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "n25q128"; compatible = "micron,n25q128", "jedec,spi-nor";
reg = <0>; /* chip select */ reg = <0>; /* chip select */
spi-max-frequency = <100000000>; spi-max-frequency = <100000000>;
m25p,fast-read; m25p,fast-read;
@ -241,7 +241,7 @@ n25q128@0 {
n25q00@1 { n25q00@1 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "n25q00"; compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <1>; /* chip select */ reg = <1>; /* chip select */
spi-max-frequency = <100000000>; spi-max-frequency = <100000000>;
m25p,fast-read; m25p,fast-read;