From 4297f2dcbef75d872009336b72479d3a71164180 Mon Sep 17 00:00:00 2001 From: David Collins Date: Fri, 19 Jan 2018 15:14:00 -0800 Subject: [PATCH] clk: qcom: clk-spmi-pmic-div: avoid potential divide-by-0 Add a check of the cxo_hz value to ensure that it is greater than 0. That way, there is no chance of division by zero when using cxo_hz to calculate cxo_period_ns. Change-Id: I5498b7a08e4cb3be45469041a973d045f2ec2bdb Signed-off-by: David Collins --- drivers/clk/qcom/clk-spmi-pmic-div.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/clk-spmi-pmic-div.c b/drivers/clk/qcom/clk-spmi-pmic-div.c index af7ebeb9a7e8..5e762f5a0562 100644 --- a/drivers/clk/qcom/clk-spmi-pmic-div.c +++ b/drivers/clk/qcom/clk-spmi-pmic-div.c @@ -245,6 +245,10 @@ static int spmi_pmic_clkdiv_probe(struct platform_device *pdev) } cxo_hz = clk_get_rate(cxo); clk_put(cxo); + if (cxo_hz <= 0) { + dev_err(dev, "invalid CXO rate: %d\n", cxo_hz); + return -EINVAL; + } parent_name = of_clk_get_parent_name(of_node, 0); if (!parent_name) {