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Merge branch 'pci/controller/mediatek'

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- Add support for DT 'max-link-speed' and 'num-lanes' properties to
  restrict the link speed and width (AngeloGioacchino Del Regno)

* pci/controller/mediatek:
  PCI: mediatek-gen3: Remove unneeded semicolon
  PCI: mediatek-gen3: Add support for restricting link width
  PCI: mediatek-gen3: Add support for setting max-link-speed limit
This commit is contained in:
Bjorn Helgaas 2024-11-25 13:40:58 -06:00
commit 4268106135
1 changed files with 73 additions and 2 deletions
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75
drivers/pci/controller/pcie-mediatek-gen3.c
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@ -28,7 +28,12 @@
#include "../pci.h"
#define PCIE_BASE_CFG_REG 0x14
#define PCIE_BASE_CFG_SPEED GENMASK(15, 8)
#define PCIE_SETTING_REG 0x80
#define PCIE_SETTING_LINK_WIDTH GENMASK(11, 8)
#define PCIE_SETTING_GEN_SUPPORT GENMASK(14, 12)
#define PCIE_PCI_IDS_1 0x9c
#define PCI_CLASS(class) (class << 8)
#define PCIE_RC_MODE BIT(0)
@ -125,6 +130,9 @@
struct mtk_gen3_pcie;
#define PCIE_CONF_LINK2_CTL_STS (PCIE_CFG_OFFSET_ADDR + 0xb0)
#define PCIE_CONF_LINK2_LCR2_LINK_SPEED GENMASK(3, 0)
/**
* struct mtk_gen3_pcie_pdata - differentiate between host generations
* @power_up: pcie power_up callback
@ -160,6 +168,8 @@ struct mtk_msi_set {
* @phy: PHY controller block
* @clks: PCIe clocks
* @num_clks: PCIe clocks count for this port
* @max_link_speed: Maximum link speed (PCIe Gen) for this port
* @num_lanes: Number of PCIe lanes for this port
* @irq: PCIe controller interrupt number
* @saved_irq_state: IRQ enable state saved at suspend time
* @irq_lock: lock protecting IRQ register access
@ -180,6 +190,8 @@ struct mtk_gen3_pcie {
struct phy *phy;
struct clk_bulk_data *clks;
int num_clks;
u8 max_link_speed;
u8 num_lanes;
int irq;
u32 saved_irq_state;
@ -381,11 +393,35 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
int err;
u32 val;
/* Set as RC mode */
/* Set as RC mode and set controller PCIe Gen speed restriction, if any */
val = readl_relaxed(pcie->base + PCIE_SETTING_REG);
val |= PCIE_RC_MODE;
if (pcie->max_link_speed) {
val &= ~PCIE_SETTING_GEN_SUPPORT;
/* Can enable link speed support only from Gen2 onwards */
if (pcie->max_link_speed >= 2)
val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT,
GENMASK(pcie->max_link_speed - 2, 0));
}
if (pcie->num_lanes) {
val &= ~PCIE_SETTING_LINK_WIDTH;
/* Zero means one lane, each bit activates x2/x4/x8/x16 */
if (pcie->num_lanes > 1)
val |= FIELD_PREP(PCIE_SETTING_LINK_WIDTH,
GENMASK(fls(pcie->num_lanes >> 2), 0));
}
writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
/* Set Link Control 2 (LNKCTL2) speed restriction, if any */
if (pcie->max_link_speed) {
val = readl_relaxed(pcie->base + PCIE_CONF_LINK2_CTL_STS);
val &= ~PCIE_CONF_LINK2_LCR2_LINK_SPEED;
val |= FIELD_PREP(PCIE_CONF_LINK2_LCR2_LINK_SPEED, pcie->max_link_speed);
writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS);
}
/* Set class code */
val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1);
val &= ~GENMASK(31, 8);
@ -813,6 +849,7 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
struct device *dev = pcie->dev;
struct platform_device *pdev = to_platform_device(dev);
struct resource *regs;
u32 num_lanes;
regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
if (!regs)
@ -858,6 +895,14 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
return pcie->num_clks;
}
ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes);
if (ret == 0) {
if (num_lanes == 0 || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2))
dev_warn(dev, "invalid num-lanes, using controller defaults\n");
else
pcie->num_lanes = num_lanes;
}
return 0;
}
@ -1004,9 +1049,21 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
}
static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pcie)
{
u32 val;
int ret;
val = readl_relaxed(pcie->base + PCIE_BASE_CFG_REG);
val = FIELD_GET(PCIE_BASE_CFG_SPEED, val);
ret = fls(val);
return ret > 0 ? ret : -EINVAL;
}
static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
{
int err;
int err, max_speed;
err = mtk_pcie_parse_port(pcie);
if (err)
@ -1031,6 +1088,20 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
if (err)
return err;
err = of_pci_get_max_link_speed(pcie->dev->of_node);
if (err) {
/* Get the maximum speed supported by the controller */
max_speed = mtk_pcie_get_controller_max_link_speed(pcie);
/* Set max_link_speed only if the controller supports it */
if (max_speed >= 0 && max_speed <= err) {
pcie->max_link_speed = err;
dev_info(pcie->dev,
"maximum controller link speed Gen%d, overriding to Gen%u",
max_speed, pcie->max_link_speed);
}
}
/* Try link up */
err = mtk_pcie_startup_port(pcie);
if (err)