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arm64: dts: renesas: r9a09g087: Add DT nodes for SCI channels 1-5

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The RZ/N2H SoC exposes six SCI controllers; sci0 was already present in
the SoC DTSI. Add the remaining SCI nodes (sci1-sci5).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250812200344.3253781-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2025-08-12 21:03:33 +01:00 committed by Geert Uytterhoeven
parent be5d60d94b
commit 41e1949785
1 changed files with 70 additions and 0 deletions
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70
arch/arm64/boot/dts/renesas/r9a09g087.dtsi
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@ -90,6 +90,76 @@ sci0: serial@80005000 {
status = "disabled";
};
sci1: serial@80005400 {
compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
reg = <0 0x80005400 0 0x400>;
interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
sci2: serial@80005800 {
compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
reg = <0 0x80005800 0 0x400>;
interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
sci3: serial@80005c00 {
compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
reg = <0 0x80005c00 0 0x400>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
sci4: serial@80006000 {
compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
reg = <0 0x80006000 0 0x400>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 607 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 608 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
sci5: serial@81005000 {
compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
reg = <0 0x81005000 0 0x400>;
interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 611 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 612 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
i2c0: i2c@80088000 {
compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
reg = <0 0x80088000 0 0x400>;