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riscv: dts: spacemit: enable K1 SoC QSPI on BPI-F3

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Define DTS nodes to enable support for QSPI on the K1 SoC, including the
pin control configuration used.  Enable QSPI on the Banana Pi BPI-F3 board.

Signed-off-by: Alex Elder <elder@riscstar.com>
Link: https://lore.kernel.org/r/20251027133008.360237-9-elder@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
This commit is contained in:
Alex Elder 2025-10-27 08:30:06 -05:00 committed by Yixun Lan
parent 0ee5993466
commit 41d34e0b54
No known key found for this signature in database
GPG Key ID: 31AAEA47594DBBED
3 changed files with 43 additions and 0 deletions
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6
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
View File

@ -113,6 +113,12 @@ &pdma {
status = "okay";
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&qspi_cfg>;
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_0_cfg>;
pinctrl-names = "default";

21
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
View File

@ -73,6 +73,27 @@ i2c8-0-pins {
};
};
qspi_cfg: qspi-cfg {
qspi-pins {
pinmux = <K1_PADCONF(98, 0)>, /* QSPI_DATA3 */
<K1_PADCONF(99, 0)>, /* QSPI_DATA2 */
<K1_PADCONF(100, 0)>, /* QSPI_DATA1 */
<K1_PADCONF(101, 0)>, /* QSPI_DATA0 */
<K1_PADCONF(102, 0)>; /* QSPI_CLK */
bias-disable;
drive-strength = <19>;
power-source = <3300>;
};
qspi-cs1-pins {
pinmux = <K1_PADCONF(103, 0)>; /* QSPI_CS1 */
bias-pull-up = <0>;
drive-strength = <19>;
power-source = <3300>;
};
};
/omit-if-no-ref/
uart0_0_cfg: uart0-0-cfg {
uart0-0-pins {

16
arch/riscv/boot/dts/spacemit/k1.dtsi
View File

@ -823,6 +823,22 @@ uart9: serial@d4017800 {
status = "disabled";
};
qspi: spi@d420c000 {
compatible = "spacemit,k1-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0xd420c000 0x0 0x1000>,
<0x0 0xb8000000 0x0 0xc00000>;
reg-names = "QuadSPI", "QuadSPI-memory";
clocks = <&syscon_apmu CLK_QSPI_BUS>,
<&syscon_apmu CLK_QSPI>;
clock-names = "qspi_en", "qspi";
resets = <&syscon_apmu RESET_QSPI>,
<&syscon_apmu RESET_QSPI_BUS>;
interrupts = <117>;
status = "disabled";
};
/* sec_uart1: 0xf0612000, not available from Linux */
};