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arm64: dts: qcom: Introduce Glymur base dtsi
Introduce the base device tree support for Glymur – Qualcomm's next-generation compute SoC. The new glymur.dtsi describes the core SoC components, including: - CPUs and CPU topology - Interrupt controller and TLMM - GCC,DISPCC and RPMHCC clock controllers - Reserved memory and interconnects - APPS and PCIe SMMU and firmware SCM - Watchdog, RPMHPD, APPS RSC and SRAM - PSCI and PMU nodes - QUPv3 serial engines - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS - PDP0 mailbox, IPCC and AOSS - Display clock controller - SPMI PMIC arbiter with SPMI0/1/2 buses - SMP2P nodes - TSENS and thermal zones (8 instances, 92 sensors) Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104, PMH0110, PMIC's along with temp-alarm and GPIO nodes needed on Glymur Enabled PCIe controllers and associated PHY to support boot to shell with nvme storage, List of PCIe instances enabled: - PCIe3b - PCIe4 - PCIe5 - PCIe6 Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Co-developed-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com> Co-developed-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Co-developed-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Co-developed-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Co-developed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Co-developed-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260219-upstream_v3_glymur_introduction-v8-3-8ce4e489ebb6@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Pankaj Patil
Bjorn Andersson
parent
4ed5f35359
commit
41b6e8db40
5913
arch/arm64/boot/dts/qcom/glymur.dtsi
Normal file
5913
arch/arm64/boot/dts/qcom/glymur.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
187
arch/arm64/boot/dts/qcom/pmcx0102.dtsi
Normal file
187
arch/arm64/boot/dts/qcom/pmcx0102.dtsi
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@ -0,0 +1,187 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/spmi/spmi.h>
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/ {
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thermal-zones {
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pmcx0102-c0-thermal {
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polling-delay-passive = <100>;
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thermal-sensors = <&pmcx0102_c_e0_temp_alarm>;
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trips {
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trip0 {
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temperature = <95000>;
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hysteresis = <0>;
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type = "passive";
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};
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trip1 {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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pmcx0102-c1-thermal {
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polling-delay-passive = <100>;
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thermal-sensors = <&pmcx0102_c_e1_temp_alarm>;
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trips {
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trip0 {
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temperature = <95000>;
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hysteresis = <0>;
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type = "passive";
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};
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trip1 {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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pmcx0102-d0-thermal {
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polling-delay-passive = <100>;
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thermal-sensors = <&pmcx0102_d_e0_temp_alarm>;
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trips {
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trip0 {
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temperature = <95000>;
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hysteresis = <0>;
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type = "passive";
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};
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trip1 {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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pmcx0102-d1-thermal {
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polling-delay-passive = <100>;
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thermal-sensors = <&pmcx0102_d_e1_temp_alarm>;
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trips {
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trip0 {
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temperature = <95000>;
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hysteresis = <0>;
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type = "passive";
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};
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trip1 {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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};
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};
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&spmi_bus0 {
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pmcx0102_c_e0: pmic@2 {
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compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
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reg = <0x2 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pmcx0102_c_e0_temp_alarm: temp-alarm@a00 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0xa00>;
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interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
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#thermal-sensor-cells = <0>;
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};
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pmcx0102_c_e0_gpios: gpio@8800 {
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compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
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reg = <0x8800>;
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gpio-controller;
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gpio-ranges = <&pmcx0102_c_e0_gpios 0 0 14>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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pmcx0102_d_e0: pmic@3 {
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compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
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reg = <0x3 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pmcx0102_d_e0_temp_alarm: temp-alarm@a00 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0xa00>;
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interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
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#thermal-sensor-cells = <0>;
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};
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pmcx0102_d_e0_gpios: gpio@8800 {
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compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
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reg = <0x8800>;
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gpio-controller;
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gpio-ranges = <&pmcx0102_d_e0_gpios 0 0 14>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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};
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&spmi_bus1 {
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pmcx0102_c_e1: pmic@2 {
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compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
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reg = <0x2 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pmcx0102_c_e1_temp_alarm: temp-alarm@a00 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0xa00>;
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interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
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#thermal-sensor-cells = <0>;
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};
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pmcx0102_c_e1_gpios: gpio@8800 {
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compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
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reg = <0x8800>;
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gpio-controller;
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gpio-ranges = <&pmcx0102_c_e1_gpios 0 0 14>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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pmcx0102_d_e1: pmic@3 {
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compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
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reg = <0x3 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pmcx0102_d_e1_temp_alarm: temp-alarm@a00 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0xa00>;
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interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
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#thermal-sensor-cells = <0>;
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};
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pmcx0102_d_e1_gpios: gpio@8800 {
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compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
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reg = <0x8800>;
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gpio-controller;
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gpio-ranges = <&pmcx0102_d_e1_gpios 0 0 14>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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};
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68
arch/arm64/boot/dts/qcom/pmh0101.dtsi
Normal file
68
arch/arm64/boot/dts/qcom/pmh0101.dtsi
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@ -0,0 +1,68 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/spmi/spmi.h>
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/ {
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thermal-zones {
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pmh0101-thermal {
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polling-delay-passive = <100>;
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thermal-sensors = <&pmh0101_temp_alarm>;
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trips {
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trip0 {
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temperature = <95000>;
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hysteresis = <0>;
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type = "passive";
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};
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trip1 {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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};
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};
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&spmi_bus0 {
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pmic@1 {
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compatible = "qcom,pmh0101", "qcom,spmi-pmic";
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reg = <0x1 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pmh0101_temp_alarm: temp-alarm@a00 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0xa00>;
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interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
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#thermal-sensor-cells = <0>;
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};
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pmh0101_gpios: gpio@8800 {
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compatible = "qcom,pmh0101-gpio", "qcom,spmi-gpio";
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reg = <0x8800>;
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gpio-controller;
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gpio-ranges = <&pmh0101_gpios 0 0 18>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pmh0101_flash: led-controller@ee00 {
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compatible = "qcom,pmh0101-flash-led", "qcom,spmi-flash-led";
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reg = <0xee00>;
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status = "disabled";
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};
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pmh0101_pwm: pwm {
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compatible = "qcom,pmh0101-pwm", "qcom,pm8350c-pwm";
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#pwm-cells = <2>;
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status = "disabled";
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};
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};
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};
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144
arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi
Normal file
144
arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi
Normal file
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@ -0,0 +1,144 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/spmi/spmi.h>
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/{
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thermal_zones {
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pmh0104-i0-thermal {
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polling-delay-passive = <100>;
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thermal-sensors = <&pmh0104_i_e0_temp_alarm>;
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trips {
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trip0 {
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temperature = <95000>;
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hysteresis = <0>;
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type = "passive";
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};
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trip1 {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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pmh0104-j0-thermal {
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polling-delay-passive = <100>;
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thermal-sensors = <&pmh0104_j_e0_temp_alarm>;
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trips {
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trip0 {
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temperature = <95000>;
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hysteresis = <0>;
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type = "passive";
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};
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trip1 {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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pmh0104-l1-thermal {
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polling-delay-passive = <100>;
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thermal-sensors = <&pmh0104_l_e1_temp_alarm>;
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trips {
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trip0 {
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temperature = <95000>;
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hysteresis = <0>;
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type = "passive";
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};
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trip1 {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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};
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};
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&spmi_bus0 {
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pmh0104_i_e0: pmic@8 {
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compatible = "qcom,pmh0104", "qcom,spmi-pmic";
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reg = <0x8 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pmh0104_i_e0_temp_alarm: temp-alarm@a00 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0xa00>;
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interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
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#thermal-sensor-cells = <0>;
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};
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pmh0104_i_e0_gpios: gpio@8800 {
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compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
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reg = <0x8800>;
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gpio-controller;
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gpio-ranges = <&pmh0104_i_e0_gpios 0 0 8>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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pmh0104_j_e0: pmic@9 {
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compatible = "qcom,pmh0104", "qcom,spmi-pmic";
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reg = <0x9 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pmh0104_j_e0_temp_alarm: temp-alarm@a00 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0xa00>;
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interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
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#thermal-sensor-cells = <0>;
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};
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pmh0104_j_e0_gpios: gpio@8800 {
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compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
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reg = <0x8800>;
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gpio-controller;
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gpio-ranges = <&pmh0104_j_e0_gpios 0 0 8>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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};
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&spmi_bus1 {
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pmh0104_l_e1: pmic@b {
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compatible = "qcom,pmh0104", "qcom,spmi-pmic";
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reg = <0xb SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pmh0104_l_e1_temp_alarm: temp-alarm@a00 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0xa00>;
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interrupts = <0xb 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
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#thermal-sensor-cells = <0>;
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};
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pmh0104_l_e1_gpios: gpio@8800 {
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compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
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reg = <0x8800>;
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gpio-controller;
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gpio-ranges = <&pmh0104_l_e1_gpios 0 0 8>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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};
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144
arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi
Normal file
144
arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi
Normal file
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@ -0,0 +1,144 @@
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// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
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|
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#include <dt-bindings/interrupt-controller/irq.h>
|
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#include <dt-bindings/spmi/spmi.h>
|
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|
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/ {
|
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thermal-zones {
|
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pmh0110-f0-thermal {
|
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polling-delay-passive = <100>;
|
||||
thermal-sensors = <&pmh0110_f_e0_temp_alarm>;
|
||||
|
||||
trips {
|
||||
trip0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
trip1 {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmh0110-f1-thermal {
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&pmh0110_f_e1_temp_alarm>;
|
||||
|
||||
trips {
|
||||
trip0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
trip1 {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmh0110-h0-thermal {
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&pmh0110_h_e0_temp_alarm>;
|
||||
|
||||
trips {
|
||||
trip0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
trip1 {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spmi_bus0 {
|
||||
pmh0110_f_e0: pmic@5 {
|
||||
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
|
||||
reg = <0x5 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmh0110_f_e0_temp_alarm: temp-alarm@a00 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0xa00>;
|
||||
interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
pmh0110_f_e0_gpios: gpio@8800 {
|
||||
compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
|
||||
reg = <0x8800>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pmh0110_f_e0_gpios 0 0 14>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pmh0110_h_e0: pmic@7 {
|
||||
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
|
||||
reg = <0x7 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmh0110_h_e0_temp_alarm: temp-alarm@a00 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0xa00>;
|
||||
interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
pmh0110_h_e0_gpios: gpio@8800 {
|
||||
compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
|
||||
reg = <0x8800>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pmh0110_h_e0_gpios 0 0 14>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spmi_bus1 {
|
||||
pmh0110_f_e1: pmic@5 {
|
||||
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
|
||||
reg = <0x5 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmh0110_f_e1_temp_alarm: temp-alarm@a00 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0xa00>;
|
||||
interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
pmh0110_f_e1_gpios: gpio@8800 {
|
||||
compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
|
||||
reg = <0x8800>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pmh0110_f_e1_gpios 0 0 14>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
70
arch/arm64/boot/dts/qcom/pmk8850.dtsi
Normal file
70
arch/arm64/boot/dts/qcom/pmk8850.dtsi
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
&spmi_bus0 {
|
||||
pmic@0 {
|
||||
compatible = "qcom,pmk8850", "qcom,spmi-pmic";
|
||||
reg = <0x0 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmk8850_pon: pon@1300 {
|
||||
compatible = "qcom,pmk8350-pon";
|
||||
reg = <0x1300>,
|
||||
<0x800>;
|
||||
reg-names = "hlos",
|
||||
"pbs";
|
||||
|
||||
pon_pwrkey: pwrkey {
|
||||
compatible = "qcom,pmk8350-pwrkey";
|
||||
interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
|
||||
linux,code = <KEY_POWER>;
|
||||
};
|
||||
|
||||
pon_resin: resin {
|
||||
compatible = "qcom,pmk8350-resin";
|
||||
interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pmk8850_gpios: gpio@b800 {
|
||||
compatible = "qcom,pmk8850-gpio", "qcom,spmi-gpio";
|
||||
reg = <0xb800>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pmk8850_gpios 0 0 8>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pmk8850_rtc: rtc@6100 {
|
||||
compatible = "qcom,pmk8350-rtc";
|
||||
reg = <0x6100>,
|
||||
<0x6200>;
|
||||
reg-names = "rtc",
|
||||
"alarm";
|
||||
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
pmk8850_sdam_2: nvram@7100 {
|
||||
compatible = "qcom,spmi-sdam";
|
||||
reg = <0x7100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x7100 0x100>;
|
||||
|
||||
reboot_reason: reboot-reason@48 {
|
||||
reg = <0x48 0x1>;
|
||||
bits = <1 7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
45
arch/arm64/boot/dts/qcom/smb2370.dtsi
Normal file
45
arch/arm64/boot/dts/qcom/smb2370.dtsi
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
&spmi_bus2 {
|
||||
smb2370_j_e2: pmic@9 {
|
||||
compatible = "qcom,smb2370", "qcom,spmi-pmic";
|
||||
reg = <0x9 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
smb2370_j_e2_eusb2_repeater: phy@fd00 {
|
||||
compatible = "qcom,smb2370-eusb2-repeater";
|
||||
reg = <0xfd00>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
smb2370_k_e2: pmic@a {
|
||||
compatible = "qcom,smb2370", "qcom,spmi-pmic";
|
||||
reg = <0xa SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
smb2370_k_e2_eusb2_repeater: phy@fd00 {
|
||||
compatible = "qcom,smb2370-eusb2-repeater";
|
||||
reg = <0xfd00>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
smb2370_l_e2: pmic@b {
|
||||
compatible = "qcom,smb2370", "qcom,spmi-pmic";
|
||||
reg = <0xb SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
smb2370_l_e2_eusb2_repeater: phy@fd00 {
|
||||
compatible = "qcom,smb2370-eusb2-repeater";
|
||||
reg = <0xfd00>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user