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drm/amdgpu: fix array out of bounds accesses for mes sw_fini
The mes.fw[] is per-pipe resource shared accross xcc inst. And enlarge hung_queue array to max inst_pipes. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -159,9 +159,9 @@ struct amdgpu_mes {
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int hung_queue_db_array_size;
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int hung_queue_hqd_info_offset;
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struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_PIPES];
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uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_PIPES];
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void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_PIPES];
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struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_INST_PIPES];
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uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
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void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_INST_PIPES];
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/* cooperative dispatch */
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bool enable_coop_mode;
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@ -1611,7 +1611,6 @@ static int mes_v12_1_sw_fini(struct amdgpu_ip_block *ip_block)
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amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[inst],
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&adev->mes.eop_gpu_addr[inst],
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NULL);
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amdgpu_ucode_release(&adev->mes.fw[inst]);
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if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) {
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amdgpu_bo_free_kernel(&adev->mes.ring[inst].mqd_obj,
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@ -1622,6 +1621,9 @@ static int mes_v12_1_sw_fini(struct amdgpu_ip_block *ip_block)
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}
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}
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for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++)
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amdgpu_ucode_release(&adev->mes.fw[pipe]);
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for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
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if (!adev->enable_uni_mes) {
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amdgpu_bo_free_kernel(&adev->gfx.kiq[xcc_id].ring.mqd_obj,
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