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FROMGIT: KVM: arm64: Don't access PMSELR_EL0/PMUSERENR_EL0 when no PMU is available
When running under a nesting hypervisor, it isn't guaranteed that the virtual HW will include a PMU. In which case, let's not try to access the PMU registers in the world switch, as that'd be deadly. Reported-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com> Link: https://lore.kernel.org/r/20210209114844.3278746-3-maz@kernel.org (cherry picked from commit 913e36d3f29d776385ae6a15506522da9b161dcd git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git fixes) Signed-off-by: Will Deacon <willdeacon@google.com> Bug: 178098380 Test: atest VirtualizationHostTestCases on an EL2-enabled device Change-Id: I123f0d3fe543899723ceb909b7b0acd342ddfdcd
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@ -101,6 +101,9 @@ KVM_NVHE_ALIAS(__stop___kvm_ex_table);
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/* Array containing bases of nVHE per-CPU memory regions. */
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KVM_NVHE_ALIAS(kvm_arm_hyp_percpu_base);
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/* PMU available static key */
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KVM_NVHE_ALIAS(kvm_arm_pmu_available);
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#endif /* CONFIG_KVM */
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#endif /* __ARM64_KERNEL_IMAGE_VARS_H */
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@ -90,15 +90,18 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
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* counter, which could make a PMXEVCNTR_EL0 access UNDEF at
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* EL1 instead of being trapped to EL2.
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*/
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write_sysreg(0, pmselr_el0);
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write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
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if (kvm_arm_support_pmu_v3()) {
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write_sysreg(0, pmselr_el0);
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write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
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}
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write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
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}
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static inline void __deactivate_traps_common(void)
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{
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write_sysreg(0, hstr_el2);
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write_sysreg(0, pmuserenr_el0);
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if (kvm_arm_support_pmu_v3())
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write_sysreg(0, pmuserenr_el0);
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}
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static inline void ___activate_traps(struct kvm_vcpu *vcpu)
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