github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-02 11:33:28 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

ARM: dts: microchip: sama7d65: Add cache configuration for cpu node

Browse Source 
Describe the cache memories according with datasheet chapter 15.2:

- L1 cache configuration with 32KB for both data and instruction cache.
- L2 cache configuration with 256KB unified cache.

Before this patch the kernel reported the warning:

[    0.161955] cacheinfo: Unable to detect cache hierarchy for CPU 0

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250619070636.8844-2-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
This commit is contained in:
Mihai Sain 2025-06-19 10:06:35 +03:00 committed by Claudiu Beznea
parent 1e2e0ed390
commit 4101c8274b
1 changed files with 10 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/boot/dts/microchip/sama7d65.dtsi
View File

@ -32,6 +32,16 @@ cpu0: cpu@0 {
device_type = "cpu";
clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
clock-names = "cpu";
d-cache-size = <0x8000>; // L1, 32 KB
i-cache-size = <0x8000>; // L1, 32 KB
next-level-cache = <&L2>;
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>; // L2, 256 KB
cache-unified;
};
};
};