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drm/amd/display: Fix for access for ddc pin and aux engine.

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[Why & How]
1. Remove unnecessary dummy interrupt source for USB4 HPD & HPD RX
2. Adjust parameter for DPCD writing of link training process of DPIA link
3. Adjust specific AUX defer delay for DPIA link

Reviewed-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Meenakshikumar Somasundaram 2021-08-13 13:09:25 -04:00 committed by Alex Deucher
parent 6aa8d42c66
commit 40fadb4c73
4 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -1709,9 +1709,9 @@ static bool dc_link_construct_dpia(struct dc_link *link,
DC_LOGGER_INIT(dc_ctx->logger);
/* Initialized dummy hpd and hpd rx */
link->irq_source_hpd = DC_IRQ_SOURCE_USB4_DMUB_HPD;
link->irq_source_hpd_rx = DC_IRQ_SOURCE_USB4_DMUB_HPDRX;
/* Initialized irq source for hpd and hpd rx */
link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
link->link_status.dpcd_caps = &link->dpcd_caps;
link->dc = init_params->dc;

6
drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
View File

@ -234,7 +234,7 @@ static enum dc_status dpcd_set_lt_pattern(struct dc_link *link,
}
status = core_link_write_dpcd(link,
DP_TRAINING_PATTERN_SET,
dpcd_tps_offset,
&dpcd_pattern.raw,
sizeof(dpcd_pattern.raw));
@ -796,7 +796,7 @@ static enum dc_status dpcd_clear_lt_pattern(struct dc_link *link, uint32_t hop)
((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (hop - 1));
status = core_link_write_dpcd(link,
DP_TRAINING_PATTERN_SET,
dpcd_tps_offset,
&dpcd_pattern.raw,
sizeof(dpcd_pattern.raw));
@ -906,7 +906,7 @@ enum link_training_result dc_link_dpia_perform_link_training(struct dc_link *lin
enum link_training_result result;
struct link_training_settings lt_settings;
uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */
uint8_t repeater_id; /* Current hop. */
int8_t repeater_id; /* Current hop. */
/* Configure link as prescribed in link_setting and set LTTPR mode. */
result = dpia_configure_link(link, link_setting, &lt_settings);

3
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
View File

@ -627,6 +627,7 @@ int dce_aux_transfer_dmub_raw(struct ddc_service *ddc,
#define AUX_MAX_I2C_DEFER_RETRIES 7
#define AUX_MAX_INVALID_REPLY_RETRIES 2
#define AUX_MAX_TIMEOUT_RETRIES 3
#define AUX_DEFER_DELAY_FOR_DPIA 4 /*ms*/
static void dce_aux_log_payload(const char *payload_name,
unsigned char *payload, uint32_t length, uint32_t max_length_to_log)
@ -772,6 +773,8 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
/* polling_timeout_period is in us */
if (aux110)
defer_time_in_ms += aux110->polling_timeout_period / 1000;
else
defer_time_in_ms += AUX_DEFER_DELAY_FOR_DPIA;
++aux_defer_retries;
fallthrough;
case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:

5
drivers/gpu/drm/amd/display/dc/irq_types.h
View File

@ -153,10 +153,7 @@ enum dc_irq_source {
DC_IRQ_SOURCE_DMCUB_OUTBOX,
DC_IRQ_SOURCE_DMCUB_OUTBOX0,
DC_IRQ_SOURCE_DMCUB_GENERAL_DATAOUT,
DAL_IRQ_SOURCES_NUMBER,
/* Dummy interrupt source for USB4 HPD & HPD RX */
DC_IRQ_SOURCE_USB4_DMUB_HPD,
DC_IRQ_SOURCE_USB4_DMUB_HPDRX,
DAL_IRQ_SOURCES_NUMBER
};
enum irq_type