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arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support
Add initial device tree support for the Qualcomm IPQ5210 SoC and rdp504 board. Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260325-ipq5210_boot_to_shell-v3-2-9c7360d19d10@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Kathiravan Thirumoorthy
Bjorn Andersson
parent
703d08de53
commit
4073cf900e
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@ -23,6 +23,7 @@ hamoa-iot-evk-el2-dtbs := hamoa-iot-evk.dtb x1-el2.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk-el2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5210-rdp504.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
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79
arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
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79
arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
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@ -0,0 +1,79 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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/dts-v1/;
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#include "ipq5210.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ5210 RDP504";
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compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210";
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aliases {
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serial0 = &uart1;
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};
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chosen {
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stdout-path = "serial0";
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};
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};
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&sdhc {
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max-frequency = <192000000>;
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bus-width = <4>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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pinctrl-0 = <&sdhc_default_state>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sleep_clk {
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clock-frequency = <32000>;
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};
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&tlmm {
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qup_uart1_default_state: qup-uart1-default-state {
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pins = "gpio38", "gpio39";
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function = "qup_se1";
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drive-strength = <6>;
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bias-pull-down;
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};
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sdhc_default_state: sdhc-default-state {
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clk-pins {
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pins = "gpio5";
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function = "sdc_clk";
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drive-strength = <8>;
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bias-disable;
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};
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cmd-pins {
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pins = "gpio4";
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function = "sdc_cmd";
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drive-strength = <8>;
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bias-pull-up;
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};
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data-pins {
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pins = "gpio0", "gpio1", "gpio2", "gpio3";
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function = "sdc_data";
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drive-strength = <8>;
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bias-pull-up;
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};
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};
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};
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&uart1 {
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pinctrl-0 = <&qup_uart1_default_state>;
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pinctrl-names = "default";
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status = "okay";
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};
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&xo_board {
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clock-frequency = <24000000>;
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};
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311
arch/arm64/boot/dts/qcom/ipq5210.dtsi
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311
arch/arm64/boot/dts/qcom/ipq5210.dtsi
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@ -0,0 +1,311 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,ipq5210-gcc.h>
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#include <dt-bindings/reset/qcom,ipq5210-gcc.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&intc>;
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clocks {
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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xo_board: xo-board-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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};
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l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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scm {
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compatible = "qcom,scm-ipq5210", "qcom,scm";
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x80000000 0x0 0x0>;
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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bootloader@87800000 {
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reg = <0x0 0x87800000 0x0 0x400000>;
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no-map;
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};
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smem@87c00000 {
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compatible = "qcom,smem";
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reg = <0x0 0x87c00000 0x0 0x40000>;
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no-map;
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hwlocks = <&tcsr_mutex 3>;
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};
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tfa@87d00000 {
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reg = <0x0 0x87d00000 0x0 0x80000>;
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no-map;
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};
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optee@87d80000 {
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reg = <0x0 0x87d80000 0x0 0x280000>;
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no-map;
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};
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-ranges = <0 0 0 0 0x10 0>;
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ranges = <0 0 0 0 0x10 0>;
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5210-tlmm";
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reg = <0x0 0x01000000 0x0 0x300000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 54>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gcc: clock-controller@1800000 {
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compatible = "qcom,ipq5210-gcc";
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reg = <0x0 0x01800000 0x0 0x40000>;
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clocks = <&xo_board>,
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<&sleep_clk>,
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<0>,
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<0>,
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<0>,
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<0>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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tcsr_mutex: hwlock@1905000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0x0 0x01905000 0x0 0x20000>;
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#hwlock-cells = <1>;
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};
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qupv3: geniqup@1ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x01ac0000 0x0 0x2000>;
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clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
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<&gcc GCC_QUPV3_AHB_SLV_CLK>;
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clock-names = "m-ahb", "s-ahb";
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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uart1: serial@1a84000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x0 0x01a84000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP_SE1_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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sdhc: mmc@7804000 {
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compatible = "qcom,ipq5210-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x0 0x07804000 0x0 0x1000>,
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<0x0 0x07805000 0x0 0x1000>;
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reg-names = "hc",
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"cqhci";
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq",
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"pwr_irq";
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clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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<&gcc GCC_SDCC1_APPS_CLK>,
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<&xo_board>;
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clock-names = "iface",
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"core",
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"xo";
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non-removable;
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status = "disabled";
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};
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x0 0xb000000 0x0 0x1000>,
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<0x0 0xb002000 0x0 0x1000>,
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<0x0 0xb001000 0x0 0x1000>,
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<0x0 0xb004000 0x0 0x1000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0x0b00c000 0 0x3000>;
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v2m0: v2m@0 {
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compatible = "arm,gic-v2m-frame";
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reg = <0x0 0x0 0x0 0xffd>;
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msi-controller;
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};
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v2m1: v2m@1000 {
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compatible = "arm,gic-v2m-frame";
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reg = <0x0 0x00001000 0x0 0xffd>;
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msi-controller;
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};
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v2m2: v2m@2000 {
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compatible = "arm,gic-v2m-frame";
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reg = <0x0 0x00002000 0x0 0xffd>;
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msi-controller;
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};
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};
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timer@b120000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x0b120000 0x0 0x1000>;
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ranges = <0 0 0 0x10000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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frame@b121000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b121000 0x1000>,
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<0x0b122000 0x1000>;
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};
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frame@b123000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b123000 0x1000>;
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status = "disabled";
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};
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frame@b124000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b124000 0x1000>;
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status = "disabled";
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};
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frame@b125000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b125000 0x1000>;
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status = "disabled";
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};
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frame@b126000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b126000 0x1000>;
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status = "disabled";
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};
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frame@b127000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b127000 0x1000>;
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status = "disabled";
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};
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frame@b128000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b128000 0x1000>;
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status = "disabled";
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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