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wifi: rtw89: mac: set EDCCA configurations for RTL8922D
Update EDCCA settings of MAC part for RTL8922D to consider EDCCA state signaled by BB circuit. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260108120320.2217402-14-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
parent
6996a4c97a
commit
40714b8a21
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@ -5818,6 +5818,7 @@ int rtw89_core_start(struct rtw89_dev *rtwdev)
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rtw89_phy_dm_init(rtwdev);
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rtw89_mac_set_edcca_mode_bands(rtwdev, true);
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rtw89_mac_cfg_ppdu_status_bands(rtwdev, true);
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rtw89_mac_cfg_phy_rpt_bands(rtwdev, true);
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rtw89_mac_update_rts_threshold(rtwdev);
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@ -7309,6 +7309,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = {
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.typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax,
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.cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax,
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.cfg_phy_rpt = NULL,
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.set_edcca_mode = NULL,
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.dle_mix_cfg = dle_mix_cfg_ax,
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.chk_dle_rdy = chk_dle_rdy_ax,
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@ -1055,6 +1055,7 @@ struct rtw89_mac_gen_def {
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u8 mac_idx);
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int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
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void (*cfg_phy_rpt)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
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void (*set_edcca_mode)(struct rtw89_dev *rtwdev, u8 mac_idx, bool normal);
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int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg);
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int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple);
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@ -1129,6 +1130,14 @@ u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band)
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return band == 0 ? reg_base : (reg_base + mac->band1_offset);
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}
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static inline void
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rtw89_write16_idx(struct rtw89_dev *rtwdev, u32 addr, u16 data, u8 band)
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{
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addr = rtw89_mac_reg_by_idx(rtwdev, addr, band);
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rtw89_write16(rtwdev, addr, data);
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}
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static inline
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u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx)
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{
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@ -1364,6 +1373,24 @@ int rtw89_mac_cfg_ppdu_status_bands(struct rtw89_dev *rtwdev, bool enable)
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return rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_1, enable);
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}
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static inline
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void rtw89_mac_set_edcca_mode(struct rtw89_dev *rtwdev, u8 mac_idx, bool normal)
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{
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const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
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if (!mac->set_edcca_mode)
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return;
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mac->set_edcca_mode(rtwdev, mac_idx, normal);
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}
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static inline
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void rtw89_mac_set_edcca_mode_bands(struct rtw89_dev *rtwdev, bool normal)
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{
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rtw89_mac_set_edcca_mode(rtwdev, RTW89_MAC_0, normal);
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rtw89_mac_set_edcca_mode(rtwdev, RTW89_MAC_1, normal);
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}
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void rtw89_mac_set_rx_fltr(struct rtw89_dev *rtwdev, u8 mac_idx, u32 rx_fltr);
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void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev);
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void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
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@ -2391,6 +2391,65 @@ void rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
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}
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EXPORT_SYMBOL(rtw89_mac_cfg_phy_rpt_be);
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static
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void rtw89_mac_set_edcca_mode_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool normal)
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{
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u16 resp_ack, resp_rts, resp_rts_punc, resp_normal, resp_normal_punc;
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if (rtwdev->chip->chip_id == RTL8922A)
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return;
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resp_ack = RESP_ACK_CFG_BE;
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resp_rts = RESP_RTS_CFG_BE;
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resp_rts_punc = RESP_RTS_PUNC_CFG_BE;
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resp_normal = RESP_NORMAL_CFG_BE;
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resp_normal_punc = RESP_NORMAL_PUNC_CFG_BE;
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if (normal) {
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rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_LEGACY,
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resp_ack, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_HE,
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resp_ack, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC,
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resp_ack, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY,
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resp_rts, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY_PUNC,
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resp_rts_punc, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY,
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resp_normal, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY_PUNC,
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resp_normal_punc, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_LEGACY,
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resp_normal, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_HE,
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resp_normal_punc, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_EHT_LEG_PUNC,
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resp_normal_punc, mac_idx);
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} else {
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rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_LEGACY,
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resp_normal, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_HE,
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resp_normal_punc, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC,
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resp_normal_punc, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY,
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resp_rts, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY_PUNC,
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resp_rts_punc, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY,
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resp_normal, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY_PUNC,
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resp_normal_punc, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_LEGACY,
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resp_normal, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_HE,
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resp_normal_punc, mac_idx);
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rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_EHT_LEG_PUNC,
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resp_normal_punc, mac_idx);
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}
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}
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static
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int rtw89_mac_cfg_ppdu_status_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
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{
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@ -2993,6 +3052,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = {
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.typ_fltr_opt = rtw89_mac_typ_fltr_opt_be,
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.cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_be,
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.cfg_phy_rpt = rtw89_mac_cfg_phy_rpt_be,
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.set_edcca_mode = rtw89_mac_set_edcca_mode_be,
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.dle_mix_cfg = dle_mix_cfg_be,
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.chk_dle_rdy = chk_dle_rdy_be,
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@ -7488,6 +7488,8 @@
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#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA20 BIT(2)
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#define B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA BIT(1)
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#define B_BE_ACK_BA_RESP_LEGACY_CHK_CCA BIT(0)
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#define RESP_ACK_CFG_BE (B_BE_ACK_BA_RESP_LEGACY_CHK_BTCCA | \
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B_BE_ACK_BA_RESP_LEGACY_CHK_TX_NAV)
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#define R_BE_WMAC_ACK_BA_RESP_HE 0x11204
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#define R_BE_WMAC_ACK_BA_RESP_HE_C1 0x15204
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@ -7529,6 +7531,188 @@
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#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA BIT(1)
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#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_CCA BIT(0)
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#define R_BE_WMAC_RX_RTS_RESP_LEGACY 0x1120C
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#define R_BE_WMAC_RX_RTS_RESP_LEGACY_C1 0x1520C
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_NSTR BIT(16)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_TX_NAV BIT(15)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_INTRA_NAV BIT(14)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_BASIC_NAV BIT(13)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_BTCCA BIT(12)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA160 BIT(11)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA80 BIT(10)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA40 BIT(9)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA20 BIT(8)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA_PER20_BMP BIT(7)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_CCA_PER20_BMP BIT(6)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA160 BIT(5)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA80 BIT(4)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA40 BIT(3)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA20 BIT(2)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA BIT(1)
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#define B_BE_RX_RTS_RESP_LEGACY_CHK_CCA BIT(0)
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#define RESP_RTS_CFG_BE (B_BE_RX_RTS_RESP_LEGACY_CHK_CCA | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA20 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA40 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA80 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA160 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA20 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA40 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA80 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA160 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_BTCCA | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_BASIC_NAV | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_INTRA_NAV | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_TX_NAV)
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#define RESP_RTS_PUNC_CFG_BE (B_BE_RX_RTS_RESP_LEGACY_CHK_CCA | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_CCA_PER20_BMP | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA_PER20_BMP | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_BTCCA | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_BASIC_NAV | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_INTRA_NAV | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_TX_NAV)
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#define RESP_NORMAL_CFG_BE (B_BE_RX_RTS_RESP_LEGACY_CHK_CCA | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA20 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA40 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA80 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA160 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA20 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA40 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA80 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA160 | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_BTCCA | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_BASIC_NAV | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_TX_NAV)
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#define RESP_NORMAL_PUNC_CFG_BE (B_BE_RX_RTS_RESP_LEGACY_CHK_CCA | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_CCA_PER20_BMP | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA_PER20_BMP | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_BTCCA | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_BASIC_NAV | \
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B_BE_RX_RTS_RESP_LEGACY_CHK_TX_NAV)
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#define R_BE_WMAC_RX_RTS_RESP_LEGACY_PUNC 0x11210
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#define R_BE_WMAC_RX_RTS_RESP_LEGACY_PUNC_C1 0x15210
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_NSTR BIT(16)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_TX_NAV BIT(15)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_INTRA_NAV BIT(14)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_BASIC_NAV BIT(13)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_BTCCA BIT(12)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA160 BIT(11)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA80 BIT(10)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA40 BIT(9)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA20 BIT(8)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_EDCCA_PER20_BMP BIT(7)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_CCA_PER20_BMP BIT(6)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_CCA160 BIT(5)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_CCA80 BIT(4)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_CCA40 BIT(3)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_CCA20 BIT(2)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_EDCCA BIT(1)
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#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_CCA BIT(0)
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#define R_BE_WMAC_RX_MURTS_RESP_LEGACY 0x11214
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#define R_BE_WMAC_RX_MURTS_RESP_LEGACY_C1 0x15214
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#define B_BE_MURTS_RESP_LEGACY_CHK_NSTR BIT(16)
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#define B_BE_MURTS_RESP_LEGACY_CHK_TX_NAV BIT(15)
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#define B_BE_MURTS_RESP_LEGACY_CHK_INTRA_NAV BIT(14)
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#define B_BE_MURTS_RESP_LEGACY_CHK_BASIC_NAV BIT(13)
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#define B_BE_MURTS_RESP_LEGACY_CHK_BTCCA BIT(12)
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#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_EDCCA160 BIT(11)
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#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_EDCCA80 BIT(10)
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#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_EDCCA40 BIT(9)
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#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_EDCCA20 BIT(8)
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#define B_BE_MURTS_RESP_LEGACY_CHK_EDCCA_PER20_BMP BIT(7)
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#define B_BE_MURTS_RESP_LEGACY_CHK_CCA_PER20_BMP BIT(6)
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#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_CCA160 BIT(5)
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#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_CCA80 BIT(4)
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#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_CCA40 BIT(3)
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#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_CCA20 BIT(2)
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#define B_BE_MURTS_RESP_LEGACY_CHK_EDCCA BIT(1)
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#define B_BE_MURTS_RESP_LEGACY_CHK_CCA BIT(0)
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#define R_BE_WMAC_RX_MURTS_RESP_LEGACY_PUNC 0x11218
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#define R_BE_WMAC_RX_MURTS_RESP_LEGACY_PUNC_C1 0x15218
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_NSTR BIT(16)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_TX_NAV BIT(15)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_INTRA_NAV BIT(14)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_BASIC_NAV BIT(13)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_BTCCA BIT(12)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA160 BIT(11)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA80 BIT(10)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA40 BIT(9)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA20 BIT(8)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_EDCCA_PER20_BMP BIT(7)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_CCA_PER20_BMP BIT(6)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_CCA160 BIT(5)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_CCA80 BIT(4)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_CCA40 BIT(3)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_CCA20 BIT(2)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_EDCCA BIT(1)
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#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_CCA BIT(0)
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#define R_BE_WMAC_OTHERS_RESP_LEGACY 0x1121C
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#define R_BE_WMAC_OTHERS_RESP_LEGACY_C1 0x1521C
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#define B_BE_OTHERS_RESP_LEGACY_CHK_NSTR BIT(16)
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#define B_BE_OTHERS_RESP_LEGACY_CHK_TX_NAV BIT(15)
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#define B_BE_OTHERS_RESP_LEGACY_CHK_INTRA_NAV BIT(14)
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#define B_BE_OTHERS_RESP_LEGACY_CHK_BASIC_NAV BIT(13)
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#define B_BE_OTHERS_RESP_LEGACY_CHK_BTCCA BIT(12)
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#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_EDCCA160 BIT(11)
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#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_EDCCA80 BIT(10)
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#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_EDCCA40 BIT(9)
|
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#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_EDCCA20 BIT(8)
|
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#define B_BE_OTHERS_RESP_LEGACY_CHK_EDCCA_PER20_BMP BIT(7)
|
||||
#define B_BE_OTHERS_RESP_LEGACY_CHK_CCA_PER20_BMP BIT(6)
|
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#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_CCA160 BIT(5)
|
||||
#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_CCA80 BIT(4)
|
||||
#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_CCA40 BIT(3)
|
||||
#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_CCA20 BIT(2)
|
||||
#define B_BE_OTHERS_RESP_LEGACY_CHK_EDCCA BIT(1)
|
||||
#define B_BE_OTHERS_RESP_LEGACY_CHK_CCA BIT(0)
|
||||
|
||||
#define R_BE_WMAC_OTHERS_RESP_HE 0x11220
|
||||
#define R_BE_WMAC_OTHERS_RESP_HE_C1 0x15220
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_NSTR BIT(16)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_TX_NAV BIT(15)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_INTRA_NAV BIT(14)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_BASIC_NAV BIT(13)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_BTCCA BIT(12)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_SEC_EDCCA160 BIT(11)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_SEC_EDCCA80 BIT(10)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_SEC_EDCCA40 BIT(9)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_SEC_EDCCA20 BIT(8)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_EDCCA_PER20_BMP BIT(7)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_CCA_PER20_BMP BIT(6)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_SEC_CCA160 BIT(5)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_SEC_CCA80 BIT(4)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_SEC_CCA40 BIT(3)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_SEC_CCA20 BIT(2)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_EDCCA BIT(1)
|
||||
#define B_BE_OTHERS_RESP_HE_CHK_CCA BIT(0)
|
||||
|
||||
#define R_BE_WMAC_OTHERS_RESP_EHT_LEG_PUNC 0x11224
|
||||
#define R_BE_WMAC_OTHERS_RESP_EHT_LEG_PUNC_C1 0x15224
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_NSTR BIT(16)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_TX_NAV BIT(15)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_INTRA_NAV BIT(14)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_BASIC_NAV BIT(13)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_BTCCA BIT(12)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_EDCCA160 BIT(11)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_EDCCA80 BIT(10)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_EDCCA40 BIT(9)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_EDCCA20 BIT(8)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_EDCCA_PER20_BMP BIT(7)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_CCA_PER20_BMP BIT(6)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_CCA160 BIT(5)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_CCA80 BIT(4)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_CCA40 BIT(3)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_CCA20 BIT(2)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_EDCCA BIT(1)
|
||||
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_CCA BIT(0)
|
||||
|
||||
#define R_BE_RCR 0x11400
|
||||
#define R_BE_RCR_C1 0x15400
|
||||
#define B_BE_BUSY_CHKSN BIT(15)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user