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drm/msm/dpu: Add missing safe_lut_tbl in sc8280xp catalog
commita33b2431d1upstream. During USB transfers on the SC8280XP __arm_smmu_tlb_sync() is seen to typically take 1-2ms to complete. As expected this results in poor performance, something that has been mitigated by proposing running the iommu in non-strict mode (boot with iommu.strict=0). This turns out to be related to the SAFE logic, and programming the QOS SAFE values in the DPU (per suggestion from Rob and Doug) reduces the TLB sync time to below 10us, which means significant less time spent with interrupts disabled and a significant boost in throughput. Fixes:4a352c2fc1("drm/msm/dpu: Introduce SC8280XP") Cc: stable@vger.kernel.org Suggested-by: Doug Anderson <dianders@chromium.org> Suggested-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Tested-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/565094/ Link: https://lore.kernel.org/r/20231030-sc8280xp-dpu-safe-lut-v1-1-6d485d7b428f@quicinc.com Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -419,6 +419,7 @@ static const struct dpu_perf_cfg sc8280xp_perf_data = {
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.min_llcc_ib = 0,
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.min_dram_ib = 800000,
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.danger_lut_tbl = {0xf, 0xffff, 0x0},
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.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc8180x_qos_linear),
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.entries = sc8180x_qos_linear
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