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drm/amdgpu: remove legacy UMC v12_0 error address

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remove legacy UMC v12_0 error address conversion

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Ce Sun <cesun102@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ce Sun 2026-06-03 15:07:57 +08:00 committed by Alex Deucher
parent 8a8793f006
commit 404665cf00
1 changed files with 0 additions and 93 deletions
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93
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
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@ -178,98 +178,6 @@ static void umc_v12_0_get_retire_flip_bits(struct amdgpu_device *adev)
adev->umc.retire_unit = 0x1 << flip_bits->bit_num;
}
static int umc_v12_0_convert_error_address(struct amdgpu_device *adev,
struct ras_err_data *err_data,
struct ta_ras_query_address_input *addr_in,
struct ta_ras_query_address_output *addr_out,
bool dump_addr)
{
uint32_t row = 0, row_lower = 0, row_high = 0;
uint32_t col = 0, col_lower = 0, bank = 0;
uint32_t channel_index = 0, umc_inst = 0;
uint32_t i, bit_num, retire_unit, *flip_bits;
uint64_t soc_pa, column, err_addr;
struct ta_ras_query_address_output addr_out_tmp;
struct ta_ras_query_address_output *paddr_out;
int ret = 0;
if (!addr_out)
paddr_out = &addr_out_tmp;
else
paddr_out = addr_out;
err_addr = bank = 0;
if (addr_in) {
err_addr = addr_in->ma.err_addr;
addr_in->addr_type = TA_RAS_MCA_TO_PA;
ret = psp_ras_query_address(&adev->psp, addr_in, paddr_out);
if (ret) {
dev_warn(adev->dev, "Failed to query RAS physical address for 0x%llx",
err_addr);
goto out;
}
bank = paddr_out->pa.bank;
/* no need to care about umc inst if addr_in is NULL */
umc_inst = addr_in->ma.umc_inst;
}
flip_bits = adev->umc.flip_bits.flip_bits_in_pa;
bit_num = adev->umc.flip_bits.bit_num;
retire_unit = adev->umc.retire_unit;
soc_pa = paddr_out->pa.pa;
channel_index = paddr_out->pa.channel_idx;
/* clear loop bits in soc physical address */
for (i = 0; i < bit_num; i++)
soc_pa &= ~BIT_ULL(flip_bits[i]);
paddr_out->pa.pa = soc_pa;
/* get column bit 0 and 1 in mca address */
col_lower = (err_addr >> 1) & 0x3ULL;
/* extra row bit will be handled later */
row_lower = (err_addr >> UMC_V12_0_MA_R0_BIT) & 0x1fffULL;
row_lower &= ~BIT_ULL(adev->umc.flip_bits.flip_row_bit);
if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 5, 0)) {
row_high = (soc_pa >> adev->umc.flip_bits.r13_in_pa) & 0x3ULL;
/* it's 2.25GB in each channel, from MCA address to PA
* [R14 R13] is converted if the two bits value are 0x3,
* get them from PA instead of MCA address.
*/
row_lower |= (row_high << 13);
}
if (!err_data && !dump_addr)
goto out;
/* loop for all possibilities of retired bits */
for (column = 0; column < retire_unit; column++) {
soc_pa = paddr_out->pa.pa;
for (i = 0; i < bit_num; i++)
soc_pa |= (((column >> i) & 0x1ULL) << flip_bits[i]);
col = ((column & 0x7) << 2) | col_lower;
/* handle extra row bit */
if (bit_num == RETIRE_FLIP_BITS_NUM)
row = ((column >> 3) << adev->umc.flip_bits.flip_row_bit) |
row_lower;
if (dump_addr)
dev_info(adev->dev,
"Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x Bank:0x%x Channel:0x%x\n",
soc_pa, row, col, bank, channel_index);
if (err_data)
amdgpu_umc_fill_error_record(err_data, err_addr,
soc_pa, channel_index, umc_inst);
}
out:
return ret;
}
static bool umc_v12_0_check_ecc_err_status(struct amdgpu_device *adev,
enum amdgpu_mca_error_type type, void *ras_error_status)
{
@ -332,7 +240,6 @@ struct amdgpu_umc_ras umc_v12_0_ras = {
.hw_ops = NULL,
},
.check_ecc_err_status = umc_v12_0_check_ecc_err_status,
.convert_ras_err_addr = umc_v12_0_convert_error_address,
.get_die_id_from_pa = umc_v12_0_get_die_id,
.get_retire_flip_bits = umc_v12_0_get_retire_flip_bits,
.mca_ipid_parse = umc_v12_0_mca_ipid_parse,