From e35a7607e05d59d35e937b80532ae93d1dd2493f Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 8 Dec 2025 08:29:08 +0100 Subject: [PATCH 1/8] spi: stm32-ospi: Set DMA maxburst dynamically Set src_maxburst and dst_maxburst dynamically from DMA capabilities. Signed-off-by: Patrice Chotard Link: https://patch.msgid.link/20251208-upstream_qspi_ospi_updates-v2-1-62526c9467dc@foss.st.com Signed-off-by: Mark Brown --- drivers/spi/spi-stm32-ospi.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-stm32-ospi.c b/drivers/spi/spi-stm32-ospi.c index f36fd36da269..d733e37f0435 100644 --- a/drivers/spi/spi-stm32-ospi.c +++ b/drivers/spi/spi-stm32-ospi.c @@ -278,10 +278,19 @@ static irqreturn_t stm32_ospi_irq(int irq, void *dev_id) return IRQ_HANDLED; } -static void stm32_ospi_dma_setup(struct stm32_ospi *ospi, - struct dma_slave_config *dma_cfg) +static int stm32_ospi_dma_setup(struct stm32_ospi *ospi, + struct dma_slave_config *dma_cfg) { + struct dma_slave_caps caps; + int ret = 0; + if (dma_cfg && ospi->dma_chrx) { + ret = dma_get_slave_caps(ospi->dma_chrx, &caps); + if (ret) + return ret; + + dma_cfg->src_maxburst = caps.max_burst / dma_cfg->src_addr_width; + if (dmaengine_slave_config(ospi->dma_chrx, dma_cfg)) { dev_err(ospi->dev, "dma rx config failed\n"); dma_release_channel(ospi->dma_chrx); @@ -290,6 +299,12 @@ static void stm32_ospi_dma_setup(struct stm32_ospi *ospi, } if (dma_cfg && ospi->dma_chtx) { + ret = dma_get_slave_caps(ospi->dma_chtx, &caps); + if (ret) + return ret; + + dma_cfg->dst_maxburst = caps.max_burst / dma_cfg->dst_addr_width; + if (dmaengine_slave_config(ospi->dma_chtx, dma_cfg)) { dev_err(ospi->dev, "dma tx config failed\n"); dma_release_channel(ospi->dma_chtx); @@ -298,6 +313,8 @@ static void stm32_ospi_dma_setup(struct stm32_ospi *ospi, } init_completion(&ospi->dma_completion); + + return ret; } static int stm32_ospi_tx_mm(struct stm32_ospi *ospi, @@ -899,9 +916,9 @@ static int stm32_ospi_probe(struct platform_device *pdev) dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; dma_cfg.src_addr = ospi->regs_phys_base + OSPI_DR; dma_cfg.dst_addr = ospi->regs_phys_base + OSPI_DR; - dma_cfg.src_maxburst = 4; - dma_cfg.dst_maxburst = 4; - stm32_ospi_dma_setup(ospi, &dma_cfg); + ret = stm32_ospi_dma_setup(ospi, &dma_cfg); + if (ret) + return ret; mutex_init(&ospi->lock); From cfe58ffc95a601988702df6f3462cb54dde467e9 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 8 Dec 2025 08:29:09 +0100 Subject: [PATCH 2/8] spi: stm32-ospi: Optimize FIFO accesses using u16 or u32 FIFO accesses uses u8 only for read/write. In order to optimize throughput, add u16 or u32 read/write accesses when possible. Running mtd_speedtest on a 4MB sNOR partition using a stm32mp257f-ev1 board gives the following results: before after gain Read : 5693 KiB/s 21139 KiB/s 371% Write: 765 KiB/s 910 KiB/s 19% Signed-off-by: Patrice Chotard Link: https://patch.msgid.link/20251208-upstream_qspi_ospi_updates-v2-2-62526c9467dc@foss.st.com Signed-off-by: Mark Brown --- drivers/spi/spi-stm32-ospi.c | 47 +++++++++++++++++++++++++++++------- 1 file changed, 38 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-stm32-ospi.c b/drivers/spi/spi-stm32-ospi.c index d733e37f0435..a6f53f06200e 100644 --- a/drivers/spi/spi-stm32-ospi.c +++ b/drivers/spi/spi-stm32-ospi.c @@ -142,14 +142,32 @@ struct stm32_ospi { struct mutex lock; }; -static void stm32_ospi_read_fifo(u8 *val, void __iomem *addr) +static void stm32_ospi_read_fifo(void *val, void __iomem *addr, u8 len) { - *val = readb_relaxed(addr); + switch (len) { + case sizeof(u32): + *((u32 *)val) = readl_relaxed(addr); + break; + case sizeof(u16): + *((u16 *)val) = readw_relaxed(addr); + break; + case sizeof(u8): + *((u8 *)val) = readb_relaxed(addr); + }; } -static void stm32_ospi_write_fifo(u8 *val, void __iomem *addr) +static void stm32_ospi_write_fifo(void *val, void __iomem *addr, u8 len) { - writeb_relaxed(*val, addr); + switch (len) { + case sizeof(u32): + writel_relaxed(*((u32 *)val), addr); + break; + case sizeof(u16): + writew_relaxed(*((u16 *)val), addr); + break; + case sizeof(u8): + writeb_relaxed(*((u8 *)val), addr); + }; } static int stm32_ospi_abort(struct stm32_ospi *ospi) @@ -172,19 +190,20 @@ static int stm32_ospi_abort(struct stm32_ospi *ospi) return timeout; } -static int stm32_ospi_poll(struct stm32_ospi *ospi, u8 *buf, u32 len, bool read) +static int stm32_ospi_poll(struct stm32_ospi *ospi, void *buf, u32 len, bool read) { void __iomem *regs_base = ospi->regs_base; - void (*fifo)(u8 *val, void __iomem *addr); + void (*fifo)(void *val, void __iomem *addr, u8 len); u32 sr; int ret; + u8 step; if (read) fifo = stm32_ospi_read_fifo; else fifo = stm32_ospi_write_fifo; - while (len--) { + while (len) { ret = readl_relaxed_poll_timeout_atomic(regs_base + OSPI_SR, sr, sr & SR_FTF, 1, STM32_FIFO_TIMEOUT_US); @@ -193,7 +212,17 @@ static int stm32_ospi_poll(struct stm32_ospi *ospi, u8 *buf, u32 len, bool read) len, sr); return ret; } - fifo(buf++, regs_base + OSPI_DR); + + if (len >= sizeof(u32)) + step = sizeof(u32); + else if (len >= sizeof(u16)) + step = sizeof(u16); + else + step = sizeof(u8); + + fifo(buf, regs_base + OSPI_DR, step); + len -= step; + buf += step; } return 0; @@ -408,7 +437,7 @@ static int stm32_ospi_xfer(struct stm32_ospi *ospi, const struct spi_mem_op *op) if (op->data.dir == SPI_MEM_DATA_IN) buf = op->data.buf.in; else - buf = (u8 *)op->data.buf.out; + buf = (void *)op->data.buf.out; return stm32_ospi_poll(ospi, buf, op->data.nbytes, op->data.dir == SPI_MEM_DATA_IN); From f6ed06926b510f54a0817567ffd458194ed90bd6 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 8 Dec 2025 08:29:10 +0100 Subject: [PATCH 3/8] spi: stm32-ospi: Remove CR_TCIE and CR_TEIE irq usage Replace CR_TCIE and CR_TEIE irq usage by a read_poll_timeout_atomic() in stm32_ospi_wait_cmd(). It will reduce the time waiting for TCF or TEF flags to optimize throughput. before after average time spent in stm32_omi_wait_cmd: 5685 ns 923 ns Signed-off-by: Patrice Chotard Link: https://patch.msgid.link/20251208-upstream_qspi_ospi_updates-v2-3-62526c9467dc@foss.st.com Signed-off-by: Mark Brown --- drivers/spi/spi-stm32-ospi.c | 31 ++++++------------------------- 1 file changed, 6 insertions(+), 25 deletions(-) diff --git a/drivers/spi/spi-stm32-ospi.c b/drivers/spi/spi-stm32-ospi.c index a6f53f06200e..06632cdd1630 100644 --- a/drivers/spi/spi-stm32-ospi.c +++ b/drivers/spi/spi-stm32-ospi.c @@ -34,8 +34,6 @@ #define CR_ABORT BIT(1) #define CR_DMAEN BIT(2) #define CR_FTHRES_SHIFT 8 -#define CR_TEIE BIT(16) -#define CR_TCIE BIT(17) #define CR_SMIE BIT(19) #define CR_APMS BIT(22) #define CR_CSSEL BIT(24) @@ -106,7 +104,7 @@ #define STM32_ABT_TIMEOUT_US 100000 #define STM32_COMP_TIMEOUT_MS 5000 #define STM32_BUSY_TIMEOUT_US 100000 - +#define STM32_WAIT_CMD_TIMEOUT_US 5000 #define STM32_AUTOSUSPEND_DELAY -1 @@ -116,7 +114,6 @@ struct stm32_ospi { struct clk *clk; struct reset_control *rstc; - struct completion data_completion; struct completion match_completion; struct dma_chan *dma_chtx; @@ -240,22 +237,16 @@ static int stm32_ospi_wait_nobusy(struct stm32_ospi *ospi) static int stm32_ospi_wait_cmd(struct stm32_ospi *ospi) { void __iomem *regs_base = ospi->regs_base; - u32 cr, sr; + u32 sr; int err = 0; - if ((readl_relaxed(regs_base + OSPI_SR) & SR_TCF) || - ospi->fmode == CR_FMODE_APM) + if (ospi->fmode == CR_FMODE_APM) goto out; - reinit_completion(&ospi->data_completion); - cr = readl_relaxed(regs_base + OSPI_CR); - writel_relaxed(cr | CR_TCIE | CR_TEIE, regs_base + OSPI_CR); + err = readl_relaxed_poll_timeout_atomic(ospi->regs_base + OSPI_SR, sr, + (sr & (SR_TEF | SR_TCF)), 1, + STM32_WAIT_CMD_TIMEOUT_US); - if (!wait_for_completion_timeout(&ospi->data_completion, - msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) - err = -ETIMEDOUT; - - sr = readl_relaxed(regs_base + OSPI_SR); if (sr & SR_TCF) /* avoid false timeout */ err = 0; @@ -293,15 +284,6 @@ static irqreturn_t stm32_ospi_irq(int irq, void *dev_id) cr &= ~CR_SMIE; writel_relaxed(cr, regs_base + OSPI_CR); complete(&ospi->match_completion); - - return IRQ_HANDLED; - } - - if (sr & (SR_TEF | SR_TCF)) { - /* disable irq */ - cr &= ~CR_TCIE & ~CR_TEIE; - writel_relaxed(cr, regs_base + OSPI_CR); - complete(&ospi->data_completion); } return IRQ_HANDLED; @@ -884,7 +866,6 @@ static int stm32_ospi_get_resources(struct platform_device *pdev) dev_info(dev, "No memory-map region found\n"); } - init_completion(&ospi->data_completion); init_completion(&ospi->match_completion); return 0; From e2f0ea18e560e5fa6180f52dffe434525a0cf86b Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 8 Dec 2025 08:29:11 +0100 Subject: [PATCH 4/8] spi: stm32-ospi: Simplify SMIE interrupt test SR_SMF status bit can only be set if CR_SMIE was previously set, keep status bit check only. Signed-off-by: Patrice Chotard Link: https://patch.msgid.link/20251208-upstream_qspi_ospi_updates-v2-4-62526c9467dc@foss.st.com Signed-off-by: Mark Brown --- drivers/spi/spi-stm32-ospi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-stm32-ospi.c b/drivers/spi/spi-stm32-ospi.c index 06632cdd1630..c36df8d3f5cb 100644 --- a/drivers/spi/spi-stm32-ospi.c +++ b/drivers/spi/spi-stm32-ospi.c @@ -279,7 +279,7 @@ static irqreturn_t stm32_ospi_irq(int irq, void *dev_id) cr = readl_relaxed(regs_base + OSPI_CR); sr = readl_relaxed(regs_base + OSPI_SR); - if (cr & CR_SMIE && sr & SR_SMF) { + if (sr & SR_SMF) { /* disable irq */ cr &= ~CR_SMIE; writel_relaxed(cr, regs_base + OSPI_CR); From 4ef80c71c62ab841db9b1a9d74ffe043c60f6222 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 8 Dec 2025 08:29:12 +0100 Subject: [PATCH 5/8] spi: stm32-qspi: Set DMA maxburst dynamically Set src_maxburst and dst_maxburst dynamically from DMA capabilities. Signed-off-by: Patrice Chotard Link: https://patch.msgid.link/20251208-upstream_qspi_ospi_updates-v2-5-62526c9467dc@foss.st.com Signed-off-by: Mark Brown --- drivers/spi/spi-stm32-qspi.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c index f2d19f1c5ab1..c131441e4dd4 100644 --- a/drivers/spi/spi-stm32-qspi.c +++ b/drivers/spi/spi-stm32-qspi.c @@ -689,6 +689,7 @@ static int stm32_qspi_dma_setup(struct stm32_qspi *qspi) { struct dma_slave_config dma_cfg; struct device *dev = qspi->dev; + struct dma_slave_caps caps; int ret = 0; memset(&dma_cfg, 0, sizeof(dma_cfg)); @@ -697,8 +698,6 @@ static int stm32_qspi_dma_setup(struct stm32_qspi *qspi) dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; dma_cfg.src_addr = qspi->phys_base + QSPI_DR; dma_cfg.dst_addr = qspi->phys_base + QSPI_DR; - dma_cfg.src_maxburst = 4; - dma_cfg.dst_maxburst = 4; qspi->dma_chrx = dma_request_chan(dev, "rx"); if (IS_ERR(qspi->dma_chrx)) { @@ -707,6 +706,11 @@ static int stm32_qspi_dma_setup(struct stm32_qspi *qspi) if (ret == -EPROBE_DEFER) goto out; } else { + ret = dma_get_slave_caps(qspi->dma_chrx, &caps); + if (ret) + return ret; + + dma_cfg.src_maxburst = caps.max_burst / dma_cfg.src_addr_width; if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) { dev_err(dev, "dma rx config failed\n"); dma_release_channel(qspi->dma_chrx); @@ -719,6 +723,11 @@ static int stm32_qspi_dma_setup(struct stm32_qspi *qspi) ret = PTR_ERR(qspi->dma_chtx); qspi->dma_chtx = NULL; } else { + ret = dma_get_slave_caps(qspi->dma_chtx, &caps); + if (ret) + return ret; + + dma_cfg.dst_maxburst = caps.max_burst / dma_cfg.dst_addr_width; if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) { dev_err(dev, "dma tx config failed\n"); dma_release_channel(qspi->dma_chtx); From 1ca91281649547efa4be34584a304974c9601df1 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 8 Dec 2025 08:29:13 +0100 Subject: [PATCH 6/8] spi: stm32-qspi: Optimize FIFO accesses using u16 or u32 FIFO accesses uses u8 only for read/write. In order to optimize throughput, add u16 or u32 read/write accesses when possible. Running mtd_speedtest on a 4MB sNOR partition using a stm32mp257f-ev1 board gives the following results: before after gain Read : 5773 KiB/s 22170 KiB/s 384% Write: 796 KiB/s 890 KiB/s 12% Signed-off-by: Patrice Chotard Link: https://patch.msgid.link/20251208-upstream_qspi_ospi_updates-v2-6-62526c9467dc@foss.st.com Signed-off-by: Mark Brown --- drivers/spi/spi-stm32-qspi.c | 51 ++++++++++++++++++++++++++++-------- 1 file changed, 40 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c index c131441e4dd4..c7f2b435d5ee 100644 --- a/drivers/spi/spi-stm32-qspi.c +++ b/drivers/spi/spi-stm32-qspi.c @@ -153,34 +153,53 @@ static irqreturn_t stm32_qspi_irq(int irq, void *dev_id) return IRQ_HANDLED; } -static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr) +static void stm32_qspi_read_fifo(void *val, void __iomem *addr, u8 len) { - *val = readb_relaxed(addr); + switch (len) { + case sizeof(u32): + *((u32 *)val) = readl_relaxed(addr); + break; + case sizeof(u16): + *((u16 *)val) = readw_relaxed(addr); + break; + case sizeof(u8): + *((u8 *)val) = readb_relaxed(addr); + }; } -static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr) +static void stm32_qspi_write_fifo(void *val, void __iomem *addr, u8 len) { - writeb_relaxed(*val, addr); + switch (len) { + case sizeof(u32): + writel_relaxed(*((u32 *)val), addr); + break; + case sizeof(u16): + writew_relaxed(*((u16 *)val), addr); + break; + case sizeof(u8): + writeb_relaxed(*((u8 *)val), addr); + }; } static int stm32_qspi_tx_poll(struct stm32_qspi *qspi, const struct spi_mem_op *op) { - void (*tx_fifo)(u8 *val, void __iomem *addr); + void (*fifo)(void *val, void __iomem *addr, u8 len); u32 len = op->data.nbytes, sr; - u8 *buf; + void *buf; int ret; + u8 step; if (op->data.dir == SPI_MEM_DATA_IN) { - tx_fifo = stm32_qspi_read_fifo; + fifo = stm32_qspi_read_fifo; buf = op->data.buf.in; } else { - tx_fifo = stm32_qspi_write_fifo; - buf = (u8 *)op->data.buf.out; + fifo = stm32_qspi_write_fifo; + buf = (void *)op->data.buf.out; } - while (len--) { + while (len) { ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr, (sr & SR_FTF), 1, STM32_FIFO_TIMEOUT_US); @@ -189,7 +208,17 @@ static int stm32_qspi_tx_poll(struct stm32_qspi *qspi, len, sr); return ret; } - tx_fifo(buf++, qspi->io_base + QSPI_DR); + + if (len >= sizeof(u32)) + step = sizeof(u32); + else if (len >= sizeof(u16)) + step = sizeof(u16); + else + step = sizeof(u8); + + fifo(buf, qspi->io_base + QSPI_DR, step); + len -= step; + buf += step; } return 0; From c5f76d888810bca2d46297a7b942e10bc8cc69dd Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 8 Dec 2025 08:29:14 +0100 Subject: [PATCH 7/8] spi: stm32-qspi: Remove CR_TCIE and CR_TEIE irq usage Replace CR_TCIE and CR_TEIE irq usage by a read_poll_timeout_atomic() in stm32_qspi_wait_cmd(). It will reduce the time waiting for TCF or TEF flags to optimize throughput. before after average time spent in stm32_qspi_wait_cmd: 2615 ns 712 ns Signed-off-by: Patrice Chotard Link: https://patch.msgid.link/20251208-upstream_qspi_ospi_updates-v2-7-62526c9467dc@foss.st.com Signed-off-by: Mark Brown --- drivers/spi/spi-stm32-qspi.c | 45 +++++++++++------------------------- 1 file changed, 13 insertions(+), 32 deletions(-) diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c index c7f2b435d5ee..d6f6f9d4e5be 100644 --- a/drivers/spi/spi-stm32-qspi.c +++ b/drivers/spi/spi-stm32-qspi.c @@ -31,8 +31,6 @@ #define CR_DFM BIT(6) #define CR_FSEL BIT(7) #define CR_FTHRES_SHIFT 8 -#define CR_TEIE BIT(16) -#define CR_TCIE BIT(17) #define CR_FTIE BIT(18) #define CR_SMIE BIT(19) #define CR_TOIE BIT(20) @@ -86,11 +84,12 @@ #define STM32_QSPI_MAX_MMAP_SZ SZ_256M #define STM32_QSPI_MAX_NORCHIP 2 -#define STM32_FIFO_TIMEOUT_US 30000 -#define STM32_BUSY_TIMEOUT_US 100000 -#define STM32_ABT_TIMEOUT_US 100000 -#define STM32_COMP_TIMEOUT_MS 1000 -#define STM32_AUTOSUSPEND_DELAY -1 +#define STM32_FIFO_TIMEOUT_US 30000 +#define STM32_BUSY_TIMEOUT_US 100000 +#define STM32_ABT_TIMEOUT_US 100000 +#define STM32_WAIT_CMD_TIMEOUT_US 5000 +#define STM32_COMP_TIMEOUT_MS 1000 +#define STM32_AUTOSUSPEND_DELAY -1 struct stm32_qspi_flash { u32 cs; @@ -107,7 +106,6 @@ struct stm32_qspi { struct clk *clk; u32 clk_rate; struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP]; - struct completion data_completion; struct completion match_completion; u32 fmode; @@ -139,15 +137,6 @@ static irqreturn_t stm32_qspi_irq(int irq, void *dev_id) cr &= ~CR_SMIE; writel_relaxed(cr, qspi->io_base + QSPI_CR); complete(&qspi->match_completion); - - return IRQ_HANDLED; - } - - if (sr & (SR_TEF | SR_TCF)) { - /* disable irq */ - cr &= ~CR_TCIE & ~CR_TEIE; - writel_relaxed(cr, qspi->io_base + QSPI_CR); - complete(&qspi->data_completion); } return IRQ_HANDLED; @@ -330,25 +319,18 @@ static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi) static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi) { - u32 cr, sr; + u32 sr; int err = 0; - if ((readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF) || - qspi->fmode == CCR_FMODE_APM) + if (qspi->fmode == CCR_FMODE_APM) goto out; - reinit_completion(&qspi->data_completion); - cr = readl_relaxed(qspi->io_base + QSPI_CR); - writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR); + err = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr, + (sr & (SR_TEF | SR_TCF)), 1, + STM32_WAIT_CMD_TIMEOUT_US); - if (!wait_for_completion_timeout(&qspi->data_completion, - msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) { - err = -ETIMEDOUT; - } else { - sr = readl_relaxed(qspi->io_base + QSPI_SR); - if (sr & SR_TEF) - err = -EIO; - } + if (sr & SR_TEF) + err = -EIO; out: /* clear flags */ @@ -835,7 +817,6 @@ static int stm32_qspi_probe(struct platform_device *pdev) return ret; } - init_completion(&qspi->data_completion); init_completion(&qspi->match_completion); qspi->clk = devm_clk_get(dev, NULL); From fee876b2ec75dcc18fdea154eae1f5bf14d82659 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 8 Dec 2025 08:29:15 +0100 Subject: [PATCH 8/8] spi: stm32-qspi: Simplify SMIE interrupt test SR_SMF status bit can only be set if CR_SMIE was previously set, keep status bit check only. Signed-off-by: Patrice Chotard Link: https://patch.msgid.link/20251208-upstream_qspi_ospi_updates-v2-8-62526c9467dc@foss.st.com Signed-off-by: Mark Brown --- drivers/spi/spi-stm32-qspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c index d6f6f9d4e5be..2a0ee96786fa 100644 --- a/drivers/spi/spi-stm32-qspi.c +++ b/drivers/spi/spi-stm32-qspi.c @@ -132,7 +132,7 @@ static irqreturn_t stm32_qspi_irq(int irq, void *dev_id) cr = readl_relaxed(qspi->io_base + QSPI_CR); sr = readl_relaxed(qspi->io_base + QSPI_SR); - if (cr & CR_SMIE && sr & SR_SMF) { + if (sr & SR_SMF) { /* disable irq */ cr &= ~CR_SMIE; writel_relaxed(cr, qspi->io_base + QSPI_CR);