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clk: socfpga: Make sure clk_init_data is fully initialized
The clk_init_data structure contains several mutually-exclusive members for different methods to specify the possible parents of a clock, prompting drivers to initialize only the members they need. However, not initializing all members may cause subtle issues, which are only exposed when CONFIG_INIT_STACK_ALL_PATTERN or CONFIG_INIT_STACK_NONE is enabled. Make sure all members are fully initialized, to avoid such bugs, and to prevent future breakage when converting drivers to a different method for specifying the parents. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Message-ID: <2d38d78f8d59583e29778bebc65eaab911d8a120.1787239813.git.geert+renesas@glider.be> Signed-off-by: Brian Masney <bmasney@redhat.com>
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@ -49,7 +49,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
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struct socfpga_gate_clk *socfpga_clk;
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const char *clk_name = node->name;
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const char *parent_name[SOCFPGA_MAX_PARENTS];
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struct clk_init_data init;
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struct clk_init_data init = {};
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int rc;
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socfpga_clk = kzalloc_obj(*socfpga_clk);
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@ -128,7 +128,7 @@ struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void _
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{
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struct clk_hw *hw_clk;
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struct socfpga_gate_clk *socfpga_clk;
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struct clk_init_data init;
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struct clk_init_data init = {};
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const char *parent_name = clks->parent_name;
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int ret;
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@ -186,7 +186,7 @@ struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, voi
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{
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struct clk_hw *hw_clk;
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struct socfpga_gate_clk *socfpga_clk;
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struct clk_init_data init;
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struct clk_init_data init = {};
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const char *parent_name = clks->parent_name;
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int ret;
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@ -244,7 +244,7 @@ struct clk_hw *agilex5_register_gate(const struct agilex5_gate_clock *clks, void
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{
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struct clk_hw *hw_clk;
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struct socfpga_gate_clk *socfpga_clk;
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struct clk_init_data init;
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struct clk_init_data init = {};
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int ret;
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socfpga_clk = kzalloc_obj(*socfpga_clk);
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@ -143,7 +143,7 @@ void __init socfpga_gate_init(struct device_node *node)
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struct socfpga_gate_clk *socfpga_clk;
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const char *clk_name = node->name;
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const char *parent_name[SOCFPGA_MAX_PARENTS];
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struct clk_init_data init;
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struct clk_init_data init = {};
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struct clk_ops *ops;
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int rc;
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@ -65,7 +65,7 @@ static void __init __socfpga_periph_init(struct device_node *node,
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struct socfpga_periph_clk *periph_clk;
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const char *clk_name = node->name;
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const char *parent_name[SOCFPGA_MAX_PARENTS];
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struct clk_init_data init;
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struct clk_init_data init = {};
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int rc;
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u32 fixed_div;
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u32 div_reg[3];
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@ -103,7 +103,7 @@ struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
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{
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struct clk_hw *hw_clk;
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struct socfpga_periph_clk *periph_clk;
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struct clk_init_data init;
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struct clk_init_data init = {};
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const char *name = clks->name;
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const char *parent_name = clks->parent_name;
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int ret;
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@ -139,7 +139,7 @@ struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
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{
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struct clk_hw *hw_clk;
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struct socfpga_periph_clk *periph_clk;
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struct clk_init_data init;
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struct clk_init_data init = {};
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const char *name = clks->name;
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const char *parent_name = clks->parent_name;
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int ret;
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@ -174,7 +174,7 @@ struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *c
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{
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struct clk_hw *hw_clk;
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struct socfpga_periph_clk *periph_clk;
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struct clk_init_data init;
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struct clk_init_data init = {};
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const char *name = clks->name;
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const char *parent_name = clks->parent_name;
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int ret;
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@ -220,7 +220,7 @@ struct clk_hw *agilex5_register_cnt_periph(const struct agilex5_perip_cnt_clock
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{
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struct clk_hw *hw_clk;
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struct socfpga_periph_clk *periph_clk;
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struct clk_init_data init;
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struct clk_init_data init = {};
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const char *name = clks->name;
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int ret;
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@ -55,7 +55,7 @@ static void __init __socfpga_periph_init(struct device_node *node,
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struct socfpga_periph_clk *periph_clk;
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const char *clk_name = node->name;
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const char *parent_name[SOCFPGA_MAX_PARENTS];
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struct clk_init_data init;
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struct clk_init_data init = {};
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int rc;
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u32 fixed_div;
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u32 div_reg[3];
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@ -71,7 +71,7 @@ static void __init __socfpga_pll_init(struct device_node *node,
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struct socfpga_pll *pll_clk;
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const char *clk_name = node->name;
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const char *parent_name[SOCFGPA_MAX_PARENTS];
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struct clk_init_data init;
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struct clk_init_data init = {};
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struct device_node *clkmgr_np;
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int rc;
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int i = 0;
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@ -192,7 +192,7 @@ struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
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{
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struct clk_hw *hw_clk;
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struct socfpga_pll *pll_clk;
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struct clk_init_data init;
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struct clk_init_data init = {};
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const char *name = clks->name;
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int ret;
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@ -232,7 +232,7 @@ struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
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{
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struct clk_hw *hw_clk;
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struct socfpga_pll *pll_clk;
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struct clk_init_data init;
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struct clk_init_data init = {};
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const char *name = clks->name;
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int ret;
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@ -271,7 +271,7 @@ struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
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{
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struct clk_hw *hw_clk;
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struct socfpga_pll *pll_clk;
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struct clk_init_data init;
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struct clk_init_data init = {};
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const char *name = clks->name;
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int ret;
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@ -310,7 +310,7 @@ struct clk_hw *agilex5_register_pll(const struct agilex5_pll_clock *clks,
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{
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struct clk_hw *hw_clk;
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struct socfpga_pll *pll_clk;
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struct clk_init_data init;
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struct clk_init_data init = {};
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const char *name = clks->name;
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int ret;
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@ -78,7 +78,7 @@ static void __init __socfpga_pll_init(struct device_node *node,
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struct socfpga_pll *pll_clk;
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const char *clk_name = node->name;
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const char *parent_name[SOCFPGA_MAX_PARENTS];
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struct clk_init_data init;
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struct clk_init_data init = {};
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struct device_node *clkmgr_np;
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int rc;
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