clk: socfpga: Make sure clk_init_data is fully initialized

The clk_init_data structure contains several mutually-exclusive members
for different methods to specify the possible parents of a clock,
prompting drivers to initialize only the members they need.  However,
not initializing all members may cause subtle issues, which are only
exposed when CONFIG_INIT_STACK_ALL_PATTERN or CONFIG_INIT_STACK_NONE is
enabled.

Make sure all members are fully initialized, to avoid such bugs, and to
prevent future breakage when converting drivers to a different method
for specifying the parents.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Message-ID: <2d38d78f8d59583e29778bebc65eaab911d8a120.1787239813.git.geert+renesas@glider.be>
Signed-off-by: Brian Masney <bmasney@redhat.com>
This commit is contained in:
Geert Uytterhoeven 2026-08-21 10:53:42 +02:00 committed by Brian Masney
parent 292a454790
commit 40322814a6
9 changed files with 17 additions and 17 deletions

View File

@ -49,7 +49,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
struct socfpga_gate_clk *socfpga_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
struct clk_init_data init = {};
int rc;
socfpga_clk = kzalloc_obj(*socfpga_clk);

View File

@ -128,7 +128,7 @@ struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void _
{
struct clk_hw *hw_clk;
struct socfpga_gate_clk *socfpga_clk;
struct clk_init_data init;
struct clk_init_data init = {};
const char *parent_name = clks->parent_name;
int ret;
@ -186,7 +186,7 @@ struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, voi
{
struct clk_hw *hw_clk;
struct socfpga_gate_clk *socfpga_clk;
struct clk_init_data init;
struct clk_init_data init = {};
const char *parent_name = clks->parent_name;
int ret;
@ -244,7 +244,7 @@ struct clk_hw *agilex5_register_gate(const struct agilex5_gate_clock *clks, void
{
struct clk_hw *hw_clk;
struct socfpga_gate_clk *socfpga_clk;
struct clk_init_data init;
struct clk_init_data init = {};
int ret;
socfpga_clk = kzalloc_obj(*socfpga_clk);

View File

@ -143,7 +143,7 @@ void __init socfpga_gate_init(struct device_node *node)
struct socfpga_gate_clk *socfpga_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
struct clk_init_data init = {};
struct clk_ops *ops;
int rc;

View File

@ -65,7 +65,7 @@ static void __init __socfpga_periph_init(struct device_node *node,
struct socfpga_periph_clk *periph_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
struct clk_init_data init = {};
int rc;
u32 fixed_div;
u32 div_reg[3];

View File

@ -103,7 +103,7 @@ struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
{
struct clk_hw *hw_clk;
struct socfpga_periph_clk *periph_clk;
struct clk_init_data init;
struct clk_init_data init = {};
const char *name = clks->name;
const char *parent_name = clks->parent_name;
int ret;
@ -139,7 +139,7 @@ struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
{
struct clk_hw *hw_clk;
struct socfpga_periph_clk *periph_clk;
struct clk_init_data init;
struct clk_init_data init = {};
const char *name = clks->name;
const char *parent_name = clks->parent_name;
int ret;
@ -174,7 +174,7 @@ struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *c
{
struct clk_hw *hw_clk;
struct socfpga_periph_clk *periph_clk;
struct clk_init_data init;
struct clk_init_data init = {};
const char *name = clks->name;
const char *parent_name = clks->parent_name;
int ret;
@ -220,7 +220,7 @@ struct clk_hw *agilex5_register_cnt_periph(const struct agilex5_perip_cnt_clock
{
struct clk_hw *hw_clk;
struct socfpga_periph_clk *periph_clk;
struct clk_init_data init;
struct clk_init_data init = {};
const char *name = clks->name;
int ret;

View File

@ -55,7 +55,7 @@ static void __init __socfpga_periph_init(struct device_node *node,
struct socfpga_periph_clk *periph_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
struct clk_init_data init = {};
int rc;
u32 fixed_div;
u32 div_reg[3];

View File

@ -71,7 +71,7 @@ static void __init __socfpga_pll_init(struct device_node *node,
struct socfpga_pll *pll_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFGPA_MAX_PARENTS];
struct clk_init_data init;
struct clk_init_data init = {};
struct device_node *clkmgr_np;
int rc;
int i = 0;

View File

@ -192,7 +192,7 @@ struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
{
struct clk_hw *hw_clk;
struct socfpga_pll *pll_clk;
struct clk_init_data init;
struct clk_init_data init = {};
const char *name = clks->name;
int ret;
@ -232,7 +232,7 @@ struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
{
struct clk_hw *hw_clk;
struct socfpga_pll *pll_clk;
struct clk_init_data init;
struct clk_init_data init = {};
const char *name = clks->name;
int ret;
@ -271,7 +271,7 @@ struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
{
struct clk_hw *hw_clk;
struct socfpga_pll *pll_clk;
struct clk_init_data init;
struct clk_init_data init = {};
const char *name = clks->name;
int ret;
@ -310,7 +310,7 @@ struct clk_hw *agilex5_register_pll(const struct agilex5_pll_clock *clks,
{
struct clk_hw *hw_clk;
struct socfpga_pll *pll_clk;
struct clk_init_data init;
struct clk_init_data init = {};
const char *name = clks->name;
int ret;

View File

@ -78,7 +78,7 @@ static void __init __socfpga_pll_init(struct device_node *node,
struct socfpga_pll *pll_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
struct clk_init_data init = {};
struct device_node *clkmgr_np;
int rc;