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intel-iommu: Force-disable IOMMU for iGFX on broken Cantiga revisions.

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commit 2d9e667efd upstream.

Certain revisions of this chipset appear to be broken. There is a shadow
GTT which mirrors the real GTT but contains pre-translated physical
addresses, for performance reasons. When a GTT update happens, the
translations are done once and the resulting physical addresses written
back to the shadow GTT.

Except sometimes, the physical address is actually written back to the
_real_ GTT, not the shadow GTT. Thus we start to see faults when that
physical address is fed through translation again.

Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
David Woodhouse 2010-06-15 10:57:57 +01:00 committed by Greg Kroah-Hartman
parent e281433b15
commit 400036c2e5
1 changed files with 7 additions and 1 deletions
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8
drivers/pci/intel-iommu.c
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@ -382,7 +382,7 @@ int dmar_disabled = 0;
int dmar_disabled = 1;
#endif /*CONFIG_DMAR_DEFAULT_ON*/
static int __initdata dmar_map_gfx = 1;
static int dmar_map_gfx = 1;
static int dmar_forcedac;
static int intel_iommu_strict;
@ -3741,6 +3741,12 @@ static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
*/
printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
rwbf_quirk = 1;
/* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */
if (dev->revision == 0x07) {
printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
dmar_map_gfx = 0;
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);