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drm/i915/psr: Introduce helper intel_psr_set_non_psr_pipes()

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Add a function to set non-psr pipes in crtc_state based on psr features.
This will help to move this part later where we re-evaluate psr features
and update the non-psr pipes.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20251016055415.2101347-7-ankit.k.nautiyal@intel.com
This commit is contained in:
Ankit Nautiyal 2025-10-16 11:24:10 +05:30
parent e00eb31a5a
commit 3fdae52c3d
1 changed files with 29 additions and 20 deletions
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49
drivers/gpu/drm/i915/display/intel_psr.c
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@ -1711,15 +1711,40 @@ static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp,
!crtc_state->has_sel_update);
}
static
void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(intel_dp);
struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
struct intel_crtc *crtc;
u8 active_pipes = 0;
/* Wa_16025596647 */
if (DISPLAY_VER(display) != 20 &&
!IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
return;
/* Not needed by Panel Replay */
if (crtc_state->has_panel_replay)
return;
/* We ignore possible secondary PSR/Panel Replay capable eDP */
for_each_intel_crtc(display->drm, crtc)
active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;
active_pipes = intel_calc_active_pipes(state, active_pipes);
crtc_state->active_non_psr_pipes = active_pipes &
~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe);
}
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(intel_dp);
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
struct intel_crtc *crtc;
u8 active_pipes = 0;
if (!psr_global_enabled(intel_dp)) {
drm_dbg_kms(display->drm, "PSR disabled by flag\n");
@ -1768,23 +1793,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
"PSR disabled to workaround PSR FSM hang issue\n");
}
/* Rest is for Wa_16025596647 */
if (DISPLAY_VER(display) != 20 &&
!IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
return;
/* Not needed by Panel Replay */
if (crtc_state->has_panel_replay)
return;
/* We ignore possible secondary PSR/Panel Replay capable eDP */
for_each_intel_crtc(display->drm, crtc)
active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;
active_pipes = intel_calc_active_pipes(state, active_pipes);
crtc_state->active_non_psr_pipes = active_pipes &
~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe);
intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
}
void intel_psr_get_config(struct intel_encoder *encoder,