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video: tegra: host: Disable 3d powergating
It is possible for the 3d block to generate an invalid memory request during the power up sequence in some cases. Workaround is to disable 3d block power gating. Change-Id: I10efad1f7d3dada7cd3fe18e268f06d60bdbab67 Signed-off-by: Colin Cross <ccross@android.com>
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@ -30,6 +30,8 @@
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#define ACM_TIMEOUT 1*HZ
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#define DISABLE_3D_POWERGATING
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void nvhost_module_busy(struct nvhost_module *mod)
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{
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mutex_lock(&mod->lock);
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@ -139,6 +141,21 @@ int nvhost_module_init(struct nvhost_module *mod, const char *name,
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mod->parent = parent;
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mod->powered = false;
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mod->powergate_id = get_module_powergate_id(name);
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#ifdef DISABLE_3D_POWERGATING
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/*
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* It is possible for the 3d block to generate an invalid memory
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* request during the power up sequence in some cases. Workaround
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* is to disable 3d block power gating.
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*/
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if (mod->powergate_id == TEGRA_POWERGATE_3D) {
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tegra_powergate_sequence_power_up(mod->powergate_id,
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mod->clk[0]);
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clk_disable(mod->clk[0]);
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mod->powergate_id = -1;
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}
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#endif
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mutex_init(&mod->lock);
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init_waitqueue_head(&mod->idle);
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INIT_DELAYED_WORK(&mod->powerdown, powerdown_handler);
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