github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-09 07:03:37 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drivers/net/wireless/rockchip_wlan: remove unused rtl8723bs-vq0 driver

Browse Source 
Change-Id: Ibe4beed8468c6617873964afb51af1e15d7a2a72
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This commit is contained in:
Tao Huang 2018-11-06 19:52:50 +08:00
parent 95ae164f15
commit 3fc6120369
377 changed files with 0 additions and 302568 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/Kconfig
View File

@ -1,5 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
config RTL8723BS_VQ0
tristate "Realtek 8723BS-VQ0 COB WiFi"
---help---
Help message of RTL8723BS-VQ0 COB

1510
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/Makefile
View File

File diff suppressed because it is too large Load Diff

5
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/clean
View File

@ -1,5 +0,0 @@
#!/bin/bash
rmmod 8192cu
rmmod 8192ce
rmmod 8192du
rmmod 8192de

1436
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/efuse/rtw_efuse.c
View File

File diff suppressed because it is too large Load Diff

3515
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_ap.c
View File

File diff suppressed because it is too large Load Diff

1010
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_beamforming.c
View File

File diff suppressed because it is too large Load Diff

1696
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_br_ext.c
View File

File diff suppressed because it is too large Load Diff

1775
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_bt_mp.c
View File

File diff suppressed because it is too large Load Diff

391
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_btcoex.c
View File

@ -1,391 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2013 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifdef CONFIG_BT_COEXIST
#include <rtw_btcoex.h>
#include <hal_btcoex.h>
void rtw_btcoex_Initialize(PADAPTER padapter)
{
hal_btcoex_Initialize(padapter);
}
void rtw_btcoex_PowerOnSetting(PADAPTER padapter)
{
hal_btcoex_PowerOnSetting(padapter);
}
void rtw_btcoex_PreLoadFirmware(PADAPTER padapter)
{
hal_btcoex_PreLoadFirmware(padapter);
}
void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly)
{
hal_btcoex_InitHwConfig(padapter, bWifiOnly);
}
void rtw_btcoex_IpsNotify(PADAPTER padapter, u8 type)
{
hal_btcoex_IpsNotify(padapter, type);
}
void rtw_btcoex_LpsNotify(PADAPTER padapter, u8 type)
{
hal_btcoex_LpsNotify(padapter, type);
}
void rtw_btcoex_ScanNotify(PADAPTER padapter, u8 type)
{
#ifdef CONFIG_CONCURRENT_MODE
if ((_FALSE == type) && (padapter->pbuddy_adapter))
{
PADAPTER pbuddy = padapter->pbuddy_adapter;
if (check_fwstate(&pbuddy->mlmepriv, WIFI_SITE_MONITOR) == _TRUE)
return;
}
#endif
hal_btcoex_ScanNotify(padapter, type);
}
void rtw_btcoex_ConnectNotify(PADAPTER padapter, u8 action)
{
#ifdef DBG_CONFIG_ERROR_RESET
if (_TRUE == rtw_hal_sreset_inprogress(padapter))
{
DBG_8192C(FUNC_ADPT_FMT ": [BTCoex] under reset, skip notify!\n",
FUNC_ADPT_ARG(padapter));
return;
}
#endif // DBG_CONFIG_ERROR_RESET
#ifdef CONFIG_CONCURRENT_MODE
if ((_FALSE == action) && (padapter->pbuddy_adapter))
{
PADAPTER pbuddy = padapter->pbuddy_adapter;
if (check_fwstate(&pbuddy->mlmepriv, WIFI_UNDER_LINKING) == _TRUE)
return;
}
#endif
hal_btcoex_ConnectNotify(padapter, action);
}
void rtw_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus)
{
#ifdef DBG_CONFIG_ERROR_RESET
if (_TRUE == rtw_hal_sreset_inprogress(padapter))
{
DBG_8192C(FUNC_ADPT_FMT ": [BTCoex] under reset, skip notify!\n",
FUNC_ADPT_ARG(padapter));
return;
}
#endif // DBG_CONFIG_ERROR_RESET
#ifdef CONFIG_CONCURRENT_MODE
if ((RT_MEDIA_DISCONNECT == mediaStatus) && (padapter->pbuddy_adapter))
{
PADAPTER pbuddy = padapter->pbuddy_adapter;
if (check_fwstate(&pbuddy->mlmepriv, WIFI_ASOC_STATE) == _TRUE)
return;
}
#endif // CONFIG_CONCURRENT_MODE
if ((RT_MEDIA_CONNECT == mediaStatus)
&& (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE))
{
rtw_hal_set_hwreg(padapter, HW_VAR_DL_RSVD_PAGE, NULL);
}
hal_btcoex_MediaStatusNotify(padapter, mediaStatus);
}
void rtw_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType)
{
hal_btcoex_SpecialPacketNotify(padapter, pktType);
}
void rtw_btcoex_IQKNotify(PADAPTER padapter, u8 state)
{
hal_btcoex_IQKNotify(padapter, state);
}
void rtw_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
{
hal_btcoex_BtInfoNotify(padapter, length, tmpBuf);
}
void rtw_btcoex_SuspendNotify(PADAPTER padapter, u8 state)
{
hal_btcoex_SuspendNotify(padapter, state);
}
void rtw_btcoex_HaltNotify(PADAPTER padapter)
{
if (_FALSE == padapter->bup)
{
DBG_871X(FUNC_ADPT_FMT ": bup=%d Skip!\n",
FUNC_ADPT_ARG(padapter), padapter->bup);
return;
}
if (_TRUE == padapter->bSurpriseRemoved)
{
DBG_871X(FUNC_ADPT_FMT ": bSurpriseRemoved=%d Skip!\n",
FUNC_ADPT_ARG(padapter), padapter->bSurpriseRemoved);
return;
}
hal_btcoex_HaltNotify(padapter);
}
void rtw_btcoex_SwitchBtTRxMask(PADAPTER padapter)
{
hal_btcoex_SwitchBtTRxMask(padapter);
}
void rtw_btcoex_Switch(PADAPTER padapter, u8 enable)
{
hal_btcoex_SetBTCoexist(padapter, enable);
}
u8 rtw_btcoex_IsBtDisabled(PADAPTER padapter)
{
return hal_btcoex_IsBtDisabled(padapter);
}
void rtw_btcoex_Handler(PADAPTER padapter)
{
#if defined(CONFIG_CONCURRENT_MODE)
if (padapter->adapter_type != PRIMARY_ADAPTER)
return;
#endif
hal_btcoex_Hanlder(padapter);
}
s32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter)
{
s32 coexctrl;
coexctrl = hal_btcoex_IsBTCoexCtrlAMPDUSize(padapter);
return coexctrl;
}
u32 rtw_btcoex_GetAMPDUSize(PADAPTER padapter)
{
u32 size;
size = hal_btcoex_GetAMPDUSize(padapter);
return size;
}
void rtw_btcoex_SetManualControl(PADAPTER padapter, u8 manual)
{
if (_TRUE == manual)
{
hal_btcoex_SetManualControl(padapter, _TRUE);
}
else
{
hal_btcoex_SetManualControl(padapter, _FALSE);
}
}
u8 rtw_btcoex_1Ant(PADAPTER padapter)
{
return hal_btcoex_1Ant(padapter);
}
u8 rtw_btcoex_IsBtControlLps(PADAPTER padapter)
{
return hal_btcoex_IsBtControlLps(padapter);
}
u8 rtw_btcoex_IsLpsOn(PADAPTER padapter)
{
return hal_btcoex_IsLpsOn(padapter);
}
u8 rtw_btcoex_RpwmVal(PADAPTER padapter)
{
return hal_btcoex_RpwmVal(padapter);
}
u8 rtw_btcoex_LpsVal(PADAPTER padapter)
{
return hal_btcoex_LpsVal(padapter);
}
void rtw_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist)
{
hal_btcoex_SetBTCoexist(padapter, bBtExist);
}
void rtw_btcoex_SetChipType(PADAPTER padapter, u8 chipType)
{
hal_btcoex_SetChipType(padapter, chipType);
}
void rtw_btcoex_SetPGAntNum(PADAPTER padapter, u8 antNum)
{
hal_btcoex_SetPgAntNum(padapter, antNum);
}
u8 rtw_btcoex_GetPGAntNum(PADAPTER padapter)
{
return hal_btcoex_GetPgAntNum(padapter);
}
void rtw_btcoex_SetSingleAntPath(PADAPTER padapter, u8 singleAntPath)
{
hal_btcoex_SetSingleAntPath(padapter, singleAntPath);
}
u32 rtw_btcoex_GetRaMask(PADAPTER padapter)
{
return hal_btcoex_GetRaMask(padapter);
}
void rtw_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen)
{
hal_btcoex_RecordPwrMode(padapter, pCmdBuf, cmdLen);
}
void rtw_btcoex_DisplayBtCoexInfo(PADAPTER padapter, u8 *pbuf, u32 bufsize)
{
hal_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize);
}
void rtw_btcoex_SetDBG(PADAPTER padapter, u32 *pDbgModule)
{
hal_btcoex_SetDBG(padapter, pDbgModule);
}
u32 rtw_btcoex_GetDBG(PADAPTER padapter, u8 *pStrBuf, u32 bufSize)
{
return hal_btcoex_GetDBG(padapter, pStrBuf, bufSize);
}
u8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER padapter)
{
return hal_btcoex_IncreaseScanDeviceNum(padapter);
}
u8 rtw_btcoex_IsBtLinkExist(PADAPTER padapter)
{
return hal_btcoex_IsBtLinkExist(padapter);
}
// ==================================================
// Below Functions are called by BT-Coex
// ==================================================
void rtw_btcoex_RejectApAggregatedPacket(PADAPTER padapter, u8 enable)
{
struct mlme_ext_info *pmlmeinfo;
pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
if (_TRUE == enable)
{
struct sta_info *psta = NULL;
pmlmeinfo->bAcceptAddbaReq = _FALSE;
if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {
psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
if (psta)
send_delba(padapter, 0, psta->hwaddr);
} else if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
_irqL irqL;
_list *phead, *plist;
u8 peer_num = 0;
char peers[NUM_STA];
struct sta_priv *pstapriv = &padapter->stapriv;
int i;
_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
phead = &pstapriv->asoc_list;
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
int stainfo_offset;
psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
plist = get_next(plist);
stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
if (stainfo_offset_valid(stainfo_offset))
peers[peer_num++] = stainfo_offset;
}
_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
if (peer_num) {
for (i = 0; i < peer_num; i++) {
psta = rtw_get_stainfo_by_offset(pstapriv, peers[i]);
if (psta)
send_delba(padapter, 0, psta->hwaddr);
}
}
}
}
else
{
pmlmeinfo->bAcceptAddbaReq = _TRUE;
}
}
void rtw_btcoex_LPS_Enter(PADAPTER padapter)
{
struct pwrctrl_priv *pwrpriv;
u8 lpsVal;
pwrpriv = adapter_to_pwrctl(padapter);
pwrpriv->bpower_saving = _TRUE;
lpsVal = rtw_btcoex_LpsVal(padapter);
rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, lpsVal, "BTCOEX");
}
void rtw_btcoex_LPS_Leave(PADAPTER padapter)
{
struct pwrctrl_priv *pwrpriv;
pwrpriv = adapter_to_pwrctl(padapter);
if (pwrpriv->pwr_mode != PS_MODE_ACTIVE)
{
rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "BTCOEX");
LPS_RF_ON_check(padapter, 100);
pwrpriv->bpower_saving = _FALSE;
}
}
#endif // CONFIG_BT_COEXIST

3945
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_cmd.c
View File

File diff suppressed because it is too large Load Diff

2044
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_debug.c
View File

File diff suppressed because it is too large Load Diff

423
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_eeprom.c
View File

@ -1,423 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTW_EEPROM_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
void up_clk(_adapter* padapter, u16 *x)
{
_func_enter_;
*x = *x | _EESK;
rtw_write8(padapter, EE_9346CR, (u8)*x);
rtw_udelay_os(CLOCK_RATE);
_func_exit_;
}
void down_clk(_adapter * padapter, u16 *x )
{
_func_enter_;
*x = *x & ~_EESK;
rtw_write8(padapter, EE_9346CR, (u8)*x);
rtw_udelay_os(CLOCK_RATE);
_func_exit_;
}
void shift_out_bits(_adapter * padapter, u16 data, u16 count)
{
u16 x,mask;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
mask = 0x01 << (count - 1);
x = rtw_read8(padapter, EE_9346CR);
x &= ~(_EEDO | _EEDI);
do
{
x &= ~_EEDI;
if(data & mask)
x |= _EEDI;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
rtw_write8(padapter, EE_9346CR, (u8)x);
rtw_udelay_os(CLOCK_RATE);
up_clk(padapter, &x);
down_clk(padapter, &x);
mask = mask >> 1;
} while(mask);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x &= ~_EEDI;
rtw_write8(padapter, EE_9346CR, (u8)x);
out:
_func_exit_;
}
u16 shift_in_bits (_adapter * padapter)
{
u16 x,d=0,i;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x = rtw_read8(padapter, EE_9346CR);
x &= ~( _EEDO | _EEDI);
d = 0;
for(i=0; i<16; i++)
{
d = d << 1;
up_clk(padapter, &x);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x = rtw_read8(padapter, EE_9346CR);
x &= ~(_EEDI);
if(x & _EEDO)
d |= 1;
down_clk(padapter, &x);
}
out:
_func_exit_;
return d;
}
void standby(_adapter * padapter )
{
u8 x;
_func_enter_;
x = rtw_read8(padapter, EE_9346CR);
x &= ~(_EECS | _EESK);
rtw_write8(padapter, EE_9346CR,x);
rtw_udelay_os(CLOCK_RATE);
x |= _EECS;
rtw_write8(padapter, EE_9346CR, x);
rtw_udelay_os(CLOCK_RATE);
_func_exit_;
}
u16 wait_eeprom_cmd_done(_adapter* padapter)
{
u8 x;
u16 i,res=_FALSE;
_func_enter_;
standby(padapter );
for (i=0; i<200; i++)
{
x = rtw_read8(padapter, EE_9346CR);
if (x & _EEDO){
res=_TRUE;
goto exit;
}
rtw_udelay_os(CLOCK_RATE);
}
exit:
_func_exit_;
return res;
}
void eeprom_clean(_adapter * padapter)
{
u16 x;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x = rtw_read8(padapter, EE_9346CR);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x &= ~(_EECS | _EEDI);
rtw_write8(padapter, EE_9346CR, (u8)x);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
up_clk(padapter, &x);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
down_clk(padapter, &x);
out:
_func_exit_;
}
void eeprom_write16(_adapter * padapter, u16 reg, u16 data)
{
u8 x;
#ifdef CONFIG_RTL8712
u8 tmp8_ori,tmp8_new,tmp8_clk_ori,tmp8_clk_new;
tmp8_ori=rtw_read8(padapter, 0x102502f1);
tmp8_new=tmp8_ori & 0xf7;
if(tmp8_ori != tmp8_new){
rtw_write8(padapter, 0x102502f1, tmp8_new);
RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x102502f1=====\n"));
}
tmp8_clk_ori=rtw_read8(padapter,0x10250003);
tmp8_clk_new=tmp8_clk_ori|0x20;
if(tmp8_clk_new!=tmp8_clk_ori){
RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n"));
rtw_write8(padapter, 0x10250003, tmp8_clk_new);
}
#endif
_func_enter_;
x = rtw_read8(padapter, EE_9346CR);
x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
x |= _EEM1 | _EECS;
rtw_write8(padapter, EE_9346CR, x);
shift_out_bits(padapter, EEPROM_EWEN_OPCODE, 5);
if(padapter->EepromAddressSize==8) //CF+ and SDIO
shift_out_bits(padapter, 0, 6);
else //USB
shift_out_bits(padapter, 0, 4);
standby( padapter);
// Commented out by rcnjko, 2004.0
// // Erase this particular word. Write the erase opcode and register
// // number in that order. The opcode is 3bits in length; reg is 6 bits long.
// shift_out_bits(Adapter, EEPROM_ERASE_OPCODE, 3);
// shift_out_bits(Adapter, reg, Adapter->EepromAddressSize);
//
// if (wait_eeprom_cmd_done(Adapter ) == FALSE)
// {
// return;
// }
standby(padapter );
// write the new word to the EEPROM
// send the write opcode the EEPORM
shift_out_bits(padapter, EEPROM_WRITE_OPCODE, 3);
// select which word in the EEPROM that we are writing to.
shift_out_bits(padapter, reg, padapter->EepromAddressSize);
// write the data to the selected EEPROM word.
shift_out_bits(padapter, data, 16);
if (wait_eeprom_cmd_done(padapter ) == _FALSE)
{
goto exit;
}
standby(padapter );
shift_out_bits(padapter, EEPROM_EWDS_OPCODE, 5);
shift_out_bits(padapter, reg, 4);
eeprom_clean(padapter );
exit:
#ifdef CONFIG_RTL8712
if(tmp8_clk_new!=tmp8_clk_ori)
rtw_write8(padapter, 0x10250003, tmp8_clk_ori);
if(tmp8_new!=tmp8_ori)
rtw_write8(padapter, 0x102502f1, tmp8_ori);
#endif
_func_exit_;
return;
}
u16 eeprom_read16(_adapter * padapter, u16 reg) //ReadEEprom
{
u16 x;
u16 data=0;
#ifdef CONFIG_RTL8712
u8 tmp8_ori,tmp8_new,tmp8_clk_ori,tmp8_clk_new;
tmp8_ori= rtw_read8(padapter, 0x102502f1);
tmp8_new = tmp8_ori & 0xf7;
if(tmp8_ori != tmp8_new){
rtw_write8(padapter, 0x102502f1, tmp8_new);
RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x102502f1=====\n"));
}
tmp8_clk_ori=rtw_read8(padapter,0x10250003);
tmp8_clk_new=tmp8_clk_ori|0x20;
if(tmp8_clk_new!=tmp8_clk_ori){
RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n"));
rtw_write8(padapter, 0x10250003, tmp8_clk_new);
}
#endif
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
// select EEPROM, reset bits, set _EECS
x = rtw_read8(padapter, EE_9346CR);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
x |= _EEM1 | _EECS;
rtw_write8(padapter, EE_9346CR, (unsigned char)x);
// write the read opcode and register number in that order
// The opcode is 3bits in length, reg is 6 bits long
shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
shift_out_bits(padapter, reg, padapter->EepromAddressSize);
// Now read the data (16 bits) in from the selected EEPROM word
data = shift_in_bits(padapter);
eeprom_clean(padapter);
out:
#ifdef CONFIG_RTL8712
if(tmp8_clk_new!=tmp8_clk_ori)
rtw_write8(padapter, 0x10250003, tmp8_clk_ori);
if(tmp8_new!=tmp8_ori)
rtw_write8(padapter, 0x102502f1, tmp8_ori);
#endif
_func_exit_;
return data;
}
//From even offset
void eeprom_read_sz(_adapter * padapter, u16 reg, u8* data, u32 sz)
{
u16 x, data16;
u32 i;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
// select EEPROM, reset bits, set _EECS
x = rtw_read8(padapter, EE_9346CR);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
x |= _EEM1 | _EECS;
rtw_write8(padapter, EE_9346CR, (unsigned char)x);
// write the read opcode and register number in that order
// The opcode is 3bits in length, reg is 6 bits long
shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
shift_out_bits(padapter, reg, padapter->EepromAddressSize);
for(i=0; i<sz; i+=2)
{
data16 = shift_in_bits(padapter);
data[i] = data16 & 0xff;
data[i+1] = data16 >>8;
}
eeprom_clean(padapter);
out:
_func_exit_;
}
//addr_off : address offset of the entry in eeprom (not the tuple number of eeprom (reg); that is addr_off !=reg)
u8 eeprom_read(_adapter * padapter, u32 addr_off, u8 sz, u8* rbuf)
{
u8 quotient, remainder, addr_2align_odd;
u16 reg, stmp , i=0, idx = 0;
_func_enter_;
reg = (u16)(addr_off >> 1);
addr_2align_odd = (u8)(addr_off & 0x1);
if(addr_2align_odd) //read that start at high part: e.g 1,3,5,7,9,...
{
stmp = eeprom_read16(padapter, reg);
rbuf[idx++] = (u8) ((stmp>>8)&0xff); //return hogh-part of the short
reg++; sz--;
}
quotient = sz >> 1;
remainder = sz & 0x1;
for( i=0 ; i < quotient; i++)
{
stmp = eeprom_read16(padapter, reg+i);
rbuf[idx++] = (u8) (stmp&0xff);
rbuf[idx++] = (u8) ((stmp>>8)&0xff);
}
reg = reg+i;
if(remainder){ //end of read at lower part of short : 0,2,4,6,...
stmp = eeprom_read16(padapter, reg);
rbuf[idx] = (u8)(stmp & 0xff);
}
_func_exit_;
return _TRUE;
}
VOID read_eeprom_content(_adapter * padapter)
{
_func_enter_;
_func_exit_;
}

2299
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_ieee80211.c
View File

File diff suppressed because it is too large Load Diff

513
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_io.c
View File

@ -1,513 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*
The purpose of rtw_io.c
a. provides the API
b. provides the protocol engine
c. provides the software interface between caller and the hardware interface
Compiler Flag Option:
1. CONFIG_SDIO_HCI:
a. USE_SYNC_IRP: Only sync operations are provided.
b. USE_ASYNC_IRP:Both sync/async operations are provided.
2. CONFIG_USB_HCI:
a. USE_ASYNC_IRP: Both sync/async operations are provided.
3. CONFIG_CFIO_HCI:
b. USE_SYNC_IRP: Only sync operations are provided.
Only sync read/rtw_write_mem operations are provided.
jackson@realtek.com.tw
*/
#define _RTW_IO_C_
#include <drv_types.h>
#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
#error "Shall be Linux or Windows, but not both!\n"
#endif
#ifdef CONFIG_SDIO_HCI
#define rtw_le16_to_cpu(val) val
#define rtw_le32_to_cpu(val) val
#define rtw_cpu_to_le16(val) val
#define rtw_cpu_to_le32(val) val
#else
#define rtw_le16_to_cpu(val) le16_to_cpu(val)
#define rtw_le32_to_cpu(val) le32_to_cpu(val)
#define rtw_cpu_to_le16(val) cpu_to_le16(val)
#define rtw_cpu_to_le32(val) cpu_to_le32(val)
#endif
u8 _rtw_read8(_adapter *adapter, u32 addr)
{
u8 r_val;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr);
_func_enter_;
_read8 = pintfhdl->io_ops._read8;
r_val = _read8(pintfhdl, addr);
_func_exit_;
return r_val;
}
u16 _rtw_read16(_adapter *adapter, u32 addr)
{
u16 r_val;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr);
_func_enter_;
_read16 = pintfhdl->io_ops._read16;
r_val = _read16(pintfhdl, addr);
_func_exit_;
return rtw_le16_to_cpu(r_val);
}
u32 _rtw_read32(_adapter *adapter, u32 addr)
{
u32 r_val;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr);
_func_enter_;
_read32 = pintfhdl->io_ops._read32;
r_val = _read32(pintfhdl, addr);
_func_exit_;
return rtw_le32_to_cpu(r_val);
}
int _rtw_write8(_adapter *adapter, u32 addr, u8 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
int ret;
_func_enter_;
_write8 = pintfhdl->io_ops._write8;
ret = _write8(pintfhdl, addr, val);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
int _rtw_write16(_adapter *adapter, u32 addr, u16 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
int ret;
_func_enter_;
_write16 = pintfhdl->io_ops._write16;
val = rtw_cpu_to_le16(val);
ret = _write16(pintfhdl, addr, val);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
int _rtw_write32(_adapter *adapter, u32 addr, u32 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
int ret;
_func_enter_;
_write32 = pintfhdl->io_ops._write32;
val = rtw_cpu_to_le32(val);
ret = _write32(pintfhdl, addr, val);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
int _rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *pdata)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = (struct intf_hdl*)(&(pio_priv->intf));
int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr,u32 length, u8 *pdata);
int ret;
_func_enter_;
_writeN = pintfhdl->io_ops._writeN;
ret = _writeN(pintfhdl, addr,length,pdata);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
#ifdef CONFIG_SDIO_HCI
u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr)
{
u8 r_val = 0x00;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u8 (*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr);
_func_enter_;
_sd_f0_read8 = pintfhdl->io_ops._sd_f0_read8;
if (_sd_f0_read8)
r_val = _sd_f0_read8(pintfhdl, addr);
else
DBG_871X_LEVEL(_drv_warning_, FUNC_ADPT_FMT" _sd_f0_read8 callback is NULL\n", FUNC_ADPT_ARG(adapter));
_func_exit_;
return r_val;
}
#endif /* CONFIG_SDIO_HCI */
int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
int ret;
_func_enter_;
_write8_async = pintfhdl->io_ops._write8_async;
ret = _write8_async(pintfhdl, addr, val);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
int ret;
_func_enter_;
_write16_async = pintfhdl->io_ops._write16_async;
val = rtw_cpu_to_le16(val);
ret = _write16_async(pintfhdl, addr, val);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
int ret;
_func_enter_;
_write32_async = pintfhdl->io_ops._write32_async;
val = rtw_cpu_to_le32(val);
ret = _write32_async(pintfhdl, addr, val);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
_func_enter_;
if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE))
{
RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_mem:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));
return;
}
_read_mem = pintfhdl->io_ops._read_mem;
_read_mem(pintfhdl, addr, cnt, pmem);
_func_exit_;
}
void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
_func_enter_;
_write_mem = pintfhdl->io_ops._write_mem;
_write_mem(pintfhdl, addr, cnt, pmem);
_func_exit_;
}
void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
_func_enter_;
if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE))
{
RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_port:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));
return;
}
_read_port = pintfhdl->io_ops._read_port;
_read_port(pintfhdl, addr, cnt, pmem);
_func_exit_;
}
void _rtw_read_port_cancel(_adapter *adapter)
{
void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
_read_port_cancel = pintfhdl->io_ops._read_port_cancel;
RTW_DISABLE_FUNC(adapter, DF_RX_BIT);
if(_read_port_cancel)
_read_port_cancel(pintfhdl);
}
u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u32 ret = _SUCCESS;
_func_enter_;
_write_port = pintfhdl->io_ops._write_port;
ret = _write_port(pintfhdl, addr, cnt, pmem);
_func_exit_;
return ret;
}
u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms)
{
int ret = _SUCCESS;
struct xmit_buf *pxmitbuf = (struct xmit_buf *)pmem;
struct submit_ctx sctx;
rtw_sctx_init(&sctx, timeout_ms);
pxmitbuf->sctx = &sctx;
ret = _rtw_write_port(adapter, addr, cnt, pmem);
if (ret == _SUCCESS)
ret = rtw_sctx_wait(&sctx, __func__);
return ret;
}
void _rtw_write_port_cancel(_adapter *adapter)
{
void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
_write_port_cancel = pintfhdl->io_ops._write_port_cancel;
RTW_DISABLE_FUNC(adapter, DF_TX_BIT);
if(_write_port_cancel)
_write_port_cancel(pintfhdl);
}
int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter,struct _io_ops *pops))
{
struct io_priv *piopriv = &padapter->iopriv;
struct intf_hdl *pintf = &piopriv->intf;
if (set_intf_ops == NULL)
return _FAIL;
piopriv->padapter = padapter;
pintf->padapter = padapter;
pintf->pintf_dev = adapter_to_dvobj(padapter);
set_intf_ops(padapter,&pintf->io_ops);
return _SUCCESS;
}
/*
* Increase and check if the continual_io_error of this @param dvobjprive is larger than MAX_CONTINUAL_IO_ERR
* @return _TRUE:
* @return _FALSE:
*/
int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj)
{
int ret = _FALSE;
int value;
if( (value=ATOMIC_INC_RETURN(&dvobj->continual_io_error)) > MAX_CONTINUAL_IO_ERR) {
DBG_871X("[dvobj:%p][ERROR] continual_io_error:%d > %d\n", dvobj, value, MAX_CONTINUAL_IO_ERR);
ret = _TRUE;
} else {
//DBG_871X("[dvobj:%p] continual_io_error:%d\n", dvobj, value);
}
return ret;
}
/*
* Set the continual_io_error of this @param dvobjprive to 0
*/
void rtw_reset_continual_io_error(struct dvobj_priv *dvobj)
{
ATOMIC_SET(&dvobj->continual_io_error, 0);
}
#ifdef DBG_IO
u16 read_sniff_ranges[][2] = {
//{0x520, 0x523},
};
u16 write_sniff_ranges[][2] = {
//{0x520, 0x523},
//{0x4c, 0x4c},
};
int read_sniff_num = sizeof(read_sniff_ranges)/sizeof(u16)/2;
int write_sniff_num = sizeof(write_sniff_ranges)/sizeof(u16)/2;
bool match_read_sniff_ranges(u16 addr, u16 len)
{
int i;
for (i = 0; i<read_sniff_num; i++) {
if (addr + len > read_sniff_ranges[i][0] && addr <= read_sniff_ranges[i][1])
return _TRUE;
}
return _FALSE;
}
bool match_write_sniff_ranges(u16 addr, u16 len)
{
int i;
for (i = 0; i<write_sniff_num; i++) {
if (addr + len > write_sniff_ranges[i][0] && addr <= write_sniff_ranges[i][1])
return _TRUE;
}
return _FALSE;
}
u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u8 val = _rtw_read8(adapter, addr);
if (match_read_sniff_ranges(addr, 1))
DBG_871X("DBG_IO %s:%d rtw_read8(0x%04x) return 0x%02x\n", caller, line, addr, val);
return val;
}
u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u16 val = _rtw_read16(adapter, addr);
if (match_read_sniff_ranges(addr, 2))
DBG_871X("DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x\n", caller, line, addr, val);
return val;
}
u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u32 val = _rtw_read32(adapter, addr);
if (match_read_sniff_ranges(addr, 4))
DBG_871X("DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x\n", caller, line, addr, val);
return val;
}
int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 1))
DBG_871X("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x)\n", caller, line, addr, val);
return _rtw_write8(adapter, addr, val);
}
int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 2))
DBG_871X("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x)\n", caller, line, addr, val);
return _rtw_write16(adapter, addr, val);
}
int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 4))
DBG_871X("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x)\n", caller, line, addr, val);
return _rtw_write32(adapter, addr, val);
}
int dbg_rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, length))
DBG_871X("DBG_IO %s:%d rtw_writeN(0x%04x, %u)\n", caller, line, addr, length);
return _rtw_writeN(adapter, addr, length, data);
}
#endif

192
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_ioctl_query.c
View File

@ -1,192 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTW_IOCTL_QUERY_C_
#include <drv_types.h>
#ifdef PLATFORM_WINDOWS
//
// Added for WPA2-PSK, by Annie, 2005-09-20.
//
u8
query_802_11_capability(
_adapter* Adapter,
u8* pucBuf,
u32 * pulOutLen
)
{
static NDIS_802_11_AUTHENTICATION_ENCRYPTION szAuthEnc[] =
{
{Ndis802_11AuthModeOpen, Ndis802_11EncryptionDisabled},
{Ndis802_11AuthModeOpen, Ndis802_11Encryption1Enabled},
{Ndis802_11AuthModeShared, Ndis802_11EncryptionDisabled},
{Ndis802_11AuthModeShared, Ndis802_11Encryption1Enabled},
{Ndis802_11AuthModeWPA, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPA, Ndis802_11Encryption3Enabled},
{Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption3Enabled},
{Ndis802_11AuthModeWPANone, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPANone, Ndis802_11Encryption3Enabled},
{Ndis802_11AuthModeWPA2, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPA2, Ndis802_11Encryption3Enabled},
{Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption3Enabled}
};
static ULONG ulNumOfPairSupported = sizeof(szAuthEnc)/sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION);
NDIS_802_11_CAPABILITY * pCap = (NDIS_802_11_CAPABILITY *)pucBuf;
u8* pucAuthEncryptionSupported = (u8*) pCap->AuthenticationEncryptionSupported;
pCap->Length = sizeof(NDIS_802_11_CAPABILITY);
if(ulNumOfPairSupported > 1 )
pCap->Length += (ulNumOfPairSupported-1) * sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION);
pCap->Version = 2;
pCap->NoOfPMKIDs = NUM_PMKID_CACHE;
pCap->NoOfAuthEncryptPairsSupported = ulNumOfPairSupported;
if( sizeof (szAuthEnc) <= 240 ) // 240 = 256 - 4*4 // SecurityInfo.szCapability: only 256 bytes in size.
{
_rtw_memcpy( pucAuthEncryptionSupported, (u8*)szAuthEnc, sizeof (szAuthEnc) );
*pulOutLen = pCap->Length;
return _TRUE;
}
else
{
*pulOutLen = 0;
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("_query_802_11_capability(): szAuthEnc size is too large.\n"));
return _FALSE;
}
}
u8 query_802_11_association_information( _adapter *padapter,PNDIS_802_11_ASSOCIATION_INFORMATION pAssocInfo)
{
struct wlan_network *tgt_network;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct security_priv *psecuritypriv=&(padapter->securitypriv);
WLAN_BSSID_EX *psecnetwork=(WLAN_BSSID_EX*)&(psecuritypriv->sec_bss);
u8 * pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
unsigned char i,*auth_ie,*supp_ie;
//NdisZeroMemory(pAssocInfo, sizeof(NDIS_802_11_ASSOCIATION_INFORMATION));
_rtw_memset(pAssocInfo, 0, sizeof(NDIS_802_11_ASSOCIATION_INFORMATION));
//pAssocInfo->Length = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
//------------------------------------------------------
// Association Request related information
//------------------------------------------------------
// Req_1. AvailableRequestFixedIEs
if(psecnetwork!=NULL){
pAssocInfo->AvailableRequestFixedIEs |= NDIS_802_11_AI_REQFI_CAPABILITIES|NDIS_802_11_AI_REQFI_CURRENTAPADDRESS;
pAssocInfo->RequestFixedIEs.Capabilities = (unsigned short)* & psecnetwork->IEs[10];
_rtw_memcpy(pAssocInfo->RequestFixedIEs.CurrentAPAddress,
& psecnetwork->MacAddress, 6);
pAssocInfo->OffsetRequestIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
if(check_fwstate( pmlmepriv, _FW_UNDER_LINKING|_FW_LINKED)==_TRUE)
{
if(psecuritypriv->ndisauthtype>=Ndis802_11AuthModeWPA2)
pDest[0] =48; //RSN Information Element
else
pDest[0] =221; //WPA(SSN) Information Element
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n Adapter->ndisauthtype==Ndis802_11AuthModeWPA)?0xdd:0x30 [%d]",pDest[0]));
supp_ie=&psecuritypriv->supplicant_ie[0];
for(i=0;i<supp_ie[0];i++)
{
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("IEs [%d] = 0x%x \n\n", i,supp_ie[i]));
}
i=13; //0~11 is fixed information element
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("i= %d tgt_network->network.IELength=%d\n\n", i,(int)psecnetwork->IELength));
while((i<supp_ie[0]) && (i<256)){
if((unsigned char)supp_ie[i]==pDest[0]){
_rtw_memcpy((u8 *)(pDest),
&supp_ie[i],
supp_ie[1+i]+2);
break;
}
i=i+supp_ie[i+1]+2;
if(supp_ie[1+i]==0)
i=i+1;
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("iteration i=%d IEs [%d] = 0x%x \n\n", i,i,supp_ie[i+1]));
}
pAssocInfo->RequestIELength += (2 + supp_ie[1+i]);// (2 + psecnetwork->IEs[1+i]+4);
}
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n psecnetwork != NULL,fwstate==_FW_UNDER_LINKING \n"));
}
//------------------------------------------------------
// Association Response related information
//------------------------------------------------------
if(check_fwstate( pmlmepriv, _FW_LINKED)==_TRUE)
{
tgt_network =&(pmlmepriv->cur_network);
if(tgt_network!=NULL){
pAssocInfo->AvailableResponseFixedIEs =
NDIS_802_11_AI_RESFI_CAPABILITIES
|NDIS_802_11_AI_RESFI_ASSOCIATIONID
;
pAssocInfo->ResponseFixedIEs.Capabilities =(unsigned short)* & tgt_network->network.IEs[10];
pAssocInfo->ResponseFixedIEs.StatusCode = 0;
pAssocInfo->ResponseFixedIEs.AssociationId =(unsigned short) tgt_network->aid;
pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)+pAssocInfo->RequestIELength;
auth_ie=&psecuritypriv->authenticator_ie[0];
for(i=0;i<auth_ie[0];i++)
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("IEs [%d] = 0x%x \n\n", i,auth_ie[i]));
i=auth_ie[0]-12;
if(i>0){
_rtw_memcpy((u8 *)&pDest[0],&auth_ie[1],i);
pAssocInfo->ResponseIELength =i;
}
pAssocInfo->OffsetResponseIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION) + pAssocInfo->RequestIELength;
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n tgt_network != NULL,fwstate==_FW_LINKED \n"));
}
}
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n exit query_802_11_association_information \n"));
_func_exit_;
return _TRUE;
}
#endif

1023
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_ioctl_rtl.c
View File

File diff suppressed because it is too large Load Diff

1483
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_ioctl_set.c
View File

File diff suppressed because it is too large Load Diff

390
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_iol.c
View File

@ -1,390 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include <drv_types.h>
#ifdef CONFIG_IOL
struct xmit_frame *rtw_IOL_accquire_xmit_frame(ADAPTER *adapter)
{
struct xmit_frame *xmit_frame;
struct xmit_buf *xmitbuf;
struct pkt_attrib *pattrib;
struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
#if 1
if ((xmit_frame = rtw_alloc_xmitframe(pxmitpriv)) == NULL)
{
DBG_871X("%s rtw_alloc_xmitframe return null\n", __FUNCTION__);
goto exit;
}
if ((xmitbuf = rtw_alloc_xmitbuf(pxmitpriv)) == NULL)
{
DBG_871X("%s rtw_alloc_xmitbuf return null\n", __FUNCTION__);
rtw_free_xmitframe(pxmitpriv, xmit_frame);
xmit_frame=NULL;
goto exit;
}
xmit_frame->frame_tag = MGNT_FRAMETAG;
xmit_frame->pxmitbuf = xmitbuf;
xmit_frame->buf_addr = xmitbuf->pbuf;
xmitbuf->priv_data = xmit_frame;
pattrib = &xmit_frame->attrib;
update_mgntframe_attrib(adapter, pattrib);
pattrib->qsel = QSLT_BEACON;//Beacon
pattrib->subtype = WIFI_BEACON;
pattrib->pktlen = pattrib->last_txcmdsz = 0;
#else
if ((xmit_frame = alloc_mgtxmitframe(pxmitpriv)) == NULL)
{
DBG_871X("%s alloc_mgtxmitframe return null\n", __FUNCTION__);
}
else {
pattrib = &xmit_frame->attrib;
update_mgntframe_attrib(adapter, pattrib);
pattrib->qsel = QSLT_BEACON;
pattrib->pktlen = pattrib->last_txcmdsz = 0;
}
#endif
exit:
return xmit_frame;
}
int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len)
{
struct pkt_attrib *pattrib = &xmit_frame->attrib;
u16 buf_offset;
u32 ori_len;
buf_offset = TXDESC_OFFSET;
ori_len = buf_offset+pattrib->pktlen;
//check if the io_buf can accommodate new cmds
if(ori_len + cmd_len + 8 > MAX_XMITBUF_SZ) {
DBG_871X("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate new cmds\n", __FUNCTION__
, ori_len + cmd_len + 8, MAX_XMITBUF_SZ);
return _FAIL;
}
_rtw_memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, IOL_cmds, cmd_len);
pattrib->pktlen += cmd_len;
pattrib->last_txcmdsz += cmd_len;
//DBG_871X("%s ori:%u + cmd_len:%u = %u\n", __FUNCTION__, ori_len, cmd_len, buf_offset+pattrib->pktlen);
return _SUCCESS;
}
bool rtw_IOL_applied(ADAPTER *adapter)
{
if(1 == adapter->registrypriv.fw_iol)
return _TRUE;
#ifdef CONFIG_USB_HCI
if((2 == adapter->registrypriv.fw_iol) && (IS_FULL_SPEED_USB(adapter)))
return _TRUE;
#endif
return _FALSE;
}
int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
{
return rtw_hal_iol_cmd(adapter, xmit_frame, max_wating_ms,bndy_cnt);
}
#ifdef CONFIG_IOL_NEW_GENERATION
int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)
{
return _SUCCESS;
}
int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask)
{
struct ioreg_cfg cmd = {8,IOREG_CMD_WB_REG,0x0, 0x0,0x0};
//RTW_PUT_LE16((u8*)&cmd.address, addr);
//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);
cmd.address = cpu_to_le16(addr);
cmd.data = cpu_to_le32(value);
if(mask!=0xFF)
{
cmd.length = 12;
//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);
cmd.mask = cpu_to_le32(mask);
}
//DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length);
}
int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask)
{
struct ioreg_cfg cmd = {8,IOREG_CMD_WW_REG,0x0, 0x0,0x0};
//RTW_PUT_LE16((u8*)&cmd.address, addr);
//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);
cmd.address = cpu_to_le16(addr);
cmd.data = cpu_to_le32(value);
if(mask!=0xFFFF)
{
cmd.length = 12;
//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);
cmd.mask = cpu_to_le32(mask);
}
//DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length);
}
int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask)
{
struct ioreg_cfg cmd = {8,IOREG_CMD_WD_REG,0x0, 0x0,0x0};
//RTW_PUT_LE16((u8*)&cmd.address, addr);
//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);
cmd.address = cpu_to_le16(addr);
cmd.data = cpu_to_le32(value);
if(mask!=0xFFFFFFFF)
{
cmd.length = 12;
//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);
cmd.mask = cpu_to_le32(mask);
}
//DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__, addr,value,mask);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length);
}
int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask)
{
struct ioreg_cfg cmd = {8,IOREG_CMD_W_RF,0x0, 0x0,0x0};
//RTW_PUT_LE16((u8*)&cmd.address, addr);
//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);
cmd.address = (rf_path<<8) |((addr) &0xFF);
cmd.data = cpu_to_le32(value);
if(mask!=0x000FFFFF)
{
cmd.length = 12;
//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);
cmd.mask = cpu_to_le32(mask);
}
//DBG_871X("%s rf_path:0x%02x addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__,rf_path, addr,value,mask);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length);
}
int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
{
struct ioreg_cfg cmd = {4,IOREG_CMD_DELAY_US,0x0, 0x0,0x0};
//RTW_PUT_LE16((u8*)&cmd.address, us);
cmd.address = cpu_to_le16(us);
//DBG_871X("%s %u\n", __FUNCTION__, us);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4);
}
int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
{
struct ioreg_cfg cmd = {4,IOREG_CMD_DELAY_US,0x0, 0x0,0x0};
//RTW_PUT_LE16((u8*)&cmd.address, ms);
cmd.address = cpu_to_le16(ms);
//DBG_871X("%s %u\n", __FUNCTION__, ms);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4);
}
int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
{
struct ioreg_cfg cmd = {4,IOREG_CMD_END,0xFFFF, 0xFF,0x0};
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4);
}
u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame)
{
u8 is_cmd_bndy = _FALSE;
if(((pxmit_frame->attrib.pktlen+32)%256) + 8 >= 256){
rtw_IOL_append_END_cmd(pxmit_frame);
pxmit_frame->attrib.pktlen = ((((pxmit_frame->attrib.pktlen+32)/256)+1)*256 );
//printk("==> %s, pktlen(%d)\n",__FUNCTION__,pxmit_frame->attrib.pktlen);
pxmit_frame->attrib.last_txcmdsz = pxmit_frame->attrib.pktlen;
is_cmd_bndy = _TRUE;
}
return is_cmd_bndy;
}
void rtw_IOL_cmd_buf_dump(ADAPTER *Adapter,int buf_len,u8 *pbuf)
{
int i;
int j=1;
printk("###### %s ######\n",__FUNCTION__);
for(i=0;i< buf_len;i++){
printk("%02x-",*(pbuf+i));
if(j%32 ==0) printk("\n");j++;
}
printk("\n");
printk("============= ioreg_cmd len = %d =============== \n",buf_len);
}
#else //CONFIG_IOL_NEW_GENERATION
int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)
{
IOL_CMD cmd = {0x0, IOL_CMD_LLT, 0x0, 0x0};
RTW_PUT_BE32((u8*)&cmd.value, (u32)page_boundary);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
}
int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value)
{
IOL_CMD cmd = {0x0, IOL_CMD_WB_REG, 0x0, 0x0};
RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
}
int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value)
{
IOL_CMD cmd = {0x0, IOL_CMD_WW_REG, 0x0, 0x0};
RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
}
int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value)
{
IOL_CMD cmd = {0x0, IOL_CMD_WD_REG, 0x0, 0x0};
u8* pos = (u8 *)&cmd;
RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
}
#ifdef DBG_IO
int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 1))
DBG_871X("DBG_IO %s:%d IOL_WB(0x%04x, 0x%02x)\n", caller, line, addr, value);
return _rtw_IOL_append_WB_cmd(xmit_frame, addr, value);
}
int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 2))
DBG_871X("DBG_IO %s:%d IOL_WW(0x%04x, 0x%04x)\n", caller, line, addr, value);
return _rtw_IOL_append_WW_cmd(xmit_frame, addr, value);
}
int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 4))
DBG_871X("DBG_IO %s:%d IOL_WD(0x%04x, 0x%08x)\n", caller, line, addr, value);
return _rtw_IOL_append_WD_cmd(xmit_frame, addr, value);
}
#endif
int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
{
IOL_CMD cmd = {0x0, IOL_CMD_DELAY_US, 0x0, 0x0};
RTW_PUT_BE32((u8*)&cmd.value, (u32)us);
//DBG_871X("%s %u\n", __FUNCTION__, us);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
}
int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
{
IOL_CMD cmd = {0x0, IOL_CMD_DELAY_MS, 0x0, 0x0};
RTW_PUT_BE32((u8*)&cmd.value, (u32)ms);
//DBG_871X("%s %u\n", __FUNCTION__, ms);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
}
int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
{
IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};
return rtw_IOL_append_cmds(xmit_frame, (u8*)&end_cmd, 8);
}
int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms)
{
struct xmit_frame *xmit_frame;
if((xmit_frame=rtw_IOL_accquire_xmit_frame(adapter)) == NULL)
return _FAIL;
if(rtw_IOL_append_cmds(xmit_frame, IOL_cmds, cmd_num<<3) == _FAIL)
return _FAIL;
return rtw_IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms,0);
}
int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms)
{
IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};
return rtw_IOL_exec_cmd_array_sync(adapter, (u8*)&end_cmd, 1, max_wating_ms);
}
#endif //CONFIG_IOL_NEW_GENERATION
#endif //CONFIG_IOL

103
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_mem.c
View File

@ -1,103 +0,0 @@
#include <drv_types.h>
#include <rtw_mem.h>
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Realtek Wireless Lan Driver");
MODULE_AUTHOR("Realtek Semiconductor Corp.");
MODULE_VERSION("DRIVERVERSION");
struct sk_buff_head rtk_skb_mem_q;
struct u8* rtk_buf_mem[NR_RECVBUFF];
struct u8 * rtw_get_buf_premem(int index)
{
printk("%s, rtk_buf_mem index : %d\n", __func__, index);
return rtk_buf_mem[index];
}
struct sk_buff *rtw_alloc_skb_premem(void)
{
struct sk_buff *skb = NULL;
skb = skb_dequeue(&rtk_skb_mem_q);
printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
return skb;
}
EXPORT_SYMBOL(rtw_alloc_skb_premem);
int rtw_free_skb_premem(struct sk_buff *pskb)
{
if(!pskb)
return -1;
if(skb_queue_len(&rtk_skb_mem_q) >= NR_PREALLOC_RECV_SKB)
return -1;
skb_queue_tail(&rtk_skb_mem_q, pskb);
printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
return 0;
}
EXPORT_SYMBOL(rtw_free_skb_premem);
static int __init rtw_mem_init(void)
{
int i;
SIZE_PTR tmpaddr=0;
SIZE_PTR alignment=0;
struct sk_buff *pskb=NULL;
printk("%s\n", __func__);
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
for(i=0; i<NR_RECVBUFF; i++)
{
rtk_buf_mem[i] = usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);
}
#endif //CONFIG_USE_USB_BUFFER_ALLOC_RX
skb_queue_head_init(&rtk_skb_mem_q);
for(i=0; i<NR_PREALLOC_RECV_SKB; i++)
{
pskb = __dev_alloc_skb(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
if(pskb)
{
tmpaddr = (SIZE_PTR)pskb->data;
alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment));
skb_queue_tail(&rtk_skb_mem_q, pskb);
}
else
{
printk("%s, alloc skb memory fail!\n", __func__);
}
pskb=NULL;
}
printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
return 0;
}
static void __exit rtw_mem_exit(void)
{
if (skb_queue_len(&rtk_skb_mem_q)) {
printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
}
skb_queue_purge(&rtk_skb_mem_q);
printk("%s\n", __func__);
}
module_init(rtw_mem_init);
module_exit(rtw_mem_exit);

4536
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_mlme.c
View File

File diff suppressed because it is too large Load Diff

14696
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_mlme_ext.c
View File

File diff suppressed because it is too large Load Diff

2520
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_mp.c
View File

File diff suppressed because it is too large Load Diff

2948
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_mp_ioctl.c
View File

File diff suppressed because it is too large Load Diff

338
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_odm.c
View File

@ -1,338 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2013 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include <rtw_odm.h>
#include <hal_data.h>
const char *odm_comp_str[] = {
/* BIT0 */"ODM_COMP_DIG",
/* BIT1 */"ODM_COMP_RA_MASK",
/* BIT2 */"ODM_COMP_DYNAMIC_TXPWR",
/* BIT3 */"ODM_COMP_FA_CNT",
/* BIT4 */"ODM_COMP_RSSI_MONITOR",
/* BIT5 */"ODM_COMP_CCK_PD",
/* BIT6 */"ODM_COMP_ANT_DIV",
/* BIT7 */"ODM_COMP_PWR_SAVE",
/* BIT8 */"ODM_COMP_PWR_TRAIN",
/* BIT9 */"ODM_COMP_RATE_ADAPTIVE",
/* BIT10 */"ODM_COMP_PATH_DIV",
/* BIT11 */"ODM_COMP_PSD",
/* BIT12 */"ODM_COMP_DYNAMIC_PRICCA",
/* BIT13 */"ODM_COMP_RXHP",
/* BIT14 */"ODM_COMP_MP",
/* BIT15 */"ODM_COMP_CFO_TRACKING",
/* BIT16 */"ODM_COMP_ACS",
/* BIT17 */"PHYDM_COMP_ADAPTIVITY",
/* BIT18 */NULL,
/* BIT19 */NULL,
/* BIT20 */"ODM_COMP_EDCA_TURBO",
/* BIT21 */"ODM_COMP_EARLY_MODE",
/* BIT22 */NULL,
/* BIT23 */NULL,
/* BIT24 */"ODM_COMP_TX_PWR_TRACK",
/* BIT25 */"ODM_COMP_RX_GAIN_TRACK",
/* BIT26 */"ODM_COMP_CALIBRATION",
/* BIT27 */NULL,
/* BIT28 */NULL,
/* BIT29 */NULL,
/* BIT30 */"ODM_COMP_COMMON",
/* BIT31 */"ODM_COMP_INIT",
};
#define RTW_ODM_COMP_MAX 32
const char *odm_ability_str[] = {
/* BIT0 */"ODM_BB_DIG",
/* BIT1 */"ODM_BB_RA_MASK",
/* BIT2 */"ODM_BB_DYNAMIC_TXPWR",
/* BIT3 */"ODM_BB_FA_CNT",
/* BIT4 */"ODM_BB_RSSI_MONITOR",
/* BIT5 */"ODM_BB_CCK_PD",
/* BIT6 */"ODM_BB_ANT_DIV",
/* BIT7 */"ODM_BB_PWR_SAVE",
/* BIT8 */"ODM_BB_PWR_TRAIN",
/* BIT9 */"ODM_BB_RATE_ADAPTIVE",
/* BIT10 */"ODM_BB_PATH_DIV",
/* BIT11 */"ODM_BB_PSD",
/* BIT12 */"ODM_BB_RXHP",
/* BIT13 */"ODM_BB_ADAPTIVITY",
/* BIT14 */"ODM_BB_CFO_TRACKING",
/* BIT15 */"ODM_BB_NHM_CNT",
/* BIT16 */"ODM_BB_PRIMARY_CCA",
/* BIT17 */NULL,
/* BIT18 */NULL,
/* BIT19 */NULL,
/* BIT20 */"ODM_MAC_EDCA_TURBO",
/* BIT21 */"ODM_MAC_EARLY_MODE",
/* BIT22 */NULL,
/* BIT23 */NULL,
/* BIT24 */"ODM_RF_TX_PWR_TRACK",
/* BIT25 */"ODM_RF_RX_GAIN_TRACK",
/* BIT26 */"ODM_RF_CALIBRATION",
};
#define RTW_ODM_ABILITY_MAX 27
const char *odm_dbg_level_str[] = {
NULL,
"ODM_DBG_OFF",
"ODM_DBG_SERIOUS",
"ODM_DBG_WARNING",
"ODM_DBG_LOUD",
"ODM_DBG_TRACE",
};
#define RTW_ODM_DBG_LEVEL_NUM 6
void rtw_odm_dbg_comp_msg(void *sel, _adapter *adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
int cnt = 0;
u64 dbg_comp;
int i;
rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &dbg_comp);
DBG_871X_SEL_NL(sel, "odm.DebugComponents = 0x%016llx \n", dbg_comp);
for (i=0;i<RTW_ODM_COMP_MAX;i++) {
if (odm_comp_str[i])
DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
(BIT0 << i) & dbg_comp ? '+' : ' ', i, odm_comp_str[i]);
}
}
inline void rtw_odm_dbg_comp_set(_adapter *adapter, u64 comps)
{
rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &comps);
}
void rtw_odm_dbg_level_msg(void *sel, _adapter *adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
int cnt = 0;
u32 dbg_level;
int i;
rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &dbg_level);
DBG_871X_SEL_NL(sel, "odm.DebugLevel = %u\n", dbg_level);
for (i=0;i<RTW_ODM_DBG_LEVEL_NUM;i++) {
if (odm_dbg_level_str[i])
DBG_871X_SEL_NL(sel, "%u %s\n", i, odm_dbg_level_str[i]);
}
}
inline void rtw_odm_dbg_level_set(_adapter *adapter, u32 level)
{
rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &level);
}
void rtw_odm_ability_msg(void *sel, _adapter *adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
int cnt = 0;
u32 ability = 0;
int i;
rtw_hal_get_hwreg(adapter, HW_VAR_DM_FLAG, (u8*)&ability);
DBG_871X_SEL_NL(sel, "odm.SupportAbility = 0x%08x\n", ability);
for (i=0;i<RTW_ODM_ABILITY_MAX;i++) {
if (odm_ability_str[i])
DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
(BIT0 << i) & ability ? '+' : ' ', i, odm_ability_str[i]);
}
}
inline void rtw_odm_ability_set(_adapter *adapter, u32 ability)
{
rtw_hal_set_hwreg(adapter, HW_VAR_DM_FLAG, (u8*)&ability);
}
void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
{
DBG_871X_SEL_NL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n");
}
#define RTW_ADAPTIVITY_EN_DISABLE 0
#define RTW_ADAPTIVITY_EN_ENABLE 1
#define RTW_ADAPTIVITY_EN_AUTO 2
void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
{
struct registry_priv *regsty = &adapter->registrypriv;
struct mlme_priv *mlme = &adapter->mlmepriv;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &hal_data->odmpriv;
DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_EN_");
if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE) {
DBG_871X_SEL(sel, "DISABLE\n");
} else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE) {
DBG_871X_SEL(sel, "ENABLE\n");
} else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_AUTO) {
DBG_871X_SEL(sel, "AUTO, chplan:0x%02x, Regulation:%u,%u\n"
, mlme->ChannelPlan, odm->odm_Regulation2_4G, odm->odm_Regulation5G);
} else {
DBG_871X_SEL(sel, "INVALID\n");
}
}
#define RTW_ADAPTIVITY_MODE_NORMAL 0
#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)
{
struct registry_priv *regsty = &adapter->registrypriv;
DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_MODE_");
if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL) {
DBG_871X_SEL(sel, "NORMAL\n");
} else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE) {
DBG_871X_SEL(sel, "CARRIER_SENSE\n");
} else {
DBG_871X_SEL(sel, "INVALID\n");
}
}
#define RTW_NHM_EN_DISABLE 0
#define RTW_NHM_EN_ENABLE 1
void rtw_odm_nhm_en_msg(void *sel, _adapter *adapter)
{
struct registry_priv *regsty = &adapter->registrypriv;
DBG_871X_SEL_NL(sel, "RTW_NHM_EN_");
if (regsty->nhm_en == RTW_NHM_EN_DISABLE) {
DBG_871X_SEL(sel, "DISABLE\n");
} else if (regsty->nhm_en == RTW_NHM_EN_ENABLE) {
DBG_871X_SEL(sel, "ENABLE\n");
} else {
DBG_871X_SEL(sel, "INVALID\n");
}
}
bool rtw_odm_adaptivity_needed(_adapter *adapter)
{
struct registry_priv *regsty = &adapter->registrypriv;
struct mlme_priv *mlme = &adapter->mlmepriv;
bool ret = _FALSE;
if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE
|| regsty->adaptivity_en == RTW_ADAPTIVITY_EN_AUTO)
ret = _TRUE;
if (ret == _TRUE) {
rtw_odm_adaptivity_ver_msg(RTW_DBGDUMP, adapter);
rtw_odm_adaptivity_en_msg(RTW_DBGDUMP, adapter);
rtw_odm_adaptivity_mode_msg(RTW_DBGDUMP, adapter);
rtw_odm_nhm_en_msg(RTW_DBGDUMP, adapter);
}
return ret;
}
void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
rtw_odm_adaptivity_ver_msg(sel, adapter);
rtw_odm_adaptivity_en_msg(sel, adapter);
rtw_odm_adaptivity_mode_msg(sel, adapter);
rtw_odm_nhm_en_msg(sel, adapter);
DBG_871X_SEL_NL(sel, "%10s %16s %8s %10s %11s %14s\n"
, "TH_L2H_ini", "TH_EDCCA_HL_diff", "IGI_Base", "ForceEDCCA", "AdapEn_RSSI", "IGI_LowerBound");
DBG_871X_SEL_NL(sel, "0x%-8x %-16d 0x%-6x %-10d %-11u %-14u\n"
, (u8)odm->TH_L2H_ini
, odm->TH_EDCCA_HL_diff
, odm->IGI_Base
, odm->ForceEDCCA
, odm->AdapEn_RSSI
, odm->IGI_LowerBound
);
DBG_871X_SEL_NL(sel, "%8s %9s\n", "EDCCA_ES","Adap_Flag");
DBG_871X_SEL_NL(sel, "%-8x %-9x \n"
, odm->EDCCA_enable_state
, odm->adaptivity_flag
);
}
void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
odm->TH_L2H_ini = TH_L2H_ini;
odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;
odm->IGI_Base = IGI_Base;
odm->ForceEDCCA = ForceEDCCA;
odm->AdapEn_RSSI = AdapEn_RSSI;
odm->IGI_LowerBound = IGI_LowerBound;
}
void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &(hal_data->odmpriv);
DBG_871X_SEL_NL(sel,"RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
}
void rtw_odm_acquirespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
_irqL irqL;
switch(type)
{
case RT_IQK_SPINLOCK:
_enter_critical_bh(&pdmpriv->IQKSpinLock, &irqL);
default:
break;
}
}
void rtw_odm_releasespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
_irqL irqL;
switch(type)
{
case RT_IQK_SPINLOCK:
_exit_critical_bh(&pdmpriv->IQKSpinLock, &irqL);
default:
break;
}
}

5352
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_p2p.c
View File

File diff suppressed because it is too large Load Diff

2814
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_pwrctrl.c
View File

File diff suppressed because it is too large Load Diff

4300
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_recv.c
View File

File diff suppressed because it is too large Load Diff

91
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_rf.c
View File

@ -1,91 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTW_RF_C_
#include <drv_types.h>
struct ch_freq {
u32 channel;
u32 frequency;
};
struct ch_freq ch_freq_map[] = {
{1, 2412},{2, 2417},{3, 2422},{4, 2427},{5, 2432},
{6, 2437},{7, 2442},{8, 2447},{9, 2452},{10, 2457},
{11, 2462},{12, 2467},{13, 2472},{14, 2484},
/* UNII */
{36, 5180},{40, 5200},{44, 5220},{48, 5240},{52, 5260},
{56, 5280},{60, 5300},{64, 5320},{149, 5745},{153, 5765},
{157, 5785},{161, 5805},{165, 5825},{167, 5835},{169, 5845},
{171, 5855},{173, 5865},
/* HiperLAN2 */
{100, 5500},{104, 5520},{108, 5540},{112, 5560},{116, 5580},
{120, 5600},{124, 5620},{128, 5640},{132, 5660},{136, 5680},
{140, 5700},
/* Japan MMAC */
{34, 5170},{38, 5190},{42, 5210},{46, 5230},
/* Japan */
{184, 4920},{188, 4940},{192, 4960},{196, 4980},
{208, 5040},/* Japan, means J08 */
{212, 5060},/* Japan, means J12 */
{216, 5080},/* Japan, means J16 */
};
int ch_freq_map_num = (sizeof(ch_freq_map) / sizeof(struct ch_freq));
u32 rtw_ch2freq(u32 channel)
{
u8 i;
u32 freq = 0;
for (i = 0; i < ch_freq_map_num; i++)
{
if (channel == ch_freq_map[i].channel)
{
freq = ch_freq_map[i].frequency;
break;
}
}
if (i == ch_freq_map_num)
freq = 2412;
return freq;
}
u32 rtw_freq2ch(u32 freq)
{
u8 i;
u32 ch = 0;
for (i = 0; i < ch_freq_map_num; i++)
{
if (freq == ch_freq_map[i].frequency)
{
ch = ch_freq_map[i].channel;
break;
}
}
if (i == ch_freq_map_num)
ch = 1;
return ch;
}

3230
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_security.c
View File

File diff suppressed because it is too large Load Diff

365
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_sreset.c
View File

@ -1,365 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include <drv_types.h>
#include <hal_data.h>
#include <rtw_sreset.h>
void sreset_init_value(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
_rtw_mutex_init(&psrtpriv->silentreset_mutex);
psrtpriv->silent_reset_inprogress = _FALSE;
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
psrtpriv->last_tx_time =0;
psrtpriv->last_tx_complete_time =0;
#endif
}
void sreset_reset_value(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
psrtpriv->last_tx_time =0;
psrtpriv->last_tx_complete_time =0;
#endif
}
u8 sreset_get_wifi_status(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
u8 status = WIFI_STATUS_SUCCESS;
u32 val32 = 0;
_irqL irqL;
if(psrtpriv->silent_reset_inprogress == _TRUE)
{
return status;
}
val32 =rtw_read32(padapter,REG_TXDMA_STATUS);
if(val32==0xeaeaeaea){
psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST;
}
else if(val32!=0){
DBG_8192C("txdmastatu(%x)\n",val32);
psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR;
}
if(WIFI_STATUS_SUCCESS !=psrtpriv->Wifi_Error_Status)
{
DBG_8192C("==>%s error_status(0x%x) \n",__FUNCTION__,psrtpriv->Wifi_Error_Status);
status = (psrtpriv->Wifi_Error_Status &( ~(USB_READ_PORT_FAIL|USB_WRITE_PORT_FAIL)));
}
DBG_8192C("==> %s wifi_status(0x%x)\n",__FUNCTION__,status);
//status restore
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
return status;
#else
return WIFI_STATUS_SUCCESS;
#endif
}
void sreset_set_wifi_error_status(_adapter *padapter, u32 status)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
pHalData->srestpriv.Wifi_Error_Status = status;
#endif
}
void sreset_set_trigger_point(_adapter *padapter, s32 tgp)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
pHalData->srestpriv.dbg_trigger_point = tgp;
#endif
}
bool sreset_inprogress(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_RESET)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
return pHalData->srestpriv.silent_reset_inprogress;
#else
return _FALSE;
#endif
}
void sreset_restore_security_station(_adapter *padapter)
{
u8 EntryId = 0;
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct sta_priv * pstapriv = &padapter->stapriv;
struct sta_info *psta;
struct security_priv* psecuritypriv=&(padapter->securitypriv);
struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
{
u8 val8;
if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) {
val8 = 0xcc;
#ifdef CONFIG_WAPI_SUPPORT
} else if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) {
//Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey.
val8 = 0x4c;
#endif
} else {
val8 = 0xcf;
}
rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
}
#if 0
if ( ( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP40_ ) ||
( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP104_ ))
{
for(EntryId=0; EntryId<4; EntryId++)
{
if(EntryId == psecuritypriv->dot11PrivacyKeyIndex)
rtw_set_key(padapter,&padapter->securitypriv, EntryId, 1,_FALSE);
else
rtw_set_key(padapter,&padapter->securitypriv, EntryId, 0,_FALSE);
}
}
else
#endif
if((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
(padapter->securitypriv.dot11PrivacyAlgrthm == _AES_))
{
psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv));
if (psta == NULL) {
//DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n"));
}
else
{
//pairwise key
rtw_setstakey_cmd(padapter, psta, _TRUE,_FALSE);
//group key
rtw_set_key(padapter,&padapter->securitypriv,padapter->securitypriv.dot118021XGrpKeyid, 0,_FALSE);
}
}
}
void sreset_restore_network_station(_adapter *padapter)
{
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
#if 0
{
//=======================================================
// reset related register of Beacon control
//set MSR to nolink
Set_MSR(padapter, _HW_STATE_NOLINK_);
// reject all data frame
rtw_write16(padapter, REG_RXFLTMAP2,0x00);
//reset TSF
rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
// disable update TSF
SetBcnCtrlReg(padapter, BIT(4), 0);
//=======================================================
}
#endif
rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure,_FALSE);
{
u8 threshold;
#ifdef CONFIG_USB_HCI
// TH=1 => means that invalidate usb rx aggregation
// TH=0 => means that validate usb rx aggregation, use init value.
if(mlmepriv->htpriv.ht_option) {
if(padapter->registrypriv.wifi_spec==1)
threshold = 1;
else
threshold = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
} else {
threshold = 1;
rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
}
#endif
}
rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, NULL);
set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
//disable dynamic functions, such as high power, DIG
//Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
{
u8 join_type = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
}
Set_MSR(padapter, (pmlmeinfo->state & 0x3));
mlmeext_joinbss_event_callback(padapter, 1);
//restore Sequence No.
rtw_write8(padapter,0x4dc,padapter->xmitpriv.nqos_ssn);
sreset_restore_security_station(padapter);
}
void sreset_restore_network_status(_adapter *padapter)
{
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
sreset_restore_network_station(padapter);
} else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
rtw_ap_restore_network(padapter);
} else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
} else {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
}
}
void sreset_stop_adapter(_adapter *padapter)
{
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
if (padapter == NULL)
return;
DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
rtw_netif_stop_queue(padapter->pnetdev);
rtw_cancel_all_timer(padapter);
/* TODO: OS and HCI independent */
#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
tasklet_kill(&pxmitpriv->xmit_tasklet);
#endif
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
rtw_scan_abort(padapter);
if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING))
{
rtw_set_to_roam(padapter, 0);
_rtw_join_timeout_handler(padapter);
}
}
void sreset_start_adapter(_adapter *padapter)
{
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
if (padapter == NULL)
return;
DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
if (check_fwstate(pmlmepriv, _FW_LINKED)) {
sreset_restore_network_status(padapter);
}
/* TODO: OS and HCI independent */
#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
#endif
if (is_primary_adapter(padapter))
_set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000);
rtw_netif_wake_queue(padapter->pnetdev);
}
void sreset_reset(_adapter *padapter)
{
#ifdef DBG_CONFIG_ERROR_RESET
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
_irqL irqL;
u32 start = rtw_get_current_time();
struct dvobj_priv *psdpriv = padapter->dvobj;
struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
DBG_871X("%s\n", __FUNCTION__);
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
#ifdef CONFIG_LPS
rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "SRESET");
#endif//#ifdef CONFIG_LPS
_enter_pwrlock(&pwrpriv->lock);
psrtpriv->silent_reset_inprogress = _TRUE;
pwrpriv->change_rfpwrstate = rf_off;
sreset_stop_adapter(padapter);
#ifdef CONFIG_CONCURRENT_MODE
sreset_stop_adapter(padapter->pbuddy_adapter);
#endif
#ifdef CONFIG_IPS
_ips_enter(padapter);
_ips_leave(padapter);
#endif
sreset_start_adapter(padapter);
#ifdef CONFIG_CONCURRENT_MODE
sreset_start_adapter(padapter->pbuddy_adapter);
#endif
psrtpriv->silent_reset_inprogress = _FALSE;
_exit_pwrlock(&pwrpriv->lock);
DBG_871X("%s done in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
pdbgpriv->dbg_sreset_cnt++;
#endif
}

872
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_sta_mgt.c
View File

@ -1,872 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTW_STA_MGT_C_
#include <drv_types.h>
#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
#error "Shall be Linux or Windows, but not both!\n"
#endif
void _rtw_init_stainfo(struct sta_info *psta);
void _rtw_init_stainfo(struct sta_info *psta)
{
_func_enter_;
_rtw_memset((u8 *)psta, 0, sizeof (struct sta_info));
_rtw_spinlock_init(&psta->lock);
_rtw_init_listhead(&psta->list);
_rtw_init_listhead(&psta->hash_list);
//_rtw_init_listhead(&psta->asoc_list);
//_rtw_init_listhead(&psta->sleep_list);
//_rtw_init_listhead(&psta->wakeup_list);
_rtw_init_queue(&psta->sleep_q);
psta->sleepq_len = 0;
_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
#ifdef CONFIG_AP_MODE
_rtw_init_listhead(&psta->asoc_list);
_rtw_init_listhead(&psta->auth_list);
psta->expire_to = 0;
psta->flags = 0;
psta->capability = 0;
psta->bpairwise_key_installed = _FALSE;
#ifdef CONFIG_NATIVEAP_MLME
psta->nonerp_set = 0;
psta->no_short_slot_time_set = 0;
psta->no_short_preamble_set = 0;
psta->no_ht_gf_set = 0;
psta->no_ht_set = 0;
psta->ht_20mhz_set = 0;
#endif
#ifdef CONFIG_TX_MCAST2UNI
psta->under_exist_checking = 0;
#endif // CONFIG_TX_MCAST2UNI
psta->keep_alive_trycnt = 0;
#endif // CONFIG_AP_MODE
_func_exit_;
}
u32 _rtw_init_sta_priv(struct sta_priv *pstapriv)
{
struct sta_info *psta;
s32 i;
_func_enter_;
pstapriv->pallocated_stainfo_buf = rtw_zvmalloc (sizeof(struct sta_info) * NUM_STA+ 4);
if(!pstapriv->pallocated_stainfo_buf)
return _FAIL;
pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 -
((SIZE_PTR)(pstapriv->pallocated_stainfo_buf ) & 3);
_rtw_init_queue(&pstapriv->free_sta_queue);
_rtw_spinlock_init(&pstapriv->sta_hash_lock);
//_rtw_init_queue(&pstapriv->asoc_q);
pstapriv->asoc_sta_count = 0;
_rtw_init_queue(&pstapriv->sleep_q);
_rtw_init_queue(&pstapriv->wakeup_q);
psta = (struct sta_info *)(pstapriv->pstainfo_buf);
for(i = 0; i < NUM_STA; i++)
{
_rtw_init_stainfo(psta);
_rtw_init_listhead(&(pstapriv->sta_hash[i]));
rtw_list_insert_tail(&psta->list, get_list_head(&pstapriv->free_sta_queue));
psta++;
}
#ifdef CONFIG_AP_MODE
pstapriv->sta_dz_bitmap = 0;
pstapriv->tim_bitmap = 0;
_rtw_init_listhead(&pstapriv->asoc_list);
_rtw_init_listhead(&pstapriv->auth_list);
_rtw_spinlock_init(&pstapriv->asoc_list_lock);
_rtw_spinlock_init(&pstapriv->auth_list_lock);
pstapriv->asoc_list_cnt = 0;
pstapriv->auth_list_cnt = 0;
pstapriv->auth_to = 3; // 3*2 = 6 sec
pstapriv->assoc_to = 3;
//pstapriv->expire_to = 900;// 900*2 = 1800 sec = 30 min, expire after no any traffic.
//pstapriv->expire_to = 30;// 30*2 = 60 sec = 1 min, expire after no any traffic.
#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
pstapriv->expire_to = 3; // 3*2 = 6 sec
#else
pstapriv->expire_to = 60;// 60*2 = 120 sec = 2 min, expire after no any traffic.
#endif
#ifdef CONFIG_ATMEL_RC_PATCH
_rtw_memset( pstapriv->atmel_rc_pattern, 0, ETH_ALEN);
#endif
pstapriv->max_num_sta = NUM_STA;
#endif
_func_exit_;
return _SUCCESS;
}
inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta)
{
int offset = (((u8 *)sta) - stapriv->pstainfo_buf)/sizeof(struct sta_info);
if (!stainfo_offset_valid(offset))
DBG_871X("%s invalid offset(%d), out of range!!!", __func__, offset);
return offset;
}
inline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset)
{
if (!stainfo_offset_valid(offset))
DBG_871X("%s invalid offset(%d), out of range!!!", __func__, offset);
return (struct sta_info *)(stapriv->pstainfo_buf + offset * sizeof(struct sta_info));
}
void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv);
void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv)
{
_func_enter_;
_rtw_spinlock_free(&psta_xmitpriv->lock);
_rtw_spinlock_free(&(psta_xmitpriv->be_q.sta_pending.lock));
_rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock));
_rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock));
_rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock));
_func_exit_;
}
static void _rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv)
{
_func_enter_;
_rtw_spinlock_free(&psta_recvpriv->lock);
_rtw_spinlock_free(&(psta_recvpriv->defrag_q.lock));
_func_exit_;
}
void rtw_mfree_stainfo(struct sta_info *psta);
void rtw_mfree_stainfo(struct sta_info *psta)
{
_func_enter_;
if(&psta->lock != NULL)
_rtw_spinlock_free(&psta->lock);
_rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv);
_rtw_free_sta_recv_priv_lock(&psta->sta_recvpriv);
_func_exit_;
}
// this function is used to free the memory of lock || sema for all stainfos
void rtw_mfree_all_stainfo(struct sta_priv *pstapriv );
void rtw_mfree_all_stainfo(struct sta_priv *pstapriv )
{
_irqL irqL;
_list *plist, *phead;
struct sta_info *psta = NULL;
_func_enter_;
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
phead = get_list_head(&pstapriv->free_sta_queue);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
psta = LIST_CONTAINOR(plist, struct sta_info ,list);
plist = get_next(plist);
rtw_mfree_stainfo(psta);
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
_func_exit_;
}
void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv);
void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv)
{
#ifdef CONFIG_AP_MODE
struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
#endif
rtw_mfree_all_stainfo(pstapriv); //be done before free sta_hash_lock
_rtw_spinlock_free(&pstapriv->free_sta_queue.lock);
_rtw_spinlock_free(&pstapriv->sta_hash_lock);
_rtw_spinlock_free(&pstapriv->wakeup_q.lock);
_rtw_spinlock_free(&pstapriv->sleep_q.lock);
#ifdef CONFIG_AP_MODE
_rtw_spinlock_free(&pstapriv->asoc_list_lock);
_rtw_spinlock_free(&pstapriv->auth_list_lock);
_rtw_spinlock_free(&pacl_list->acl_node_q.lock);
#endif
}
u32 _rtw_free_sta_priv(struct sta_priv *pstapriv)
{
_irqL irqL;
_list *phead, *plist;
struct sta_info *psta = NULL;
struct recv_reorder_ctrl *preorder_ctrl;
int index;
_func_enter_;
if(pstapriv){
/* delete all reordering_ctrl_timer */
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
for(index = 0; index < NUM_STA; index++)
{
phead = &(pstapriv->sta_hash[index]);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
int i;
psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list);
plist = get_next(plist);
for(i=0; i < 16 ; i++)
{
preorder_ctrl = &psta->recvreorder_ctrl[i];
_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
}
}
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
/*===============================*/
rtw_mfree_sta_priv_lock(pstapriv);
if(pstapriv->pallocated_stainfo_buf) {
rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info)*NUM_STA+4);
}
}
_func_exit_;
return _SUCCESS;
}
//struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr)
struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
{
_irqL irqL, irqL2;
uint tmp_aid;
s32 index;
_list *phash_list;
struct sta_info *psta;
_queue *pfree_sta_queue;
struct recv_reorder_ctrl *preorder_ctrl;
int i = 0;
u16 wRxSeqInitialValue = 0xffff;
_func_enter_;
pfree_sta_queue = &pstapriv->free_sta_queue;
//_enter_critical_bh(&(pfree_sta_queue->lock), &irqL);
_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
if (_rtw_queue_empty(pfree_sta_queue) == _TRUE)
{
//_exit_critical_bh(&(pfree_sta_queue->lock), &irqL);
_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
psta = NULL;
}
else
{
psta = LIST_CONTAINOR(get_next(&pfree_sta_queue->queue), struct sta_info, list);
rtw_list_delete(&(psta->list));
//_exit_critical_bh(&(pfree_sta_queue->lock), &irqL);
tmp_aid = psta->aid;
_rtw_init_stainfo(psta);
psta->padapter = pstapriv->padapter;
_rtw_memcpy(psta->hwaddr, hwaddr, ETH_ALEN);
index = wifi_mac_hash(hwaddr);
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("rtw_alloc_stainfo: index = %x", index));
if(index >= NUM_STA){
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("ERROR=> rtw_alloc_stainfo: index >= NUM_STA"));
psta= NULL;
goto exit;
}
phash_list = &(pstapriv->sta_hash[index]);
//_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
rtw_list_insert_tail(&psta->hash_list, phash_list);
pstapriv->asoc_sta_count ++ ;
//_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
// Commented by Albert 2009/08/13
// For the SMC router, the sequence number of first packet of WPS handshake will be 0.
// In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable.
// So, we initialize the tid_rxseq variable as the 0xffff.
for( i = 0; i < 16; i++ )
{
_rtw_memcpy( &psta->sta_recvpriv.rxcache.tid_rxseq[ i ], &wRxSeqInitialValue, 2 );
}
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("alloc number_%d stainfo with hwaddr = %x %x %x %x %x %x \n",
pstapriv->asoc_sta_count , hwaddr[0], hwaddr[1], hwaddr[2],hwaddr[3],hwaddr[4],hwaddr[5]));
init_addba_retry_timer(pstapriv->padapter, psta);
#ifdef CONFIG_TDLS
rtw_init_tdls_timer(pstapriv->padapter, psta);
#endif //CONFIG_TDLS
//for A-MPDU Rx reordering buffer control
for(i=0; i < 16 ; i++)
{
preorder_ctrl = &psta->recvreorder_ctrl[i];
preorder_ctrl->padapter = pstapriv->padapter;
preorder_ctrl->enable = _FALSE;
preorder_ctrl->indicate_seq = 0xffff;
#ifdef DBG_RX_SEQ
DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d\n", __FUNCTION__, __LINE__,
preorder_ctrl->indicate_seq);
#endif
preorder_ctrl->wend_b= 0xffff;
//preorder_ctrl->wsize_b = (NR_RECVBUFF-2);
preorder_ctrl->wsize_b = 64;//64;
_rtw_init_queue(&preorder_ctrl->pending_recvframe_queue);
rtw_init_recv_timer(preorder_ctrl);
}
//init for DM
psta->rssi_stat.UndecoratedSmoothedPWDB = (-1);
psta->rssi_stat.UndecoratedSmoothedCCK = (-1);
#ifdef CONFIG_ATMEL_RC_PATCH
psta->flag_atmel_rc = 0;
#endif
/* init for the sequence number of received management frame */
psta->RxMgmtFrameSeqNum = 0xffff;
//alloc mac id for non-bc/mc station,
rtw_alloc_macid(pstapriv->padapter, psta);
}
exit:
_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
_func_exit_;
return psta;
}
// using pstapriv->sta_hash_lock to protect
u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta)
{
int i;
_irqL irqL0;
_queue *pfree_sta_queue;
struct recv_reorder_ctrl *preorder_ctrl;
struct sta_xmit_priv *pstaxmitpriv;
struct xmit_priv *pxmitpriv= &padapter->xmitpriv;
struct sta_priv *pstapriv = &padapter->stapriv;
struct hw_xmit *phwxmit;
int pending_qcnt[4];
_func_enter_;
if (psta == NULL)
goto exit;
_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
rtw_list_delete(&psta->hash_list);
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("\n free number_%d stainfo with hwaddr = 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x \n",pstapriv->asoc_sta_count , psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5]));
pstapriv->asoc_sta_count --;
_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
_enter_critical_bh(&psta->lock, &irqL0);
psta->state &= ~_FW_LINKED;
_exit_critical_bh(&psta->lock, &irqL0);
pfree_sta_queue = &pstapriv->free_sta_queue;
pstaxmitpriv = &psta->sta_xmitpriv;
//rtw_list_delete(&psta->sleep_list);
//rtw_list_delete(&psta->wakeup_list);
_enter_critical_bh(&pxmitpriv->lock, &irqL0);
rtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q);
psta->sleepq_len = 0;
//vo
//_enter_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0);
rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->vo_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
phwxmit = pxmitpriv->hwxmits;
phwxmit->accnt -= pstaxmitpriv->vo_q.qcnt;
pending_qcnt[0] = pstaxmitpriv->vo_q.qcnt;
pstaxmitpriv->vo_q.qcnt = 0;
//_exit_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0);
//vi
//_enter_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0);
rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->vi_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
phwxmit = pxmitpriv->hwxmits+1;
phwxmit->accnt -= pstaxmitpriv->vi_q.qcnt;
pending_qcnt[1] = pstaxmitpriv->vi_q.qcnt;
pstaxmitpriv->vi_q.qcnt = 0;
//_exit_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0);
//be
//_enter_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0);
rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->be_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
phwxmit = pxmitpriv->hwxmits+2;
phwxmit->accnt -= pstaxmitpriv->be_q.qcnt;
pending_qcnt[2] = pstaxmitpriv->be_q.qcnt;
pstaxmitpriv->be_q.qcnt = 0;
//_exit_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0);
//bk
//_enter_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0);
rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->bk_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
phwxmit = pxmitpriv->hwxmits+3;
phwxmit->accnt -= pstaxmitpriv->bk_q.qcnt;
pending_qcnt[3] = pstaxmitpriv->bk_q.qcnt;
pstaxmitpriv->bk_q.qcnt = 0;
//_exit_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0);
rtw_os_wake_queue_at_free_stainfo(padapter, pending_qcnt);
_exit_critical_bh(&pxmitpriv->lock, &irqL0);
// re-init sta_info; 20061114 // will be init in alloc_stainfo
//_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
//_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
_cancel_timer_ex(&psta->addba_retry_timer);
#ifdef CONFIG_TDLS
rtw_free_tdls_timer(psta);
#endif //CONFIG_TDLS
//for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer
for(i=0; i < 16 ; i++)
{
_irqL irqL;
_list *phead, *plist;
union recv_frame *prframe;
_queue *ppending_recvframe_queue;
_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
preorder_ctrl = &psta->recvreorder_ctrl[i];
_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
_enter_critical_bh(&ppending_recvframe_queue->lock, &irqL);
phead = get_list_head(ppending_recvframe_queue);
plist = get_next(phead);
while(!rtw_is_list_empty(phead))
{
prframe = LIST_CONTAINOR(plist, union recv_frame, u);
plist = get_next(plist);
rtw_list_delete(&(prframe->u.hdr.list));
rtw_free_recvframe(prframe, pfree_recv_queue);
}
_exit_critical_bh(&ppending_recvframe_queue->lock, &irqL);
}
if (!(psta->state & WIFI_AP_STATE))
rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _FALSE);
//release mac id for non-bc/mc station,
rtw_release_macid(pstapriv->padapter, psta);
#ifdef CONFIG_AP_MODE
/*
_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
rtw_list_delete(&psta->asoc_list);
_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
*/
_enter_critical_bh(&pstapriv->auth_list_lock, &irqL0);
if (!rtw_is_list_empty(&psta->auth_list)) {
rtw_list_delete(&psta->auth_list);
pstapriv->auth_list_cnt--;
}
_exit_critical_bh(&pstapriv->auth_list_lock, &irqL0);
psta->expire_to = 0;
#ifdef CONFIG_ATMEL_RC_PATCH
psta->flag_atmel_rc = 0;
#endif
psta->sleepq_ac_len = 0;
psta->qos_info = 0;
psta->max_sp_len = 0;
psta->uapsd_bk = 0;
psta->uapsd_be = 0;
psta->uapsd_vi = 0;
psta->uapsd_vo = 0;
psta->has_legacy_ac = 0;
#ifdef CONFIG_NATIVEAP_MLME
pstapriv->sta_dz_bitmap &=~BIT(psta->aid);
pstapriv->tim_bitmap &=~BIT(psta->aid);
//rtw_indicate_sta_disassoc_event(padapter, psta);
if ((psta->aid >0)&&(pstapriv->sta_aid[psta->aid - 1] == psta))
{
pstapriv->sta_aid[psta->aid - 1] = NULL;
psta->aid = 0;
}
#endif // CONFIG_NATIVEAP_MLME
#ifdef CONFIG_TX_MCAST2UNI
psta->under_exist_checking = 0;
#endif // CONFIG_TX_MCAST2UNI
#endif // CONFIG_AP_MODE
_rtw_spinlock_free(&psta->lock);
//_enter_critical_bh(&(pfree_sta_queue->lock), &irqL0);
_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue));
_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
//_exit_critical_bh(&(pfree_sta_queue->lock), &irqL0);
exit:
_func_exit_;
return _SUCCESS;
}
// free all stainfo which in sta_hash[all]
void rtw_free_all_stainfo(_adapter *padapter)
{
_irqL irqL;
_list *plist, *phead;
s32 index;
struct sta_info *psta = NULL;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info* pbcmc_stainfo =rtw_get_bcmc_stainfo( padapter);
u8 free_sta_num = 0;
char free_sta_list[NUM_STA];
int stainfo_offset;
_func_enter_;
if(pstapriv->asoc_sta_count==1)
goto exit;
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
for(index=0; index< NUM_STA; index++)
{
phead = &(pstapriv->sta_hash[index]);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list);
plist = get_next(plist);
if(pbcmc_stainfo!=psta)
{
rtw_list_delete(&psta->hash_list);
//rtw_free_stainfo(padapter , psta);
stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
if (stainfo_offset_valid(stainfo_offset)) {
free_sta_list[free_sta_num++] = stainfo_offset;
}
}
}
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
for (index = 0; index < free_sta_num; index++)
{
psta = rtw_get_stainfo_by_offset(pstapriv, free_sta_list[index]);
rtw_free_stainfo(padapter , psta);
}
exit:
_func_exit_;
}
/* any station allocated can be searched by hash list */
struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
{
_irqL irqL;
_list *plist, *phead;
struct sta_info *psta = NULL;
u32 index;
u8 *addr;
u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
_func_enter_;
if(hwaddr==NULL)
return NULL;
if(IS_MCAST(hwaddr))
{
addr = bc_addr;
}
else
{
addr = hwaddr;
}
index = wifi_mac_hash(addr);
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
phead = &(pstapriv->sta_hash[index]);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
if ((_rtw_memcmp(psta->hwaddr, addr, ETH_ALEN))== _TRUE)
{ // if found the matched address
break;
}
psta=NULL;
plist = get_next(plist);
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
_func_exit_;
return psta;
}
u32 rtw_init_bcmc_stainfo(_adapter* padapter)
{
struct sta_info *psta;
struct tx_servq *ptxservq;
u32 res=_SUCCESS;
NDIS_802_11_MAC_ADDRESS bcast_addr= {0xff,0xff,0xff,0xff,0xff,0xff};
struct sta_priv *pstapriv = &padapter->stapriv;
//_queue *pstapending = &padapter->xmitpriv.bm_pending;
_func_enter_;
psta = rtw_alloc_stainfo(pstapriv, bcast_addr);
if(psta==NULL){
res=_FAIL;
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("rtw_alloc_stainfo fail"));
goto exit;
}
ptxservq= &(psta->sta_xmitpriv.be_q);
/*
_enter_critical(&pstapending->lock, &irqL0);
if (rtw_is_list_empty(&ptxservq->tx_pending))
rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(pstapending));
_exit_critical(&pstapending->lock, &irqL0);
*/
exit:
_func_exit_;
return _SUCCESS;
}
struct sta_info* rtw_get_bcmc_stainfo(_adapter* padapter)
{
struct sta_info *psta;
struct sta_priv *pstapriv = &padapter->stapriv;
u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
_func_enter_;
psta = rtw_get_stainfo(pstapriv, bc_addr);
_func_exit_;
return psta;
}
u8 rtw_access_ctrl(_adapter *padapter, u8 *mac_addr)
{
u8 res = _TRUE;
#ifdef CONFIG_AP_MODE
_irqL irqL;
_list *plist, *phead;
struct rtw_wlan_acl_node *paclnode;
u8 match = _FALSE;
struct sta_priv *pstapriv = &padapter->stapriv;
struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
_queue *pacl_node_q =&pacl_list->acl_node_q;
_enter_critical_bh(&(pacl_node_q->lock), &irqL);
phead = get_list_head(pacl_node_q);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list);
plist = get_next(plist);
if(_rtw_memcmp(paclnode->addr, mac_addr, ETH_ALEN))
{
if(paclnode->valid == _TRUE)
{
match = _TRUE;
break;
}
}
}
_exit_critical_bh(&(pacl_node_q->lock), &irqL);
if(pacl_list->mode == 1)//accept unless in deny list
{
res = (match == _TRUE) ? _FALSE:_TRUE;
}
else if(pacl_list->mode == 2)//deny unless in accept list
{
res = (match == _TRUE) ? _TRUE:_FALSE;
}
else
{
res = _TRUE;
}
#endif
return res;
}

2967
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_tdls.c
View File

File diff suppressed because it is too large Load Diff

734
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_vht.c
View File

@ -1,734 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTW_VHT_C
#include <drv_types.h>
#ifdef CONFIG_80211AC_VHT
// 20/40/80, ShortGI, MCS Rate
const u16 VHT_MCS_DATA_RATE[3][2][30] =
{ { {13, 26, 39, 52, 78, 104, 117, 130, 156, 156,
26, 52, 78, 104, 156, 208, 234, 260, 312, 312,
39, 78, 117, 156, 234, 312, 351, 390, 468, 520}, // Long GI, 20MHz
{14, 29, 43, 58, 87, 116, 130, 144, 173, 173,
29, 58, 87, 116, 173, 231, 260, 289, 347, 347,
43, 87, 130, 173, 260, 347,390, 433, 520, 578} }, // Short GI, 20MHz
{ {27, 54, 81, 108, 162, 216, 243, 270, 324, 360,
54, 108, 162, 216, 324, 432, 486, 540, 648, 720,
81, 162, 243, 324, 486, 648, 729, 810, 972, 1080}, // Long GI, 40MHz
{30, 60, 90, 120, 180, 240, 270, 300,360, 400,
60, 120, 180, 240, 360, 480, 540, 600, 720, 800,
90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200}}, // Short GI, 40MHz
{ {59, 117, 176, 234, 351, 468, 527, 585, 702, 780,
117, 234, 351, 468, 702, 936, 1053, 1170, 1404, 1560,
176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2106}, // Long GI, 80MHz
{65, 130, 195, 260, 390, 520, 585, 650, 780, 867,
130, 260, 390, 520, 780, 1040, 1170, 1300, 1560,1734,
195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2340} } // Short GI, 80MHz
};
u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map)
{
u8 i, j;
u8 bit_map;
u8 vht_mcs_rate = 0;
for(i = 0; i < 2; i++)
{
if(pvht_mcs_map[i] != 0xff)
{
for(j = 0; j < 8; j += 2)
{
bit_map = (pvht_mcs_map[i] >> j) & 3;
if(bit_map != 3)
vht_mcs_rate = MGN_VHT1SS_MCS7 + 10*j/2 + i*40 + bit_map; //VHT rate indications begin from 0x90
}
}
}
//DBG_871X("HighestVHTMCSRate is %x\n", vht_mcs_rate);
return vht_mcs_rate;
}
u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map)
{
u8 i, j;
u8 bit_map;
u8 nss = 0;
for(i = 0; i < 2; i++)
{
if(pvht_mcs_map[i] != 0xff)
{
for(j = 0; j < 8; j += 2)
{
bit_map = (pvht_mcs_map[i] >> j) & 3;
if(bit_map != 3)
nss++;
}
}
}
//DBG_871X("%s : %dSS\n", __FUNCTION__, nss);
return nss;
}
void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map)
{
u8 i, j;
u8 cur_rate, target_rate;
for(i = 0; i < 2; i++)
{
target_mcs_map[i] = 0;
for(j = 0; j < 8; j+=2)
{
cur_rate = (cur_mcs_map[i] >> j) & 3;
if(cur_rate == 3) //0x3 indicates not supported that num of SS
target_rate = 3;
else if(nss <= ((j/2)+i*4))
target_rate = 3;
else
target_rate = cur_rate;
target_mcs_map[i] |= (target_rate << j);
}
}
//DBG_871X("%s : %dSS\n", __FUNCTION__, nss);
}
u16 rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate)
{
if(vht_mcs_rate > MGN_VHT2SS_MCS9)
vht_mcs_rate = MGN_VHT2SS_MCS9;
return VHT_MCS_DATA_RATE[bw][short_GI][((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)];
}
void rtw_vht_use_default_setting(_adapter *padapter)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
BOOLEAN bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE;
BOOLEAN bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE;
u8 rf_type = 0;
pvhtpriv->sgi_80m = TEST_FLAG(pregistrypriv->short_gi, BIT2) ? _TRUE : _FALSE;
// LDPC support
rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport);
CLEAR_FLAGS(pvhtpriv->ldpc_cap);
if(bHwLDPCSupport)
{
if(TEST_FLAG(pregistrypriv->ldpc_cap, BIT0))
SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX);
}
rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport);
if(bHwLDPCSupport)
{
if(TEST_FLAG(pregistrypriv->ldpc_cap, BIT1))
SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX);
}
if (pvhtpriv->ldpc_cap)
DBG_871X("[VHT] Support LDPC = 0x%02X\n", pvhtpriv->ldpc_cap);
// STBC
rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport);
CLEAR_FLAGS(pvhtpriv->stbc_cap);
if(bHwSTBCSupport)
{
if(TEST_FLAG(pregistrypriv->stbc_cap, BIT1))
SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX);
}
rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport);
if(bHwSTBCSupport)
{
if(TEST_FLAG(pregistrypriv->stbc_cap, BIT0))
SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX);
}
if (pvhtpriv->stbc_cap)
DBG_871X("[VHT] Support STBC = 0x%02X\n", pvhtpriv->stbc_cap);
// Beamforming setting
rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer);
rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee);
CLEAR_FLAGS(pvhtpriv->beamform_cap);
if(TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer)
{
SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
DBG_871X("[VHT] Support Beamformer\n");
}
if(TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee)
{
SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
DBG_871X("[VHT] Support Beamformee\n");
}
pvhtpriv->ampdu_len = pregistrypriv->ampdu_factor;
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
if (rf_type == RF_1T1R)
pvhtpriv->vht_mcs_map[0] = 0xfe; // Only support 1SS MCS 0~9;
else
pvhtpriv->vht_mcs_map[0] = 0xfa; //support 1SS MCS 0~9 2SS MCS 0~9
pvhtpriv->vht_mcs_map[1] = 0xff;
if(pregistrypriv->vht_rate_sel == 1)
{
pvhtpriv->vht_mcs_map[0] = 0xfc; // support 1SS MCS 0~7
}
else if(pregistrypriv->vht_rate_sel == 2)
{
pvhtpriv->vht_mcs_map[0] = 0xfd; // Support 1SS MCS 0~8
}
else if(pregistrypriv->vht_rate_sel == 3)
{
pvhtpriv->vht_mcs_map[0] = 0xfe; // Support 1SS MCS 0~9
}
else if(pregistrypriv->vht_rate_sel == 4)
{
pvhtpriv->vht_mcs_map[0] = 0xf0; // support 1SS MCS 0~7 2SS MCS 0~7
}
else if(pregistrypriv->vht_rate_sel == 5)
{
pvhtpriv->vht_mcs_map[0] = 0xf5; // support 1SS MCS 0~8 2SS MCS 0~8
}
else if(pregistrypriv->vht_rate_sel == 6)
{
pvhtpriv->vht_mcs_map[0] = 0xfa; // support 1SS MCS 0~9 2SS MCS 0~9
}
else if(pregistrypriv->vht_rate_sel == 7)
{
pvhtpriv->vht_mcs_map[0] = 0xf8; // support 1SS MCS 0-7 2SS MCS 0~9
}
else if(pregistrypriv->vht_rate_sel == 8)
{
pvhtpriv->vht_mcs_map[0] = 0xf9; // support 1SS MCS 0-8 2SS MCS 0~9
}
else if(pregistrypriv->vht_rate_sel == 9)
{
pvhtpriv->vht_mcs_map[0] = 0xf4; // support 1SS MCS 0-7 2SS MCS 0~8
}
pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
}
u32 rtw_vht_rate_to_bitmap(u8 *pVHTRate)
{
u8 i,j , tmpRate;
u32 RateBitmap = 0;
for(i = j= 0; i < 4; i+=2, j+=10)
{
tmpRate = (pVHTRate[0] >> i) & 3;
switch(tmpRate){
case 2:
RateBitmap = RateBitmap | (0x03ff << j);
break;
case 1:
RateBitmap = RateBitmap | (0x01ff << j);
break;
case 0:
RateBitmap = RateBitmap | (0x00ff << j);
break;
default:
break;
}
}
return RateBitmap;
}
void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta)
{
struct sta_info *psta = (struct sta_info *)sta;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv;
struct vht_priv *pvhtpriv_sta = &psta->vhtpriv;
struct ht_priv *phtpriv_sta = &psta->htpriv;
u8 cur_ldpc_cap=0, cur_stbc_cap=0, cur_beamform_cap=0, bw_mode = 0;
u8 *pcap_mcs;
if (pvhtpriv_sta->vht_option == _FALSE) {
return;
}
bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify);
//if (bw_mode > psta->bw_mode)
psta->bw_mode = bw_mode;
// B4 Rx LDPC
if (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap))
{
SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
DBG_871X("Current STA(%d) VHT LDPC = %02X\n", psta->aid, cur_ldpc_cap);
}
pvhtpriv_sta->ldpc_cap = cur_ldpc_cap;
if (psta->bw_mode > pmlmeext->cur_bwmode)
psta->bw_mode = pmlmeext->cur_bwmode;
if (psta->bw_mode == CHANNEL_WIDTH_80) {
// B5 Short GI for 80 MHz
pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
//DBG_871X("Current STA ShortGI80MHz = %d\n", pvhtpriv_sta->sgi_80m);
} else if (psta->bw_mode >= CHANNEL_WIDTH_160) {
// B5 Short GI for 80 MHz
pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
//DBG_871X("Current STA ShortGI160MHz = %d\n", pvhtpriv_sta->sgi_80m);
}
// B8 B9 B10 Rx STBC
if (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) &&
GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap))
{
SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
DBG_871X("Current STA(%d) VHT STBC = %02X\n", psta->aid, cur_stbc_cap);
}
pvhtpriv_sta->stbc_cap = cur_stbc_cap;
// B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee
if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap))
{
SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
}
// B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer
if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap))
{
SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
}
pvhtpriv_sta->beamform_cap = cur_beamform_cap;
if (cur_beamform_cap) {
DBG_871X("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->aid, cur_beamform_cap);
}
// B23 B24 B25 Maximum A-MPDU Length Exponent
pvhtpriv_sta->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pvhtpriv_sta->vht_cap);
pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pvhtpriv_sta->vht_cap);
_rtw_memcpy(pvhtpriv_sta->vht_mcs_map, pcap_mcs, 2);
pvhtpriv_sta->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv_sta->vht_mcs_map);
}
void update_hw_vht_param(_adapter *padapter)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
u8 ht_AMPDU_len;
ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
if(pvhtpriv->ampdu_len > ht_AMPDU_len)
rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len));
}
void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
u8 cur_ldpc_cap=0, cur_stbc_cap=0, cur_beamform_cap=0, rf_type = RF_1T1R;
u8 *pcap_mcs;
u8 vht_mcs[2];
if(pIE==NULL) return;
if(pvhtpriv->vht_option == _FALSE) return;
pmlmeinfo->VHT_enable = 1;
// B4 Rx LDPC
if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data))
{
SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
DBG_871X("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap);
}
pvhtpriv->ldpc_cap = cur_ldpc_cap;
// B5 Short GI for 80 MHz
pvhtpriv->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pIE->data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE;
//DBG_871X("Current ShortGI80MHz = %d\n", pvhtpriv->sgi_80m);
// B8 B9 B10 Rx STBC
if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) &&
GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data))
{
SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
DBG_871X("Current VHT STBC Setting = %02X\n", cur_stbc_cap);
}
pvhtpriv->stbc_cap = cur_stbc_cap;
// B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data))
{
SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
}
// B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data))
{
SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
}
pvhtpriv->beamform_cap = cur_beamform_cap;
if (cur_beamform_cap) {
DBG_871X("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap);
}
// B23 B24 B25 Maximum A-MPDU Length Exponent
pvhtpriv->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pIE->data);
pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data);
_rtw_memcpy(vht_mcs, pcap_mcs, 2);
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
if ((rf_type == RF_1T1R) || (rf_type == RF_1T2R))
vht_mcs[0] |= 0xfc;
else if (rf_type == RF_2T2R)
vht_mcs[0] |= 0xf0;
_rtw_memcpy(pvhtpriv->vht_mcs_map, vht_mcs, 2);
pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
}
void VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
if(pIE==NULL) return;
if(pvhtpriv->vht_option == _FALSE) return;
}
void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta)
{
struct sta_info *psta = (struct sta_info *)sta;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
u8 target_bw;
u8 target_rxss, current_rxss;
u8 update_ra = _FALSE;
u8 vht_mcs_map[2] = {};
if(pvhtpriv->vht_option == _FALSE)
return;
target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(pframe);
target_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe)+1);
if (target_bw != psta->bw_mode) {
if (target_bw <= (padapter->registrypriv.bw_mode >> 4)) {
update_ra = _TRUE;
psta->bw_mode = target_bw;
}
}
current_rxss = rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map);
if (target_rxss != current_rxss) {
update_ra = _TRUE;
rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map);
_rtw_memcpy(psta->vhtpriv.vht_mcs_map, vht_mcs_map, 2);
rtw_hal_update_sta_rate_mask(padapter, psta);
}
if (update_ra) {
rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta);
}
}
u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel)
{
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
//struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
u8 ChnlWidth, center_freq, bw_mode;
u32 len = 0;
u8 operation[5];
_rtw_memset(operation, 0, 5);
bw_mode = pregistrypriv->bw_mode >> 4;
if (bw_mode >= CHANNEL_WIDTH_80)
{
center_freq = rtw_get_center_ch(channel, bw_mode, HAL_PRIME_CHNL_OFFSET_LOWER);
ChnlWidth = 1;
}
else
{
center_freq = 0;
ChnlWidth = 0;
}
SET_VHT_OPERATION_ELE_CHL_WIDTH(operation, ChnlWidth);
//center frequency
SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(operation, center_freq);//Todo: need to set correct center channel
SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(operation,0);
operation[3] = 0xff;
operation[4] = 0xff;
rtw_set_ie(pbuf, EID_VHTOperation, 5, operation, &len);
return len;
}
u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw)
{
//struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
u32 len = 0;
u8 opmode = 0, rf_type = 0;
u8 chnl_width, rx_nss;
chnl_width = bw;
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
if(rf_type == RF_1T1R)
rx_nss = 1;
else
rx_nss = 2;
SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&opmode, chnl_width);
SET_VHT_OPERATING_MODE_FIELD_RX_NSS(&opmode, (rx_nss-1));
SET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(&opmode, 0); //Todo
pvhtpriv->vht_op_mode_notify = opmode;
pbuf = rtw_set_ie(pbuf, EID_OpModeNotification, 1, &opmode, &len);
return len;
}
u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
{
u8 bw, rf_type;
u16 HighestRate;
u8 *pcap, *pcap_mcs;
u32 len = 0;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
pcap = pvhtpriv->vht_cap;
_rtw_memset(pcap, 0, 32);
// B2 B3 Supported Channel Width Set
SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0); //indicate we don't support neither 160M nor 80+80M bandwidth.
// B4 Rx LDPC
if(TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX))
{
SET_VHT_CAPABILITY_ELE_RX_LDPC(pcap, 1);
}
// B5 ShortGI for 80MHz
SET_VHT_CAPABILITY_ELE_SHORT_GI80M(pcap, pvhtpriv->sgi_80m? 1 : 0); // We can receive Short GI of 80M
// B6 ShortGI for 160MHz
//SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pcap, pvhtpriv->sgi_80m? 1 : 0);
// B7 Tx STBC
if(TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX))
{
SET_VHT_CAPABILITY_ELE_TX_STBC(pcap, 1);
}
// B8 B9 B10 Rx STBC
if(TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX))
{
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
if ((rf_type == RF_2T2R) || (rf_type == RF_1T2R)) {
SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, 2);
}
else if (rf_type == RF_1T1R) {
SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, 1);
}
}
// B11 SU Beamformer Capable
if(TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE))
{
SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1);
// B16 17 18 Number of Sounding Dimensions
SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, 1);
}
// B12 SU Beamformee Capable
if(TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE))
{
SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1);
// B13 14 15 Compressed Steering Number of Beamformer Antennas Supported
SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, 1);
}
// B19 MU Beamformer Capable
SET_VHT_CAPABILITY_ELE_MU_BFER(pcap, 0); //HW don't support mu bfee/bfer
// B20 MU Beamformee Capable
SET_VHT_CAPABILITY_ELE_MU_BFEE(pcap, 0);
// B21 VHT TXOP PS
SET_VHT_CAPABILITY_ELE_TXOP_PS(pcap, 0);
// B22 +HTC-VHT Capable
SET_VHT_CAPABILITY_ELE_HTC_VHT(pcap, 1);
// B23 24 25 Maximum A-MPDU Length Exponent
if (pregistrypriv->ampdu_factor != 0xFE)
{
SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, pregistrypriv->ampdu_factor);
}
else
{
SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, 7);
}
// B26 27 VHT Link Adaptation Capable
SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(pcap, 0);
pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pcap);
_rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);
pcap_mcs = GET_VHT_CAPABILITY_ELE_TX_MCS(pcap);
_rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);
bw = (pregistrypriv->bw_mode >> 4);
HighestRate = VHT_MCS_DATA_RATE[bw][pvhtpriv->sgi_80m][((pvhtpriv->vht_highest_rate - MGN_VHT1SS_MCS0)&0x3f)];
HighestRate = (HighestRate+1) >> 1;
SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(pcap, HighestRate); //indicate we support highest rx rate is 600Mbps.
SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(pcap, HighestRate); //indicate we support highest tx rate is 600Mbps.
pbuf = rtw_set_ie(pbuf, EID_VHTCapability, 12, pcap, &len);
return len;
}
u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len)
{
u32 ielen=0, out_len=0;
u8 cap_len=0, notify_len=0, notify_bw=0, operation_bw=0, supported_chnl_width=0;
u8 *p, *pframe;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
rtw_vht_use_default_setting(padapter);
p = rtw_get_ie(in_ie+12, EID_VHTCapability, &ielen, in_len-12);
if (p && ielen>0) {
supported_chnl_width = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p+2);
// VHT Capabilities element
cap_len = rtw_build_vht_cap_ie(padapter, out_ie+*pout_len);
*pout_len += cap_len;
// Get HT BW
p = rtw_get_ie(in_ie+12, _HT_EXTRA_INFO_IE_, &ielen, in_len-12);
if (p && ielen>0) {
struct HT_info_element *pht_info = (struct HT_info_element *)(p+2);
if (pht_info->infos[0] & BIT(2))
operation_bw = CHANNEL_WIDTH_40;
else
operation_bw = CHANNEL_WIDTH_20;
}
// VHT Operation element
p = rtw_get_ie(in_ie+12, EID_VHTOperation, &ielen, in_len-12);
if (p && ielen>0) {
out_len = *pout_len;
if (GET_VHT_OPERATION_ELE_CHL_WIDTH(p+2) >= 1) {
if (supported_chnl_width == 2)
operation_bw = CHANNEL_WIDTH_80_80;
else if (supported_chnl_width == 1)
operation_bw = CHANNEL_WIDTH_160;
else
operation_bw = CHANNEL_WIDTH_80;
}
pframe = rtw_set_ie(out_ie+out_len, EID_VHTOperation, ielen, p+2 , pout_len);
}
notify_bw = pregistrypriv->bw_mode >> 4;
if (notify_bw > operation_bw)
notify_bw = operation_bw;
// Operating Mode Notification element
notify_len = rtw_build_vht_op_mode_notify_ie(padapter, out_ie+*pout_len, notify_bw);
*pout_len += notify_len;
pvhtpriv->vht_option = _TRUE;
}
return (pvhtpriv->vht_option);
}
void VHTOnAssocRsp(_adapter *padapter)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
u8 ht_AMPDU_len;
DBG_871X("%s\n", __FUNCTION__);
if (!pmlmeinfo->HT_enable)
return;
if (!pmlmeinfo->VHT_enable)
return;
ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
if(pvhtpriv->ampdu_len > ht_AMPDU_len)
rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len));
rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MAX_TIME, (u8 *)(&pvhtpriv->vht_highest_rate));
}
#endif //CONFIG_80211AC_VHT

1327
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_wapi.c
View File

File diff suppressed because it is too large Load Diff

924
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_wapi_sms4.c
View File

@ -1,924 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifdef CONFIG_WAPI_SUPPORT
#include <linux/unistd.h>
#include <linux/etherdevice.h>
#include <drv_types.h>
#include <rtw_wapi.h>
#ifdef CONFIG_WAPI_SW_SMS4
#define WAPI_LITTLE_ENDIAN
//#define BIG_ENDIAN
#define ENCRYPT 0
#define DECRYPT 1
/**********************************************************
**********************************************************/
const u8 Sbox[256] = {
0xd6,0x90,0xe9,0xfe,0xcc,0xe1,0x3d,0xb7,0x16,0xb6,0x14,0xc2,0x28,0xfb,0x2c,0x05,
0x2b,0x67,0x9a,0x76,0x2a,0xbe,0x04,0xc3,0xaa,0x44,0x13,0x26,0x49,0x86,0x06,0x99,
0x9c,0x42,0x50,0xf4,0x91,0xef,0x98,0x7a,0x33,0x54,0x0b,0x43,0xed,0xcf,0xac,0x62,
0xe4,0xb3,0x1c,0xa9,0xc9,0x08,0xe8,0x95,0x80,0xdf,0x94,0xfa,0x75,0x8f,0x3f,0xa6,
0x47,0x07,0xa7,0xfc,0xf3,0x73,0x17,0xba,0x83,0x59,0x3c,0x19,0xe6,0x85,0x4f,0xa8,
0x68,0x6b,0x81,0xb2,0x71,0x64,0xda,0x8b,0xf8,0xeb,0x0f,0x4b,0x70,0x56,0x9d,0x35,
0x1e,0x24,0x0e,0x5e,0x63,0x58,0xd1,0xa2,0x25,0x22,0x7c,0x3b,0x01,0x21,0x78,0x87,
0xd4,0x00,0x46,0x57,0x9f,0xd3,0x27,0x52,0x4c,0x36,0x02,0xe7,0xa0,0xc4,0xc8,0x9e,
0xea,0xbf,0x8a,0xd2,0x40,0xc7,0x38,0xb5,0xa3,0xf7,0xf2,0xce,0xf9,0x61,0x15,0xa1,
0xe0,0xae,0x5d,0xa4,0x9b,0x34,0x1a,0x55,0xad,0x93,0x32,0x30,0xf5,0x8c,0xb1,0xe3,
0x1d,0xf6,0xe2,0x2e,0x82,0x66,0xca,0x60,0xc0,0x29,0x23,0xab,0x0d,0x53,0x4e,0x6f,
0xd5,0xdb,0x37,0x45,0xde,0xfd,0x8e,0x2f,0x03,0xff,0x6a,0x72,0x6d,0x6c,0x5b,0x51,
0x8d,0x1b,0xaf,0x92,0xbb,0xdd,0xbc,0x7f,0x11,0xd9,0x5c,0x41,0x1f,0x10,0x5a,0xd8,
0x0a,0xc1,0x31,0x88,0xa5,0xcd,0x7b,0xbd,0x2d,0x74,0xd0,0x12,0xb8,0xe5,0xb4,0xb0,
0x89,0x69,0x97,0x4a,0x0c,0x96,0x77,0x7e,0x65,0xb9,0xf1,0x09,0xc5,0x6e,0xc6,0x84,
0x18,0xf0,0x7d,0xec,0x3a,0xdc,0x4d,0x20,0x79,0xee,0x5f,0x3e,0xd7,0xcb,0x39,0x48
};
const u32 CK[32] = {
0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269,
0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9,
0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249,
0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9,
0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229,
0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299,
0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209,
0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279 };
#define Rotl(_x, _y) (((_x) << (_y)) | ((_x) >> (32 - (_y))))
#define ByteSub(_A) (Sbox[(_A) >> 24 & 0xFF] << 24 | \
Sbox[(_A) >> 16 & 0xFF] << 16 | \
Sbox[(_A) >> 8 & 0xFF] << 8 | \
Sbox[(_A) & 0xFF])
#define L1(_B) ((_B) ^ Rotl(_B, 2) ^ Rotl(_B, 10) ^ Rotl(_B, 18) ^ Rotl(_B, 24))
#define L2(_B) ((_B) ^ Rotl(_B, 13) ^ Rotl(_B, 23))
static void
xor_block(void *dst, void *src1, void *src2)
/* 128-bit xor: *dst = *src1 xor *src2. Pointers must be 32-bit aligned */
{
((u32 *)dst)[0] = ((u32 *)src1)[0] ^ ((u32 *)src2)[0];
((u32 *)dst)[1] = ((u32 *)src1)[1] ^ ((u32 *)src2)[1];
((u32 *)dst)[2] = ((u32 *)src1)[2] ^ ((u32 *)src2)[2];
((u32 *)dst)[3] = ((u32 *)src1)[3] ^ ((u32 *)src2)[3];
}
void SMS4Crypt(u8 *Input, u8 *Output, u32 *rk)
{
u32 r, mid, x0, x1, x2, x3, *p;
p = (u32 *)Input;
x0 = p[0];
x1 = p[1];
x2 = p[2];
x3 = p[3];
#ifdef WAPI_LITTLE_ENDIAN
x0 = Rotl(x0, 16); x0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
x1 = Rotl(x1, 16); x1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
x2 = Rotl(x2, 16); x2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
x3 = Rotl(x3, 16); x3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
#endif
for (r = 0; r < 32; r += 4)
{
mid = x1 ^ x2 ^ x3 ^ rk[r + 0];
mid = ByteSub(mid);
x0 ^= L1(mid);
mid = x2 ^ x3 ^ x0 ^ rk[r + 1];
mid = ByteSub(mid);
x1 ^= L1(mid);
mid = x3 ^ x0 ^ x1 ^ rk[r + 2];
mid = ByteSub(mid);
x2 ^= L1(mid);
mid = x0 ^ x1 ^ x2 ^ rk[r + 3];
mid = ByteSub(mid);
x3 ^= L1(mid);
}
#ifdef WAPI_LITTLE_ENDIAN
x0 = Rotl(x0, 16); x0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
x1 = Rotl(x1, 16); x1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
x2 = Rotl(x2, 16); x2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
x3 = Rotl(x3, 16); x3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
#endif
p = (u32 *)Output;
p[0] = x3;
p[1] = x2;
p[2] = x1;
p[3] = x0;
}
void SMS4KeyExt(u8 *Key, u32 *rk, u32 CryptFlag)
{
u32 r, mid, x0, x1, x2, x3, *p;
p = (u32 *)Key;
x0 = p[0];
x1 = p[1];
x2 = p[2];
x3 = p[3];
#ifdef WAPI_LITTLE_ENDIAN
x0 = Rotl(x0, 16); x0 = ((x0 & 0xFF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
x1 = Rotl(x1, 16); x1 = ((x1 & 0xFF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
x2 = Rotl(x2, 16); x2 = ((x2 & 0xFF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
x3 = Rotl(x3, 16); x3 = ((x3 & 0xFF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
#endif
x0 ^= 0xa3b1bac6;
x1 ^= 0x56aa3350;
x2 ^= 0x677d9197;
x3 ^= 0xb27022dc;
for (r = 0; r < 32; r += 4)
{
mid = x1 ^ x2 ^ x3 ^ CK[r + 0];
mid = ByteSub(mid);
rk[r + 0] = x0 ^= L2(mid);
mid = x2 ^ x3 ^ x0 ^ CK[r + 1];
mid = ByteSub(mid);
rk[r + 1] = x1 ^= L2(mid);
mid = x3 ^ x0 ^ x1 ^ CK[r + 2];
mid = ByteSub(mid);
rk[r + 2] = x2 ^= L2(mid);
mid = x0 ^ x1 ^ x2 ^ CK[r + 3];
mid = ByteSub(mid);
rk[r + 3] = x3 ^= L2(mid);
}
if (CryptFlag == DECRYPT)
{
for (r = 0; r < 16; r++)
mid = rk[r], rk[r] = rk[31 - r], rk[31 - r] = mid;
}
}
void WapiSMS4Cryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
u8 *Output, u16 *OutputLength, u32 CryptFlag)
{
u32 blockNum,i,j, rk[32];
u16 remainder;
u8 blockIn[16],blockOut[16], tempIV[16], k;
*OutputLength = 0;
remainder = InputLength & 0x0F;
blockNum = InputLength >> 4;
if(remainder !=0)
blockNum++;
else
remainder = 16;
for(k=0;k<16;k++)
tempIV[k] = IV[15-k];
memcpy(blockIn, tempIV, 16);
SMS4KeyExt((u8 *)Key, rk,CryptFlag);
for(i=0; i<blockNum-1; i++)
{
SMS4Crypt((u8 *)blockIn, blockOut, rk);
xor_block(&Output[i*16], &Input[i*16], blockOut);
memcpy(blockIn,blockOut,16);
}
*OutputLength = i*16;
SMS4Crypt((u8 *)blockIn, blockOut, rk);
for(j=0; j<remainder; j++)
{
Output[i*16+j] = Input[i*16+j] ^ blockOut[j];
}
*OutputLength += remainder;
}
void WapiSMS4Encryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
u8 *Output, u16 *OutputLength)
{
WapiSMS4Cryption(Key, IV, Input, InputLength, Output, OutputLength, ENCRYPT);
}
void WapiSMS4Decryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
u8 *Output, u16 *OutputLength)
{
// OFB mode: is also ENCRYPT flag
WapiSMS4Cryption(Key, IV, Input, InputLength, Output, OutputLength, ENCRYPT);
}
void WapiSMS4CalculateMic(u8 *Key, u8 *IV, u8 *Input1, u8 Input1Length,
u8 *Input2, u16 Input2Length, u8 *Output, u8 *OutputLength)
{
u32 blockNum, i, remainder, rk[32];
u8 BlockIn[16], BlockOut[16], TempBlock[16], tempIV[16], k;
*OutputLength = 0;
remainder = Input1Length & 0x0F;
blockNum = Input1Length >> 4;
for(k=0;k<16;k++)
tempIV[k] = IV[15-k];
memcpy(BlockIn, tempIV, 16);
SMS4KeyExt((u8 *)Key, rk, ENCRYPT);
SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
for(i=0; i<blockNum; i++){
xor_block(BlockIn, (Input1+i*16), BlockOut);
SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
}
if(remainder !=0){
memset(TempBlock, 0, 16);
memcpy(TempBlock, (Input1+blockNum*16), remainder);
xor_block(BlockIn, TempBlock, BlockOut);
SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
}
remainder = Input2Length & 0x0F;
blockNum = Input2Length >> 4;
for(i=0; i<blockNum; i++){
xor_block(BlockIn, (Input2+i*16), BlockOut);
SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
}
if(remainder !=0){
memset(TempBlock, 0, 16);
memcpy(TempBlock, (Input2+blockNum*16), remainder);
xor_block(BlockIn, TempBlock, BlockOut);
SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
}
memcpy(Output, BlockOut, 16);
*OutputLength = 16;
}
void SecCalculateMicSMS4(
u8 KeyIdx,
u8 *MicKey,
u8 *pHeader,
u8 *pData,
u16 DataLen,
u8 *MicBuffer
)
{
#if 0
struct ieee80211_hdr_3addr_qos *header;
u8 TempBuf[34], TempLen = 32, MicLen, QosOffset, *IV;
u16 *pTemp, fc;
WAPI_TRACE(WAPI_TX|WAPI_RX, "=========>%s\n", __FUNCTION__);
header = (struct ieee80211_hdr_3addr_qos *)pHeader;
memset(TempBuf, 0, 34);
memcpy(TempBuf, pHeader, 2); //FrameCtrl
pTemp = (u16*)TempBuf;
*pTemp &= 0xc78f; //bit4,5,6,11,12,13
memcpy((TempBuf+2), (pHeader+4), 12); //Addr1, Addr2
memcpy((TempBuf+14), (pHeader+22), 2); // SeqCtrl
pTemp = (u16*)(TempBuf + 14);
*pTemp &= 0x000f;
memcpy((TempBuf+16), (pHeader+16), 6); //Addr3
fc = le16_to_cpu(header->frame_ctl);
if (GetFrDs((u16*)&fc) && GetToDs((u16 *)&fc))
{
memcpy((TempBuf+22), (pHeader+24), 6);
QosOffset = 30;
}else{
memset((TempBuf+22), 0, 6);
QosOffset = 24;
}
if((fc & 0x0088) == 0x0088){
memcpy((TempBuf+28), (pHeader+QosOffset), 2);
TempLen += 2;
//IV = pHeader + QosOffset + 2 + SNAP_SIZE + sizeof(u16) + 2;
IV = pHeader + QosOffset + 2 + 2;
}else{
IV = pHeader + QosOffset + 2;
//IV = pHeader + QosOffset + SNAP_SIZE + sizeof(u16) + 2;
}
TempBuf[TempLen-1] = (u8)(DataLen & 0xff);
TempBuf[TempLen-2] = (u8)((DataLen & 0xff00)>>8);
TempBuf[TempLen-4] = KeyIdx;
WAPI_DATA(WAPI_TX, "CalculateMic - KEY", MicKey, 16);
WAPI_DATA(WAPI_TX, "CalculateMic - IV", IV, 16);
WAPI_DATA(WAPI_TX, "CalculateMic - TempBuf", TempBuf, TempLen);
WAPI_DATA(WAPI_TX, "CalculateMic - pData", pData, DataLen);
WapiSMS4CalculateMic(MicKey, IV, TempBuf, TempLen,
pData, DataLen, MicBuffer, &MicLen);
if (MicLen != 16)
WAPI_TRACE(WAPI_ERR,"%s: MIC Length Error!!\n",__FUNCTION__);
WAPI_TRACE(WAPI_TX|WAPI_RX, "<=========%s\n", __FUNCTION__);
#endif
}
/* AddCount: 1 or 2.
* If overflow, return 1,
* else return 0.
*/
u8 WapiIncreasePN(u8 *PN, u8 AddCount)
{
u8 i;
if (NULL == PN)
return 1;
//YJ,test,091102
/*
if(AddCount == 2){
DBG_8192C("############################%s(): PN[0]=0x%x\n", __FUNCTION__, PN[0]);
if(PN[0] == 0x48){
PN[0] += AddCount;
return 1;
}else{
PN[0] += AddCount;
return 0;
}
}
*/
//YJ,test,091102,end
for (i=0; i<16; i++)
{
if (PN[i] + AddCount <= 0xff)
{
PN[i] += AddCount;
return 0;
}
else
{
PN[i] += AddCount;
AddCount = 1;
}
}
return 1;
}
void WapiGetLastRxUnicastPNForQoSData(
u8 UserPriority,
PRT_WAPI_STA_INFO pWapiStaInfo,
u8 *PNOut
)
{
WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
switch(UserPriority)
{
case 0:
case 3:
memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNBEQueue,16);
break;
case 1:
case 2:
memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNBKQueue,16);
break;
case 4:
case 5:
memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNVIQueue,16);
break;
case 6:
case 7:
memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNVOQueue,16);
break;
default:
WAPI_TRACE(WAPI_ERR, "%s: Unknown TID \n", __FUNCTION__);
break;
}
WAPI_TRACE(WAPI_RX, "<=========== %s\n", __FUNCTION__);
}
void WapiSetLastRxUnicastPNForQoSData(
u8 UserPriority,
u8 *PNIn,
PRT_WAPI_STA_INFO pWapiStaInfo
)
{
WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
switch(UserPriority)
{
case 0:
case 3:
memcpy(pWapiStaInfo->lastRxUnicastPNBEQueue,PNIn,16);
break;
case 1:
case 2:
memcpy(pWapiStaInfo->lastRxUnicastPNBKQueue,PNIn,16);
break;
case 4:
case 5:
memcpy(pWapiStaInfo->lastRxUnicastPNVIQueue,PNIn,16);
break;
case 6:
case 7:
memcpy(pWapiStaInfo->lastRxUnicastPNVOQueue,PNIn,16);
break;
default:
WAPI_TRACE(WAPI_ERR, "%s: Unknown TID \n", __FUNCTION__);
break;
}
WAPI_TRACE(WAPI_RX, "<=========== %s\n", __FUNCTION__);
}
/****************************************************************************
FALSE not RX-Reorder
TRUE do RX Reorder
add to support WAPI to N-mode
*****************************************************************************/
u8 WapiCheckPnInSwDecrypt(
_adapter *padapter,
struct sk_buff *pskb
)
{
u8 ret = false;
#if 0
struct ieee80211_hdr_3addr_qos *header;
u16 fc;
u8 *pDaddr, *pTaddr, *pRaddr;
header = (struct ieee80211_hdr_3addr_qos *)pskb->data;
pTaddr = header->addr2;
pRaddr = header->addr1;
fc = le16_to_cpu(header->frame_ctl);
if(GetToDs(&fc))
pDaddr = header->addr3;
else
pDaddr = header->addr1;
if ((_rtw_memcmp(pRaddr, padapter->pnetdev->dev_addr, ETH_ALEN) == 0)
&& ! (pDaddr)
&& (GetFrameType(&fc) == WIFI_QOS_DATA_TYPE))
//&& ieee->pHTInfo->bCurrentHTSupport &&
//ieee->pHTInfo->bCurRxReorderEnable)
ret = false;
else
ret = true;
#endif
WAPI_TRACE(WAPI_RX, "%s: return %d\n", __FUNCTION__, ret);
return ret;
}
int SecSMS4HeaderFillIV(_adapter *padapter, u8 *pxmitframe)
{
struct pkt_attrib *pattrib = &((struct xmit_frame*)pxmitframe)->attrib;
u8 * frame = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_OFFSET;
u8 *pSecHeader = NULL, *pos = NULL, *pRA = NULL;
u8 bPNOverflow = false, bFindMatchPeer = false, hdr_len = 0;
PWLAN_HEADER_WAPI_EXTENSION pWapiExt = NULL;
PRT_WAPI_T pWapiInfo = &padapter->wapiInfo;
PRT_WAPI_STA_INFO pWapiSta = NULL;
int ret = 0;
WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
return ret;
#if 0
hdr_len = sMacHdrLng;
if (GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE)
{
hdr_len += 2;
}
//hdr_len += SNAP_SIZE + sizeof(u16);
pos = skb_push(pskb, padapter->wapiInfo.extra_prefix_len);
memmove(pos, pos+padapter->wapiInfo.extra_prefix_len, hdr_len);
pSecHeader = pskb->data + hdr_len;
pWapiExt = (PWLAN_HEADER_WAPI_EXTENSION)pSecHeader;
pRA = pskb->data + 4;
WAPI_DATA(WAPI_TX, "FillIV - Before Fill IV", pskb->data, pskb->len);
//Address 1 is always receiver's address
if( IS_MCAST(pRA) ){
if(!pWapiInfo->wapiTxMsk.bTxEnable){
WAPI_TRACE(WAPI_ERR,"%s: bTxEnable = 0!!\n",__FUNCTION__);
return -2;
}
if(pWapiInfo->wapiTxMsk.keyId <= 1){
pWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId;
pWapiExt->Reserved = 0;
bPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1);
memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16);
if (bPNOverflow){
// Update MSK Notification.
WAPI_TRACE(WAPI_ERR,"===============>%s():multicast PN overflow\n",__FUNCTION__);
rtw_wapi_app_event_handler(padapter,NULL,0,pRA, false, false, true, 0, false);
}
}else{
WAPI_TRACE(WAPI_ERR,"%s: Invalid Wapi Multicast KeyIdx!!\n",__FUNCTION__);
ret = -3;
}
}
else{
list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
if(!memcmp(pWapiSta->PeerMacAddr,pRA,6)){
bFindMatchPeer = true;
break;
}
}
if (bFindMatchPeer){
if((!pWapiSta->wapiUskUpdate.bTxEnable) && (!pWapiSta->wapiUsk.bTxEnable)){
WAPI_TRACE(WAPI_ERR,"%s: bTxEnable = 0!!\n",__FUNCTION__);
return -4;
}
if (pWapiSta->wapiUsk.keyId <= 1){
if(pWapiSta->wapiUskUpdate.bTxEnable)
pWapiExt->KeyIdx = pWapiSta->wapiUskUpdate.keyId;
else
pWapiExt->KeyIdx = pWapiSta->wapiUsk.keyId;
pWapiExt->Reserved = 0;
bPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2);
memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16);
if (bPNOverflow){
// Update USK Notification.
WAPI_TRACE(WAPI_ERR,"===============>%s():unicast PN overflow\n",__FUNCTION__);
rtw_wapi_app_event_handler(padapter,NULL,0,pWapiSta->PeerMacAddr, false, true, false, 0, false);
}
}else{
WAPI_TRACE(WAPI_ERR,"%s: Invalid Wapi Unicast KeyIdx!!\n",__FUNCTION__);
ret = -5;
}
}
else{
WAPI_TRACE(WAPI_ERR,"%s: Can not find Peer Sta "MAC_FMT"!!\n",__FUNCTION__, MAC_ARG(pRA));
ret = -6;
}
}
WAPI_DATA(WAPI_TX, "FillIV - After Fill IV", pskb->data, pskb->len);
WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
return ret;
#endif
}
// WAPI SW Enc: must have done Coalesce!
void SecSWSMS4Encryption(
_adapter *padapter,
u8 * pxmitframe
)
{
PRT_WAPI_T pWapiInfo = &padapter->wapiInfo;
PRT_WAPI_STA_INFO pWapiSta = NULL;
u8 *pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_SIZE;
struct pkt_attrib *pattrib = &((struct xmit_frame*)pxmitframe)->attrib;
u8 *SecPtr = NULL, *pRA, *pMicKey = NULL, *pDataKey = NULL, *pIV = NULL;
u8 IVOffset, DataOffset, bFindMatchPeer = false, KeyIdx = 0, MicBuffer[16];
u16 OutputLength;
WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
WAPI_TRACE(WAPI_TX,"hdrlen: %d \n",pattrib->hdrlen);
return;
DataOffset = pattrib->hdrlen + pattrib->iv_len;
pRA = pframe + 4;
if( IS_MCAST(pRA) ){
KeyIdx = pWapiInfo->wapiTxMsk.keyId;
pIV = pWapiInfo->lastTxMulticastPN;
pMicKey = pWapiInfo->wapiTxMsk.micKey;
pDataKey = pWapiInfo->wapiTxMsk.dataKey;
}else{
if (!list_empty(&(pWapiInfo->wapiSTAUsedList))){
list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
if (0 == memcmp(pWapiSta->PeerMacAddr, pRA, 6)){
bFindMatchPeer = true;
break;
}
}
if (bFindMatchPeer){
if (pWapiSta->wapiUskUpdate.bTxEnable){
KeyIdx = pWapiSta->wapiUskUpdate.keyId;
WAPI_TRACE(WAPI_TX, "%s(): Use update USK!! KeyIdx=%d\n", __FUNCTION__, KeyIdx);
pIV = pWapiSta->lastTxUnicastPN;
pMicKey = pWapiSta->wapiUskUpdate.micKey;
pDataKey = pWapiSta->wapiUskUpdate.dataKey;
}else{
KeyIdx = pWapiSta->wapiUsk.keyId;
WAPI_TRACE(WAPI_TX, "%s(): Use USK!! KeyIdx=%d\n", __FUNCTION__, KeyIdx);
pIV = pWapiSta->lastTxUnicastPN;
pMicKey = pWapiSta->wapiUsk.micKey;
pDataKey = pWapiSta->wapiUsk.dataKey;
}
}else{
WAPI_TRACE(WAPI_ERR,"%s: Can not find Peer Sta!!\n",__FUNCTION__);
return;
}
}else{
WAPI_TRACE(WAPI_ERR,"%s: wapiSTAUsedList is empty!!\n",__FUNCTION__);
return;
}
}
SecPtr = pframe;
SecCalculateMicSMS4(KeyIdx, pMicKey, SecPtr, (SecPtr+DataOffset), pattrib->pktlen, MicBuffer);
WAPI_DATA(WAPI_TX, "Encryption - MIC", MicBuffer, padapter->wapiInfo.extra_postfix_len);
memcpy(pframe+pattrib->hdrlen+pattrib->iv_len+pattrib->pktlen-pattrib->icv_len,
(u8 *)MicBuffer,
padapter->wapiInfo.extra_postfix_len
);
WapiSMS4Encryption(pDataKey, pIV, (SecPtr+DataOffset),pattrib->pktlen+pattrib->icv_len, (SecPtr+DataOffset), &OutputLength);
WAPI_DATA(WAPI_TX, "Encryption - After SMS4 encryption",pframe,pattrib->hdrlen+pattrib->iv_len+pattrib->pktlen);
WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
}
u8 SecSWSMS4Decryption(
_adapter *padapter,
u8 *precv_frame,
struct recv_priv *precv_priv
)
{
PRT_WAPI_T pWapiInfo = &padapter->wapiInfo;
struct recv_frame_hdr *precv_hdr;
PRT_WAPI_STA_INFO pWapiSta = NULL;
u8 IVOffset, DataOffset, bFindMatchPeer = false, bUseUpdatedKey = false;
u8 KeyIdx, MicBuffer[16], lastRxPNforQoS[16];
u8 *pRA, *pTA, *pMicKey, *pDataKey, *pLastRxPN, *pRecvPN, *pSecData, *pRecvMic, *pos;
u8 TID = 0;
u16 OutputLength, DataLen;
u8 bQosData;
struct sk_buff * pskb;
WAPI_TRACE(WAPI_RX, "=========>%s\n", __FUNCTION__);
return 0;
precv_hdr = &((union recv_frame*)precv_frame)->u.hdr;
pskb = (struct sk_buff *)(precv_hdr->rx_data);
precv_hdr->bWapiCheckPNInDecrypt = WapiCheckPnInSwDecrypt(padapter, pskb);
WAPI_TRACE(WAPI_RX, "=========>%s: check PN %d\n", __FUNCTION__,precv_hdr->bWapiCheckPNInDecrypt);
WAPI_DATA(WAPI_RX, "Decryption - Before decryption", pskb->data, pskb->len);
IVOffset = sMacHdrLng;
bQosData = GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE;
if (bQosData){
IVOffset += 2;
}
//if(GetHTC())
// IVOffset += 4;
//IVOffset += SNAP_SIZE + sizeof(u16);
DataOffset = IVOffset + padapter->wapiInfo.extra_prefix_len;
pRA = pskb->data + 4;
pTA = pskb->data + 10;
KeyIdx = *(pskb->data + IVOffset);
pRecvPN = pskb->data + IVOffset + 2;
pSecData = pskb->data + DataOffset;
DataLen = pskb->len - DataOffset;
pRecvMic = pskb->data + pskb->len - padapter->wapiInfo.extra_postfix_len;
TID = GetTid(pskb->data);
if (!list_empty(&(pWapiInfo->wapiSTAUsedList))){
list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
if (0 == memcmp(pWapiSta->PeerMacAddr, pTA, 6)){
bFindMatchPeer = true;
break;
}
}
}
if (!bFindMatchPeer){
WAPI_TRACE(WAPI_ERR, "%s: Can not find Peer Sta "MAC_FMT" for Key Info!!!\n", __FUNCTION__, MAC_ARG(pTA));
return false;
}
if( IS_MCAST(pRA) ){
WAPI_TRACE(WAPI_RX, "%s: Multicast decryption !!!\n", __FUNCTION__);
if (pWapiSta->wapiMsk.keyId == KeyIdx && pWapiSta->wapiMsk.bSet){
pLastRxPN = pWapiSta->lastRxMulticastPN;
if (!WapiComparePN(pRecvPN, pLastRxPN)){
WAPI_TRACE(WAPI_ERR, "%s: MSK PN is not larger than last, Dropped!!!\n", __FUNCTION__);
WAPI_DATA(WAPI_ERR, "pRecvPN:", pRecvPN, 16);
WAPI_DATA(WAPI_ERR, "pLastRxPN:", pLastRxPN, 16);
return false;
}
memcpy(pLastRxPN, pRecvPN, 16);
pMicKey = pWapiSta->wapiMsk.micKey;
pDataKey = pWapiSta->wapiMsk.dataKey;
}else if (pWapiSta->wapiMskUpdate.keyId == KeyIdx && pWapiSta->wapiMskUpdate.bSet){
WAPI_TRACE(WAPI_RX, "%s: Use Updated MSK for Decryption !!!\n", __FUNCTION__);
bUseUpdatedKey = true;
memcpy(pWapiSta->lastRxMulticastPN, pRecvPN, 16);
pMicKey = pWapiSta->wapiMskUpdate.micKey;
pDataKey = pWapiSta->wapiMskUpdate.dataKey;
}else{
WAPI_TRACE(WAPI_ERR, "%s: Can not find MSK with matched KeyIdx(%d), Dropped !!!\n", __FUNCTION__,KeyIdx);
return false;
}
}
else{
WAPI_TRACE(WAPI_RX, "%s: Unicast decryption !!!\n", __FUNCTION__);
if (pWapiSta->wapiUsk.keyId == KeyIdx && pWapiSta->wapiUsk.bSet){
WAPI_TRACE(WAPI_RX, "%s: Use USK for Decryption!!!\n", __FUNCTION__);
if(precv_hdr->bWapiCheckPNInDecrypt){
if(GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE){
WapiGetLastRxUnicastPNForQoSData(TID, pWapiSta, lastRxPNforQoS);
pLastRxPN = lastRxPNforQoS;
}else{
pLastRxPN = pWapiSta->lastRxUnicastPN;
}
if (!WapiComparePN(pRecvPN, pLastRxPN)){
return false;
}
if(bQosData){
WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta);
}else{
memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16);
}
}else{
memcpy(precv_hdr->WapiTempPN,pRecvPN,16);
}
if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE))
{
if ((pRecvPN[0] & 0x1) == 0){
WAPI_TRACE(WAPI_ERR, "%s: Rx USK PN is not odd when Infra STA mode, Dropped !!!\n", __FUNCTION__);
return false;
}
}
pMicKey = pWapiSta->wapiUsk.micKey;
pDataKey = pWapiSta->wapiUsk.dataKey;
}
else if (pWapiSta->wapiUskUpdate.keyId == KeyIdx && pWapiSta->wapiUskUpdate.bSet ){
WAPI_TRACE(WAPI_RX, "%s: Use Updated USK for Decryption!!!\n", __FUNCTION__);
if(pWapiSta->bAuthenticatorInUpdata)
bUseUpdatedKey = true;
else
bUseUpdatedKey = false;
if(bQosData){
WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta);
}else{
memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16);
}
pMicKey = pWapiSta->wapiUskUpdate.micKey;
pDataKey = pWapiSta->wapiUskUpdate.dataKey;
}else{
WAPI_TRACE(WAPI_ERR, "%s: No valid USK!!!KeyIdx=%d pWapiSta->wapiUsk.keyId=%d pWapiSta->wapiUskUpdate.keyId=%d\n", __FUNCTION__, KeyIdx, pWapiSta->wapiUsk.keyId, pWapiSta->wapiUskUpdate.keyId);
//dump_buf(pskb->data,pskb->len);
return false;
}
}
WAPI_DATA(WAPI_RX, "Decryption - DataKey", pDataKey, 16);
WAPI_DATA(WAPI_RX, "Decryption - IV", pRecvPN, 16);
WapiSMS4Decryption(pDataKey, pRecvPN, pSecData, DataLen, pSecData, &OutputLength);
if (OutputLength != DataLen)
WAPI_TRACE(WAPI_ERR, "%s: Output Length Error!!!!\n", __FUNCTION__);
WAPI_DATA(WAPI_RX, "Decryption - After decryption", pskb->data, pskb->len);
DataLen -= padapter->wapiInfo.extra_postfix_len;
SecCalculateMicSMS4(KeyIdx, pMicKey, pskb->data, pSecData, DataLen, MicBuffer);
WAPI_DATA(WAPI_RX, "Decryption - MIC received", pRecvMic, SMS4_MIC_LEN);
WAPI_DATA(WAPI_RX, "Decryption - MIC calculated", MicBuffer, SMS4_MIC_LEN);
if (0 == memcmp(MicBuffer, pRecvMic, padapter->wapiInfo.extra_postfix_len)){
WAPI_TRACE(WAPI_RX, "%s: Check MIC OK!!\n", __FUNCTION__);
if (bUseUpdatedKey){
// delete the old key
if ( IS_MCAST(pRA) ){
WAPI_TRACE(WAPI_API, "%s(): AE use new update MSK!!\n", __FUNCTION__);
pWapiSta->wapiMsk.keyId = pWapiSta->wapiMskUpdate.keyId;
memcpy(pWapiSta->wapiMsk.dataKey, pWapiSta->wapiMskUpdate.dataKey, 16);
memcpy(pWapiSta->wapiMsk.micKey, pWapiSta->wapiMskUpdate.micKey, 16);
pWapiSta->wapiMskUpdate.bTxEnable = pWapiSta->wapiMskUpdate.bSet = false;
}else{
WAPI_TRACE(WAPI_API, "%s(): AE use new update USK!!\n", __FUNCTION__);
pWapiSta->wapiUsk.keyId = pWapiSta->wapiUskUpdate.keyId;
memcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16);
memcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16);
pWapiSta->wapiUskUpdate.bTxEnable = pWapiSta->wapiUskUpdate.bSet = false;
}
}
}else{
WAPI_TRACE(WAPI_ERR, "%s: Check MIC Error, Dropped !!!!\n", __FUNCTION__);
return false;
}
pos = pskb->data;
memmove(pos+padapter->wapiInfo.extra_prefix_len, pos, IVOffset);
skb_pull(pskb, padapter->wapiInfo.extra_prefix_len);
WAPI_TRACE(WAPI_RX, "<=========%s\n", __FUNCTION__);
return true;
}
u32 rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe)
{
u8 *pframe;
u32 res = _SUCCESS;
WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable))
{
WAPI_TRACE(WAPI_TX, "<========== %s, WAPI not supported or enabled!\n", __FUNCTION__);
return _FAIL;
}
if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL)
return _FAIL;
pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_OFFSET;
SecSWSMS4Encryption(padapter, pxmitframe);
WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
return res;
}
u32 rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe)
{
u8 *pframe;
u32 res = _SUCCESS;
WAPI_TRACE(WAPI_RX, "=========>%s\n", __FUNCTION__);
if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable))
{
WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or enabled!\n", __FUNCTION__);
return _FAIL;
}
//drop packet when hw decrypt fail
//return tempraily
return _FAIL;
//pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data;
if (false == SecSWSMS4Decryption(padapter, precvframe, &padapter->recvpriv))
{
WAPI_TRACE(WAPI_ERR, "%s():SMS4 decrypt frame error\n",__FUNCTION__);
return _FAIL;
}
WAPI_TRACE(WAPI_RX, "<=========%s\n", __FUNCTION__);
return res;
}
#else
u32 rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe)
{
WAPI_TRACE(WAPI_TX, "=========>Dummy %s\n", __FUNCTION__);
WAPI_TRACE(WAPI_TX, "<=========Dummy %s\n", __FUNCTION__);
return _SUCCESS;
}
u32 rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe)
{
WAPI_TRACE(WAPI_RX, "=========>Dummy %s\n", __FUNCTION__);
WAPI_TRACE(WAPI_RX, "<=========Dummy %s\n", __FUNCTION__);
return _SUCCESS;
}
#endif
#endif

4292
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_wlan_util.c
View File

File diff suppressed because it is too large Load Diff

4860
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/core/rtw_xmit.c
View File

File diff suppressed because it is too large Load Diff

183
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/HalPwrSeqCmd.c
View File

@ -1,183 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
HalPwrSeqCmd.c
Abstract:
Implement HW Power sequence configuration CMD handling routine for Realtek devices.
Major Change History:
When Who What
---------- --------------- -------------------------------
2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
2011-07-07 Roger Create.
--*/
#include <HalPwrSeqCmd.h>
//
// Description:
// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
//
// Assumption:
// We should follow specific format which was released from HW SD.
//
// 2011.07.07, added by Roger.
//
u8 HalPwrSeqCmdParsing(
PADAPTER padapter,
u8 CutVersion,
u8 FabVersion,
u8 InterfaceType,
WLAN_PWR_CFG PwrSeqCmd[])
{
WLAN_PWR_CFG PwrCfgCmd = {0};
u8 bPollingBit = _FALSE;
u32 AryIdx = 0;
u8 value = 0;
u32 offset = 0;
u32 pollingCount = 0; // polling autoload done.
u32 maxPollingCnt = 5000;
do {
PwrCfgCmd = PwrSeqCmd[AryIdx];
RT_TRACE(_module_hal_init_c_ , _drv_info_,
("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
GET_PWR_CFG_OFFSET(PwrCfgCmd),
GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
GET_PWR_CFG_BASE(PwrCfgCmd),
GET_PWR_CFG_CMD(PwrCfgCmd),
GET_PWR_CFG_MASK(PwrCfgCmd),
GET_PWR_CFG_VALUE(PwrCfgCmd)));
//2 Only Handle the command whose FAB, CUT, and Interface are matched
if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
(GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
(GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType))
{
switch (GET_PWR_CFG_CMD(PwrCfgCmd))
{
case PWR_CMD_READ:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
break;
case PWR_CMD_WRITE:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
#ifdef CONFIG_SDIO_HCI
//
// <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
// 2011.07.07.
//
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
{
// Read Back SDIO Local value
value = SdioLocalCmd52Read1Byte(padapter, offset);
value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
// Write Back SDIO Local value
SdioLocalCmd52Write1Byte(padapter, offset, value);
}
else
#endif
{
#ifdef CONFIG_GSPI_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
offset = SPI_LOCAL_OFFSET | offset;
#endif
// Read the value from system register
value = rtw_read8(padapter, offset);
value=value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));
value=value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));
// Write the value back to sytem register
rtw_write8(padapter, offset, value);
}
break;
case PWR_CMD_POLLING:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
bPollingBit = _FALSE;
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
#ifdef CONFIG_GSPI_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
offset = SPI_LOCAL_OFFSET | offset;
#endif
do {
#ifdef CONFIG_SDIO_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
value = SdioLocalCmd52Read1Byte(padapter, offset);
else
#endif
value = rtw_read8(padapter, offset);
value=value&GET_PWR_CFG_MASK(PwrCfgCmd);
if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
bPollingBit = _TRUE;
else
rtw_udelay_os(10);
if (pollingCount++ > maxPollingCnt) {
DBG_871X_LEVEL(_drv_always_, "HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
return _FALSE;
}
} while (!bPollingBit);
break;
case PWR_CMD_DELAY:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
else
rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
break;
case PWR_CMD_END:
// When this command is parsed, end the process
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
return _TRUE;
break;
default:
RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
break;
}
}
AryIdx++;//Add Array Index
}while(1);
return _TRUE;
}

2028
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8188c2Ant.c
View File

File diff suppressed because it is too large Load Diff

150
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8188c2Ant.h
View File

@ -1,150 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
//===========================================
// The following is for 8188C 2Ant BT Co-exist definition
//===========================================
#define BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT 6
typedef enum _BT_INFO_SRC_8188C_2ANT{
BT_INFO_SRC_8188C_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8188C_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8188C_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8188C_2ANT_MAX
}BT_INFO_SRC_8188C_2ANT,*PBT_INFO_SRC_8188C_2ANT;
typedef enum _BT_8188C_2ANT_BT_STATUS{
BT_8188C_2ANT_BT_STATUS_IDLE = 0x0,
BT_8188C_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8188C_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8188C_2ANT_BT_STATUS_MAX
}BT_8188C_2ANT_BT_STATUS,*PBT_8188C_2ANT_BT_STATUS;
typedef enum _BT_8188C_2ANT_COEX_ALGO{
BT_8188C_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8188C_2ANT_COEX_ALGO_SCO = 0x1,
BT_8188C_2ANT_COEX_ALGO_HID = 0x2,
BT_8188C_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8188C_2ANT_COEX_ALGO_PAN = 0x4,
BT_8188C_2ANT_COEX_ALGO_HID_A2DP = 0x5,
BT_8188C_2ANT_COEX_ALGO_HID_PAN = 0x6,
BT_8188C_2ANT_COEX_ALGO_PAN_A2DP = 0x7,
BT_8188C_2ANT_COEX_ALGO_MAX
}BT_8188C_2ANT_COEX_ALGO,*PBT_8188C_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8188C_2ANT{
// fw mechanism
BOOLEAN bPreBalanceOn;
BOOLEAN bCurBalanceOn;
// diminishWifi
BOOLEAN bPreDacOn;
BOOLEAN bCurDacOn;
BOOLEAN bPreInterruptOn;
BOOLEAN bCurInterruptOn;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bPreNavOn;
BOOLEAN bCurNavOn;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
//u4Byte preVal0x6c0;
//u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u4Byte preVal0x6cc;
u4Byte curVal0x6cc;
//BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
//u1Byte btStatus;
//u1Byte wifiChnlInfo[3];
} COEX_DM_8188C_2ANT, *PCOEX_DM_8188C_2ANT;
typedef struct _COEX_STA_8188C_2ANT{
u1Byte preWifiRssiState[4];
BOOLEAN bBtBusy;
BOOLEAN bBtUplink;
BOOLEAN bBtDownLink;
BOOLEAN bA2dpBusy;
}COEX_STA_8188C_2ANT, *PCOEX_STA_8188C_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8188c2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8188c2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8188c2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8188c2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8188c2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8188c2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8188c2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

2033
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8192d2Ant.c
View File

File diff suppressed because it is too large Load Diff

171
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8192d2Ant.h
View File

@ -1,171 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
//===========================================
// The following is for 8192D 2Ant BT Co-exist definition
//===========================================
#define BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT 6
typedef enum _BT_INFO_SRC_8192D_2ANT{
BT_INFO_SRC_8192D_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8192D_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8192D_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8192D_2ANT_MAX
}BT_INFO_SRC_8192D_2ANT,*PBT_INFO_SRC_8192D_2ANT;
typedef enum _BT_8192D_2ANT_BT_STATUS{
BT_8192D_2ANT_BT_STATUS_IDLE = 0x0,
BT_8192D_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8192D_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8192D_2ANT_BT_STATUS_MAX
}BT_8192D_2ANT_BT_STATUS,*PBT_8192D_2ANT_BT_STATUS;
typedef enum _BT_8192D_2ANT_COEX_ALGO{
BT_8192D_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8192D_2ANT_COEX_ALGO_SCO = 0x1,
BT_8192D_2ANT_COEX_ALGO_HID = 0x2,
BT_8192D_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8192D_2ANT_COEX_ALGO_PAN = 0x4,
BT_8192D_2ANT_COEX_ALGO_HID_A2DP = 0x5,
BT_8192D_2ANT_COEX_ALGO_HID_PAN = 0x6,
BT_8192D_2ANT_COEX_ALGO_PAN_A2DP = 0x7,
BT_8192D_2ANT_COEX_ALGO_MAX
}BT_8192D_2ANT_COEX_ALGO,*PBT_8192D_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8192D_2ANT{
// fw mechanism
BOOLEAN bPreBalanceOn;
BOOLEAN bCurBalanceOn;
// diminishWifi
BOOLEAN bPreDacOn;
BOOLEAN bCurDacOn;
BOOLEAN bPreInterruptOn;
BOOLEAN bCurInterruptOn;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bPreNavOn;
BOOLEAN bCurNavOn;
//BOOLEAN bPreDecBtPwr;
//BOOLEAN bCurDecBtPwr;
//u1Byte preFwDacSwingLvl;
//u1Byte curFwDacSwingLvl;
//BOOLEAN bCurIgnoreWlanAct;
//BOOLEAN bPreIgnoreWlanAct;
//u1Byte prePsTdma;
//u1Byte curPsTdma;
//u1Byte psTdmaPara[5];
//u1Byte psTdmaDuAdjType;
//BOOLEAN bResetTdmaAdjust;
//BOOLEAN bPrePsTdmaOn;
//BOOLEAN bCurPsTdmaOn;
//BOOLEAN bPreBtAutoReport;
//BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
//u4Byte preVal0x6c0;
//u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u4Byte preVal0x6cc;
u4Byte curVal0x6cc;
//BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
//u1Byte btStatus;
//u1Byte wifiChnlInfo[3];
} COEX_DM_8192D_2ANT, *PCOEX_DM_8192D_2ANT;
typedef struct _COEX_STA_8192D_2ANT{
u1Byte preWifiRssiState[4];
BOOLEAN bBtBusy;
BOOLEAN bBtUplink;
BOOLEAN bBtDownLink;
BOOLEAN bA2dpBusy;
}COEX_STA_8192D_2ANT, *PCOEX_STA_8192D_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8192d2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192d2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8192d2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192d2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192d2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192d2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8192d2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

3242
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8192e1Ant.c
View File

File diff suppressed because it is too large Load Diff

215
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8192e1Ant.h
View File

@ -1,215 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
//===========================================
// The following is for 8192E_1ANT BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8192E_1ANT 0
#define BT_INFO_8192E_1ANT_B_FTP BIT7
#define BT_INFO_8192E_1ANT_B_A2DP BIT6
#define BT_INFO_8192E_1ANT_B_HID BIT5
#define BT_INFO_8192E_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8192E_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8192E_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8192E_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8192E_1ANT_B_CONNECTION BIT0
#define BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT 2
typedef enum _BT_INFO_SRC_8192E_1ANT{
BT_INFO_SRC_8192E_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8192E_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8192E_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8192E_1ANT_MAX
}BT_INFO_SRC_8192E_1ANT,*PBT_INFO_SRC_8192E_1ANT;
typedef enum _BT_8192E_1ANT_BT_STATUS{
BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8192E_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8192E_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8192E_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8192E_1ANT_BT_STATUS_MAX
}BT_8192E_1ANT_BT_STATUS,*PBT_8192E_1ANT_BT_STATUS;
typedef enum _BT_8192E_1ANT_WIFI_STATUS{
BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8192E_1ANT_WIFI_STATUS_MAX
}BT_8192E_1ANT_WIFI_STATUS,*PBT_8192E_1ANT_WIFI_STATUS;
typedef enum _BT_8192E_1ANT_COEX_ALGO{
BT_8192E_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8192E_1ANT_COEX_ALGO_SCO = 0x1,
BT_8192E_1ANT_COEX_ALGO_HID = 0x2,
BT_8192E_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8192E_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8192E_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8192E_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8192E_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8192E_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8192E_1ANT_COEX_ALGO,*PBT_8192E_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8192E_1ANT{
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u1Byte preSsType;
u1Byte curSsType;
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte errorCondition;
} COEX_DM_8192E_1ANT, *PCOEX_DM_8192E_1ANT;
typedef struct _COEX_STA_8192E_1ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8192E_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8192E_1ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8192E_1ANT, *PCOEX_STA_8192E_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8192e1ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8192e1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8192e1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8192e1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);

4370
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8192e2Ant.c
View File

File diff suppressed because it is too large Load Diff

207
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8192e2Ant.h
View File

@ -1,207 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
//===========================================
// The following is for 8192E 2Ant BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8192E_2ANT 0
#define BT_INFO_8192E_2ANT_B_FTP BIT7
#define BT_INFO_8192E_2ANT_B_A2DP BIT6
#define BT_INFO_8192E_2ANT_B_HID BIT5
#define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8192E_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT 2
typedef enum _BT_INFO_SRC_8192E_2ANT{
BT_INFO_SRC_8192E_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8192E_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8192E_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8192E_2ANT_MAX
}BT_INFO_SRC_8192E_2ANT,*PBT_INFO_SRC_8192E_2ANT;
typedef enum _BT_8192E_2ANT_BT_STATUS{
BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8192E_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8192E_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8192E_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8192E_2ANT_BT_STATUS_MAX
}BT_8192E_2ANT_BT_STATUS,*PBT_8192E_2ANT_BT_STATUS;
typedef enum _BT_8192E_2ANT_COEX_ALGO{
BT_8192E_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8192E_2ANT_COEX_ALGO_SCO = 0x1,
BT_8192E_2ANT_COEX_ALGO_SCO_PAN = 0x2,
BT_8192E_2ANT_COEX_ALGO_HID = 0x3,
BT_8192E_2ANT_COEX_ALGO_A2DP = 0x4,
BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS = 0x5,
BT_8192E_2ANT_COEX_ALGO_PANEDR = 0x6,
BT_8192E_2ANT_COEX_ALGO_PANHS = 0x7,
BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8,
BT_8192E_2ANT_COEX_ALGO_PANEDR_HID = 0x9,
BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa,
BT_8192E_2ANT_COEX_ALGO_HID_A2DP = 0xb,
BT_8192E_2ANT_COEX_ALGO_MAX = 0xc
}BT_8192E_2ANT_COEX_ALGO,*PBT_8192E_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8192E_2ANT{
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u1Byte preSsType;
u1Byte curSsType;
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte curRaMaskType;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
} COEX_DM_8192E_2ANT, *PCOEX_DM_8192E_2ANT;
typedef struct _COEX_STA_8192E_2ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8192E_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8192E_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8192E_2ANT, *PCOEX_STA_8192E_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8192e2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8192e2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8192e2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

1559
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8723a1Ant.c
View File

File diff suppressed because it is too large Load Diff

172
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8723a1Ant.h
View File

@ -1,172 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
//===========================================
// The following is for 8723A 1Ant BT Co-exist definition
//===========================================
#define BT_INFO_8723A_1ANT_B_FTP BIT7
#define BT_INFO_8723A_1ANT_B_A2DP BIT6
#define BT_INFO_8723A_1ANT_B_HID BIT5
#define BT_INFO_8723A_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723A_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723A_1ANT_B_CONNECTION BIT0
typedef enum _BT_STATE_8723A_1ANT{
BT_STATE_8723A_1ANT_DISABLED = 0,
BT_STATE_8723A_1ANT_NO_CONNECTION = 1,
BT_STATE_8723A_1ANT_CONNECT_IDLE = 2,
BT_STATE_8723A_1ANT_INQ_OR_PAG = 3,
BT_STATE_8723A_1ANT_ACL_ONLY_BUSY = 4,
BT_STATE_8723A_1ANT_SCO_ONLY_BUSY = 5,
BT_STATE_8723A_1ANT_ACL_SCO_BUSY = 6,
BT_STATE_8723A_1ANT_HID_BUSY = 7,
BT_STATE_8723A_1ANT_HID_SCO_BUSY = 8,
BT_STATE_8723A_1ANT_MAX
}BT_STATE_8723A_1ANT, *PBT_STATE_8723A_1ANT;
#define BTC_RSSI_COEX_THRESH_TOL_8723A_1ANT 2
typedef enum _BT_INFO_SRC_8723A_1ANT{
BT_INFO_SRC_8723A_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723A_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723A_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723A_1ANT_MAX
}BT_INFO_SRC_8723A_1ANT,*PBT_INFO_SRC_8723A_1ANT;
typedef enum _BT_8723A_1ANT_BT_STATUS{
BT_8723A_1ANT_BT_STATUS_IDLE = 0x0,
BT_8723A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723A_1ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8723A_1ANT_BT_STATUS_MAX
}BT_8723A_1ANT_BT_STATUS,*PBT_8723A_1ANT_BT_STATUS;
typedef enum _BT_8723A_1ANT_COEX_ALGO{
BT_8723A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723A_1ANT_COEX_ALGO_SCO = 0x1,
BT_8723A_1ANT_COEX_ALGO_HID = 0x2,
BT_8723A_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8723A_1ANT_COEX_ALGO_PANEDR = 0x4,
BT_8723A_1ANT_COEX_ALGO_PANHS = 0x5,
BT_8723A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x6,
BT_8723A_1ANT_COEX_ALGO_PANEDR_HID = 0x7,
BT_8723A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8,
BT_8723A_1ANT_COEX_ALGO_HID_A2DP = 0x9,
BT_8723A_1ANT_COEX_ALGO_MAX
}BT_8723A_1ANT_COEX_ALGO,*PBT_8723A_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8723A_1ANT{
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
u4Byte psTdmaMonitorCnt;
u4Byte psTdmaGlobalCnt;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
} COEX_DM_8723A_1ANT, *PCOEX_DM_8723A_1ANT;
typedef struct _COEX_STA_8723A_1ANT{
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preBtRssiState1;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723A_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_1ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
//BOOLEAN bHoldForStackOperation;
//u1Byte bHoldPeriodCnt;
// this is for c2h hang work-around
u4Byte c2hHangDetectCnt;
}COEX_STA_8723A_1ANT, *PCOEX_STA_8723A_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723a1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723a1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

3799
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8723a2Ant.c
View File

File diff suppressed because it is too large Load Diff

185
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8723a2Ant.h
View File

@ -1,185 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
//===========================================
// The following is for 8723A 2Ant BT Co-exist definition
//===========================================
#define BT_INFO_8723A_2ANT_B_FTP BIT7
#define BT_INFO_8723A_2ANT_B_A2DP BIT6
#define BT_INFO_8723A_2ANT_B_HID BIT5
#define BT_INFO_8723A_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723A_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723A_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723A_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723A_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT 2
typedef enum _BT_INFO_SRC_8723A_2ANT{
BT_INFO_SRC_8723A_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723A_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723A_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723A_2ANT_MAX
}BT_INFO_SRC_8723A_2ANT,*PBT_INFO_SRC_8723A_2ANT;
typedef enum _BT_8723A_2ANT_BT_STATUS{
BT_8723A_2ANT_BT_STATUS_IDLE = 0x0,
BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723A_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8723A_2ANT_BT_STATUS_MAX
}BT_8723A_2ANT_BT_STATUS,*PBT_8723A_2ANT_BT_STATUS;
typedef enum _BT_8723A_2ANT_COEX_ALGO{
BT_8723A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723A_2ANT_COEX_ALGO_SCO = 0x1,
BT_8723A_2ANT_COEX_ALGO_HID = 0x2,
BT_8723A_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8723A_2ANT_COEX_ALGO_PANEDR = 0x4,
BT_8723A_2ANT_COEX_ALGO_PANHS = 0x5,
BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x6,
BT_8723A_2ANT_COEX_ALGO_PANEDR_HID = 0x7,
BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8,
BT_8723A_2ANT_COEX_ALGO_HID_A2DP = 0x9,
BT_8723A_2ANT_COEX_ALGO_MAX
}BT_8723A_2ANT_COEX_ALGO,*PBT_8723A_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8723A_2ANT{
// fw mechanism
BOOLEAN bPreDecBtPwr;
BOOLEAN bCurDecBtPwr;
//BOOLEAN bPreBtLnaConstrain;
//BOOLEAN bCurBtLnaConstrain;
//u1Byte bPreBtPsdMode;
//u1Byte bCurBtPsdMode;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
//BOOLEAN bPreBtAutoReport;
//BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
} COEX_DM_8723A_2ANT, *PCOEX_DM_8723A_2ANT;
typedef struct _COEX_STA_8723A_2ANT{
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preBtRssiState1;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723A_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
BOOLEAN bHoldForStackOperation;
u1Byte bHoldPeriodCnt;
// this is for c2h hang work-around
u4Byte c2hHangDetectCnt;
}COEX_STA_8723A_2ANT, *PCOEX_STA_8723A_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723a2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8723a2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723a2ant_StackOperationNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

4824
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8723b1Ant.c
View File

File diff suppressed because it is too large Load Diff

316
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8723b1Ant.h
View File

@ -1,316 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
//===========================================
// The following is for 8723B 1ANT BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8723B_1ANT 1
#define BT_INFO_8723B_1ANT_B_FTP BIT7
#define BT_INFO_8723B_1ANT_B_A2DP BIT6
#define BT_INFO_8723B_1ANT_B_HID BIT5
#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
#define BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT 2
#define BT_8723B_1ANT_WIFI_NOISY_THRESH 30 //max: 255
typedef enum _BT_INFO_SRC_8723B_1ANT{
BT_INFO_SRC_8723B_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723B_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723B_1ANT_MAX
}BT_INFO_SRC_8723B_1ANT,*PBT_INFO_SRC_8723B_1ANT;
typedef enum _BT_8723B_1ANT_BT_STATUS{
BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723B_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8723B_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8723B_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8723B_1ANT_BT_STATUS_MAX
}BT_8723B_1ANT_BT_STATUS,*PBT_8723B_1ANT_BT_STATUS;
typedef enum _BT_8723B_1ANT_WIFI_STATUS{
BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8723B_1ANT_WIFI_STATUS_MAX
}BT_8723B_1ANT_WIFI_STATUS,*PBT_8723B_1ANT_WIFI_STATUS;
typedef enum _BT_8723B_1ANT_COEX_ALGO{
BT_8723B_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723B_1ANT_COEX_ALGO_SCO = 0x1,
BT_8723B_1ANT_COEX_ALGO_HID = 0x2,
BT_8723B_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8723B_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8723B_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8723B_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8723B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8723B_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8723B_1ANT_COEX_ALGO,*PBT_8723B_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8723B_1ANT{
// hw setting
u1Byte preAntPosType;
u1Byte curAntPosType;
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
u4Byte nArpCnt;
u1Byte errorCondition;
} COEX_DM_8723B_1ANT, *PCOEX_DM_8723B_1ANT;
typedef struct _COEX_STA_8723B_1ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bBtHiPriLinkExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte specialPktPeriodCnt;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
s1Byte btRssi;
BOOLEAN bBtTxRxMask;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723B_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723B_1ANT_MAX];
BOOLEAN bBtWhckTest;
BOOLEAN bC2hBtInquiryPage;
BOOLEAN bC2hBtPage; //Add for win8.1 page out issue
BOOLEAN bWiFiIsHighPriTask; //Add for win8.1 page out issue
u1Byte btRetryCnt;
u1Byte btInfoExt;
u4Byte popEventCnt;
u1Byte nScanAPNum;
u4Byte nCRCOK_CCK;
u4Byte nCRCOK_11g;
u4Byte nCRCOK_11n;
u4Byte nCRCOK_11nAgg;
u4Byte nCRCErr_CCK;
u4Byte nCRCErr_11g;
u4Byte nCRCErr_11n;
u4Byte nCRCErr_11nAgg;
BOOLEAN bCCKLock;
BOOLEAN bPreCCKLock;
BOOLEAN bCCKEverLock;
u1Byte nCoexTableType;
BOOLEAN bForceLpsOn;
}COEX_STA_8723B_1ANT, *PCOEX_STA_8723B_1ANT;
#define BT_8723B_1ANT_ANTDET_PSD_POINTS 256 //MAX:1024
#define BT_8723B_1ANT_ANTDET_PSD_AVGNUM 1 //MAX:3
typedef struct _PSDSCAN_STA_8723B_1ANT{
BOOLEAN bIsAntDetEnable;
BOOLEAN bIsAntIsoEnable;
BOOLEAN bIsPSDScanEnable;
u4Byte realcentFreq; //ex:2412
s4Byte realoffset;
u4Byte realspan;
u4Byte realseconds;
BOOLEAN bAntDetFinish;
u1Byte nAntIsolation;
u4Byte nPSDBandWidth; //unit: Hz
u4Byte nPSDPoint; //128/256/512/1024
u4Byte nPSDReport[1024]; //unit:dB (20logx), 0~255
u4Byte nPSDReport_MaxHold[1024]; //unit:dB (20logx), 0~255
u4Byte nPSDStartPoint;
u4Byte nPSDStopPoint;
u4Byte nPSDMaxValuePoint;
u4Byte nPSDMaxValue;
u4Byte nPSDStartBase;
u4Byte nPSDAvgNum; // 1/8/16/32
u4Byte nPSDGenCount;
u4Byte nPSDGenTotalCount;
BOOLEAN bIsSetupFinish;
BOOLEAN bIsPSDRunning;
BOOLEAN bIsPSDShowMaxOnly;
} PSDSCAN_STA_8723B_1ANT, *PPSDSCAN_STA_8723B_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723b1ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_PreLoadFirmware(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8723b1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723b1ant_RfStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8723b1ant_CoexDmReset(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_AntennaDetection(
IN PBTC_COEXIST pBtCoexist,
IN u4Byte centFreq,
IN u4Byte offset,
IN u4Byte span,
IN u4Byte seconds
);
VOID
EXhalbtc8723b1ant_AntennaIsolation(
IN PBTC_COEXIST pBtCoexist,
IN u4Byte centFreq,
IN u4Byte offset,
IN u4Byte span,
IN u4Byte seconds
);
VOID
EXhalbtc8723b1ant_PSDScan(
IN PBTC_COEXIST pBtCoexist,
IN u4Byte centFreq,
IN u4Byte offset,
IN u4Byte span,
IN u4Byte seconds
);
VOID
EXhalbtc8723b1ant_DisplayAntIsolation(
IN PBTC_COEXIST pBtCoexist
);

4894
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8723b2Ant.c
View File

File diff suppressed because it is too large Load Diff

227
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8723b2Ant.h
View File

@ -1,227 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
//===========================================
// The following is for 8723B 2Ant BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8723B_2ANT 1
#define BT_INFO_8723B_2ANT_B_FTP BIT7
#define BT_INFO_8723B_2ANT_B_A2DP BIT6
#define BT_INFO_8723B_2ANT_B_HID BIT5
#define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723B_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT 2
#define BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES 42 //WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation
#define BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES 46 //BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation
typedef enum _BT_INFO_SRC_8723B_2ANT{
BT_INFO_SRC_8723B_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723B_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723B_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723B_2ANT_MAX
}BT_INFO_SRC_8723B_2ANT,*PBT_INFO_SRC_8723B_2ANT;
typedef enum _BT_8723B_2ANT_BT_STATUS{
BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723B_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8723B_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8723B_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8723B_2ANT_BT_STATUS_MAX
}BT_8723B_2ANT_BT_STATUS,*PBT_8723B_2ANT_BT_STATUS;
typedef enum _BT_8723B_2ANT_COEX_ALGO{
BT_8723B_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723B_2ANT_COEX_ALGO_SCO = 0x1,
BT_8723B_2ANT_COEX_ALGO_HID = 0x2,
BT_8723B_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8723B_2ANT_COEX_ALGO_PANEDR = 0x5,
BT_8723B_2ANT_COEX_ALGO_PANHS = 0x6,
BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8723B_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8723B_2ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8723B_2ANT_COEX_ALGO_MAX = 0xb,
}BT_8723B_2ANT_COEX_ALGO,*PBT_8723B_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8723B_2ANT{
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
BOOLEAN bNeedRecover0x948;
u4Byte backup0x948;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
} COEX_DM_8723B_2ANT, *PCOEX_DM_8723B_2ANT;
typedef struct _COEX_STA_8723B_2ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
BOOLEAN bBtTxRxMask;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723B_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723B_2ANT_MAX];
BOOLEAN bBtWhckTest;
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
u4Byte nCRCOK_CCK;
u4Byte nCRCOK_11g;
u4Byte nCRCOK_11n;
u4Byte nCRCOK_11nAgg;
u4Byte nCRCErr_CCK;
u4Byte nCRCErr_11g;
u4Byte nCRCErr_11n;
u4Byte nCRCErr_11nAgg;
u1Byte nCoexTableType;
BOOLEAN bForceLpsOn;
u1Byte disVerInfoCnt;
}COEX_STA_8723B_2ANT, *PCOEX_STA_8723B_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723b2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b2ant_PreLoadFirmware(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8723b2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723b2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b2ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8723b2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

2942
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8812a1Ant.c
View File

File diff suppressed because it is too large Load Diff

207
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8812a1Ant.h
View File

@ -1,207 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
//===========================================
// The following is for 8812A_1ANT BT Co-exist definition
//===========================================
#define BT_INFO_8812A_1ANT_B_FTP BIT7
#define BT_INFO_8812A_1ANT_B_A2DP BIT6
#define BT_INFO_8812A_1ANT_B_HID BIT5
#define BT_INFO_8812A_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8812A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8812A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8812A_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8812A_1ANT_B_CONNECTION BIT0
#define BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT 2
#define BTC_8812A_1ANT_SWITCH_TO_WIFI 0
#define BTC_8812A_1ANT_SWITCH_TO_BT 1
typedef enum _BT_INFO_SRC_8812A_1ANT{
BT_INFO_SRC_8812A_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8812A_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8812A_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8812A_1ANT_MAX
}BT_INFO_SRC_8812A_1ANT,*PBT_INFO_SRC_8812A_1ANT;
typedef enum _BT_8812A_1ANT_BT_STATUS{
BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8812A_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8812A_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8812A_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8812A_1ANT_BT_STATUS_MAX
}BT_8812A_1ANT_BT_STATUS,*PBT_8812A_1ANT_BT_STATUS;
typedef enum _BT_8812A_1ANT_WIFI_STATUS{
BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8812A_1ANT_WIFI_STATUS_MAX
}BT_8812A_1ANT_WIFI_STATUS,*PBT_8812A_1ANT_WIFI_STATUS;
typedef enum _BT_8812A_1ANT_COEX_ALGO{
BT_8812A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8812A_1ANT_COEX_ALGO_SCO = 0x1,
BT_8812A_1ANT_COEX_ALGO_HID = 0x2,
BT_8812A_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8812A_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8812A_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8812A_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8812A_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8812A_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8812A_1ANT_COEX_ALGO,*PBT_8812A_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8812A_1ANT{
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte errorCondition;
} COEX_DM_8812A_1ANT, *PCOEX_DM_8812A_1ANT;
typedef struct _COEX_STA_8812A_1ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8812A_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8812A_1ANT_MAX];
u4Byte btInfoQueryCnt;
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8812A_1ANT, *PCOEX_STA_8812A_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8812a1ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8812a1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8812a1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8812a1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);

4791
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8812a2Ant.c
View File

File diff suppressed because it is too large Load Diff

219
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8812a2Ant.h
View File

@ -1,219 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
//===========================================
// The following is for 8812A 2Ant BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8812A_2ANT 0
#define BT_INFO_8812A_2ANT_B_FTP BIT7
#define BT_INFO_8812A_2ANT_B_A2DP BIT6
#define BT_INFO_8812A_2ANT_B_HID BIT5
#define BT_INFO_8812A_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8812A_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8812A_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8812A_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8812A_2ANT_B_CONNECTION BIT0
#define BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT 2
typedef enum _BT_INFO_SRC_8812A_2ANT{
BT_INFO_SRC_8812A_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8812A_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8812A_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8812A_2ANT_MAX
}BT_INFO_SRC_8812A_2ANT,*PBT_INFO_SRC_8812A_2ANT;
typedef enum _BT_8812A_2ANT_BT_STATUS{
BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8812A_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8812A_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8812A_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8812A_2ANT_BT_STATUS_MAX
}BT_8812A_2ANT_BT_STATUS,*PBT_8812A_2ANT_BT_STATUS;
typedef enum _BT_8812A_2ANT_COEX_ALGO{
BT_8812A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8812A_2ANT_COEX_ALGO_SCO = 0x1,
BT_8812A_2ANT_COEX_ALGO_SCO_HID = 0x2,
BT_8812A_2ANT_COEX_ALGO_HID = 0x3,
BT_8812A_2ANT_COEX_ALGO_A2DP = 0x4,
BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS = 0x5,
BT_8812A_2ANT_COEX_ALGO_PANEDR = 0x6,
BT_8812A_2ANT_COEX_ALGO_PANHS = 0x7,
BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8,
BT_8812A_2ANT_COEX_ALGO_PANEDR_HID = 0x9,
BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa,
BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS = 0xb,
BT_8812A_2ANT_COEX_ALGO_HID_A2DP = 0xc,
BT_8812A_2ANT_COEX_ALGO_MAX = 0xd
}BT_8812A_2ANT_COEX_ALGO,*PBT_8812A_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8812A_2ANT{
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bAutoTdmaAdjustLowRssi;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte curRaMaskType;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
} COEX_DM_8812A_2ANT, *PCOEX_DM_8812A_2ANT;
typedef struct _COEX_STA_8812A_2ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8812A_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8812A_2ANT_MAX];
u4Byte btInfoQueryCnt;
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8812A_2ANT, *PCOEX_STA_8812A_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8812a2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8812a2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8812a2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);

3469
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8821a1Ant.c
View File

File diff suppressed because it is too large Load Diff

214
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8821a1Ant.h
View File

@ -1,214 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
//===========================================
// The following is for 8821A 1ANT BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8821A_1ANT 1
#define BT_INFO_8821A_1ANT_B_FTP BIT7
#define BT_INFO_8821A_1ANT_B_A2DP BIT6
#define BT_INFO_8821A_1ANT_B_HID BIT5
#define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8821A_1ANT_B_CONNECTION BIT0
#define BT_INFO_8821A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT 2
typedef enum _BT_INFO_SRC_8821A_1ANT{
BT_INFO_SRC_8821A_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8821A_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8821A_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8821A_1ANT_MAX
}BT_INFO_SRC_8821A_1ANT,*PBT_INFO_SRC_8821A_1ANT;
typedef enum _BT_8821A_1ANT_BT_STATUS{
BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8821A_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8821A_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8821A_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8821A_1ANT_BT_STATUS_MAX
}BT_8821A_1ANT_BT_STATUS,*PBT_8821A_1ANT_BT_STATUS;
typedef enum _BT_8821A_1ANT_WIFI_STATUS{
BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8821A_1ANT_WIFI_STATUS_MAX
}BT_8821A_1ANT_WIFI_STATUS,*PBT_8821A_1ANT_WIFI_STATUS;
typedef enum _BT_8821A_1ANT_COEX_ALGO{
BT_8821A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8821A_1ANT_COEX_ALGO_SCO = 0x1,
BT_8821A_1ANT_COEX_ALGO_HID = 0x2,
BT_8821A_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8821A_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8821A_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8821A_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8821A_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8821A_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8821A_1ANT_COEX_ALGO,*PBT_8821A_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8821A_1ANT{
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
u4Byte nArpCnt;
u1Byte errorCondition;
} COEX_DM_8821A_1ANT, *PCOEX_DM_8821A_1ANT;
typedef struct _COEX_STA_8821A_1ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte specialPktPeriodCnt;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
BOOLEAN bBtTxRxMask;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8821A_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8821A_1ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
BOOLEAN bC2hBtPage; //Add for win8.1 page out issue
BOOLEAN bWiFiIsHighPriTask; //Add for win8.1 page out issue
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8821A_1ANT, *PCOEX_STA_8821A_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8821a1ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8821a1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8821a1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8821a1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

4102
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8821a2Ant.c
View File

File diff suppressed because it is too large Load Diff

187
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8821a2Ant.h
View File

@ -1,187 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
//===========================================
// The following is for 8821A 2Ant BT Co-exist definition
//===========================================
#define BT_INFO_8821A_2ANT_B_FTP BIT7
#define BT_INFO_8821A_2ANT_B_A2DP BIT6
#define BT_INFO_8821A_2ANT_B_HID BIT5
#define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8821A_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT 2
typedef enum _BT_INFO_SRC_8821A_2ANT{
BT_INFO_SRC_8821A_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8821A_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8821A_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8821A_2ANT_MAX
}BT_INFO_SRC_8821A_2ANT,*PBT_INFO_SRC_8821A_2ANT;
typedef enum _BT_8821A_2ANT_BT_STATUS{
BT_8821A_2ANT_BT_STATUS_IDLE = 0x0,
BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8821A_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8821A_2ANT_BT_STATUS_MAX
}BT_8821A_2ANT_BT_STATUS,*PBT_8821A_2ANT_BT_STATUS;
typedef enum _BT_8821A_2ANT_COEX_ALGO{
BT_8821A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8821A_2ANT_COEX_ALGO_SCO = 0x1,
BT_8821A_2ANT_COEX_ALGO_HID = 0x2,
BT_8821A_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8821A_2ANT_COEX_ALGO_PANEDR = 0x5,
BT_8821A_2ANT_COEX_ALGO_PANHS = 0x6,
BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8821A_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8821A_2ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8821A_2ANT_COEX_ALGO_MAX = 0xb,
}BT_8821A_2ANT_COEX_ALGO,*PBT_8821A_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8821A_2ANT{
// fw mechanism
BOOLEAN bPreDecBtPwr;
BOOLEAN bCurDecBtPwr;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
} COEX_DM_8821A_2ANT, *PCOEX_DM_8821A_2ANT;
typedef struct _COEX_STA_8821A_2ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8821A_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8821A_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8821A_2ANT, *PCOEX_STA_8821A_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8821a2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8821a2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8821a2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8821a2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

4399
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8821aCsr2Ant.c
View File

File diff suppressed because it is too large Load Diff

208
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtc8821aCsr2Ant.h
View File

@ -1,208 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
//===========================================
// The following is for 8821A_CSR 2Ant BT Co-exist definition
//===========================================
#define BT_INFO_8821A_CSR_2ANT_B_FTP BIT7
#define BT_INFO_8821A_CSR_2ANT_B_A2DP BIT6
#define BT_INFO_8821A_CSR_2ANT_B_HID BIT5
#define BT_INFO_8821A_CSR_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8821A_CSR_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8821A_CSR_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_CSR_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8821A_CSR_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT 2
typedef enum _BT_INFO_SRC_8821A_CSR_2ANT{
BT_INFO_SRC_8821A_CSR_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8821A_CSR_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8821A_CSR_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8821A_CSR_2ANT_MAX
}BT_INFO_SRC_8821A_CSR_2ANT,*PBT_INFO_SRC_8821A_CSR_2ANT;
typedef enum _BT_8821A_CSR_2ANT_BT_STATUS{
BT_8821A_CSR_2ANT_BT_STATUS_IDLE = 0x0,
BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8821A_CSR_2ANT_BT_STATUS_MAX
}BT_8821A_CSR_2ANT_BT_STATUS,*PBT_8821A_CSR_2ANT_BT_STATUS;
typedef enum _BT_8821A_CSR_2ANT_COEX_ALGO{
BT_8821A_CSR_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8821A_CSR_2ANT_COEX_ALGO_SCO = 0x1,
BT_8821A_CSR_2ANT_COEX_ALGO_HID = 0x2,
BT_8821A_CSR_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8821A_CSR_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR = 0x5,
BT_8821A_CSR_2ANT_COEX_ALGO_PANHS = 0x6,
BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8821A_CSR_2ANT_COEX_ALGO_MAX = 0xb,
}BT_8821A_CSR_2ANT_COEX_ALGO,*PBT_8821A_CSR_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8821A_CSR_2ANT{
// fw mechanism
BOOLEAN bPreDecBtPwr;
BOOLEAN bCurDecBtPwr;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[6];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte curAmpduNumType;
u1Byte preAmpduNumType;
u2Byte backupAmpduMaxNum;
u1Byte curAmpduTimeType;
u1Byte preAmpduTimeType;
u1Byte backupAmpduMaxTime;
u1Byte curArfrType;
u1Byte preArfrType;
u4Byte backupArfrCnt1;
u4Byte backupArfrCnt2;
u1Byte curRetryLimitType;
u1Byte preRetryLimitType;
u2Byte backupRetryLimit;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
} COEX_DM_8821A_CSR_2ANT, *PCOEX_DM_8821A_CSR_2ANT;
typedef struct _COEX_STA_8821A_CSR_2ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bSlave;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8821A_CSR_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8821A_CSR_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8821A_CSR_2ANT, *PCOEX_STA_8821A_CSR_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8821aCsr2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821aCsr2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8821aCsr2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821aCsr2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8821aCsr2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821aCsr2ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8821aCsr2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821aCsr2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

778
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/HalBtcOutSrc.h
View File

@ -1,778 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __HALBTC_OUT_SRC_H__
#define __HALBTC_OUT_SRC_H__
#define NORMAL_EXEC FALSE
#define FORCE_EXEC TRUE
#define BTC_RF_OFF 0x0
#define BTC_RF_ON 0x1
#define BTC_RF_A 0x0
#define BTC_RF_B 0x1
#define BTC_RF_C 0x2
#define BTC_RF_D 0x3
#define BTC_SMSP SINGLEMAC_SINGLEPHY
#define BTC_DMDP DUALMAC_DUALPHY
#define BTC_DMSP DUALMAC_SINGLEPHY
#define BTC_MP_UNKNOWN 0xff
#define BT_COEX_ANT_TYPE_PG 0
#define BT_COEX_ANT_TYPE_ANTDIV 1
#define BT_COEX_ANT_TYPE_DETECTED 2
#define BTC_MIMO_PS_STATIC 0 // 1ss
#define BTC_MIMO_PS_DYNAMIC 1 // 2ss
#define BTC_RATE_DISABLE 0
#define BTC_RATE_ENABLE 1
// single Antenna definition
#define BTC_ANT_PATH_WIFI 0
#define BTC_ANT_PATH_BT 1
#define BTC_ANT_PATH_PTA 2
// dual Antenna definition
#define BTC_ANT_WIFI_AT_MAIN 0
#define BTC_ANT_WIFI_AT_AUX 1
// coupler Antenna definition
#define BTC_ANT_WIFI_AT_CPL_MAIN 0
#define BTC_ANT_WIFI_AT_CPL_AUX 1
typedef enum _BTC_POWERSAVE_TYPE{
BTC_PS_WIFI_NATIVE = 0, // wifi original power save behavior
BTC_PS_LPS_ON = 1,
BTC_PS_LPS_OFF = 2,
BTC_PS_MAX
} BTC_POWERSAVE_TYPE, *PBTC_POWERSAVE_TYPE;
typedef enum _BTC_BT_REG_TYPE{
BTC_BT_REG_RF = 0,
BTC_BT_REG_MODEM = 1,
BTC_BT_REG_BLUEWIZE = 2,
BTC_BT_REG_VENDOR = 3,
BTC_BT_REG_LE = 4,
BTC_BT_REG_MAX
} BTC_BT_REG_TYPE, *PBTC_BT_REG_TYPE;
typedef enum _BTC_CHIP_INTERFACE{
BTC_INTF_UNKNOWN = 0,
BTC_INTF_PCI = 1,
BTC_INTF_USB = 2,
BTC_INTF_SDIO = 3,
BTC_INTF_MAX
} BTC_CHIP_INTERFACE, *PBTC_CHIP_INTERFACE;
typedef enum _BTC_CHIP_TYPE{
BTC_CHIP_UNDEF = 0,
BTC_CHIP_CSR_BC4 = 1,
BTC_CHIP_CSR_BC8 = 2,
BTC_CHIP_RTL8723A = 3,
BTC_CHIP_RTL8821 = 4,
BTC_CHIP_RTL8723B = 5,
BTC_CHIP_MAX
} BTC_CHIP_TYPE, *PBTC_CHIP_TYPE;
typedef enum _BTC_MSG_TYPE{
BTC_MSG_INTERFACE = 0x0,
BTC_MSG_ALGORITHM = 0x1,
BTC_MSG_MAX
}BTC_MSG_TYPE;
extern u4Byte GLBtcDbgType[];
// following is for BTC_MSG_INTERFACE
#define INTF_INIT BIT0
#define INTF_NOTIFY BIT2
// following is for BTC_ALGORITHM
#define ALGO_BT_RSSI_STATE BIT0
#define ALGO_WIFI_RSSI_STATE BIT1
#define ALGO_BT_MONITOR BIT2
#define ALGO_TRACE BIT3
#define ALGO_TRACE_FW BIT4
#define ALGO_TRACE_FW_DETAIL BIT5
#define ALGO_TRACE_FW_EXEC BIT6
#define ALGO_TRACE_SW BIT7
#define ALGO_TRACE_SW_DETAIL BIT8
#define ALGO_TRACE_SW_EXEC BIT9
// following is for wifi link status
#define WIFI_STA_CONNECTED BIT0
#define WIFI_AP_CONNECTED BIT1
#define WIFI_HS_CONNECTED BIT2
#define WIFI_P2P_GO_CONNECTED BIT3
#define WIFI_P2P_GC_CONNECTED BIT4
// following is for command line utility
#define CL_SPRINTF rsprintf
#define CL_PRINTF DCMD_Printf
// The following is for dbgview print
#if DBG
#define BTC_PRINT(dbgtype, dbgflag, printstr)\
{\
if (GLBtcDbgType[dbgtype] & dbgflag)\
{\
DbgPrint printstr;\
}\
}
#define BTC_PRINT_F(dbgtype, dbgflag, printstr)\
{\
if (GLBtcDbgType[dbgtype] & dbgflag)\
{\
DbgPrint("%s(): ", __FUNCTION__);\
DbgPrint printstr;\
}\
}
#define BTC_PRINT_ADDR(dbgtype, dbgflag, printstr, _Ptr)\
{\
if (GLBtcDbgType[dbgtype] & dbgflag)\
{\
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint printstr; \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}\
}
#define BTC_PRINT_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)\
{\
if (GLBtcDbgType[dbgtype] & dbgflag)\
{\
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" ");\
if (((__i + 1) % 16) == 0) DbgPrint("\n");\
} \
DbgPrint("\n"); \
}\
}
#else
#define BTC_PRINT(dbgtype, dbgflag, printstr)
#define BTC_PRINT_F(dbgtype, dbgflag, printstr)
#define BTC_PRINT_ADDR(dbgtype, dbgflag, printstr, _Ptr)
#define BTC_PRINT_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)
#endif
typedef struct _BTC_BOARD_INFO{
// The following is some board information
u1Byte btChipType;
u1Byte pgAntNum; // pg ant number
u1Byte btdmAntNum; // ant number for btdm
u1Byte btdmAntPos; //Bryant Add to indicate Antenna Position for (pgAntNum = 2) && (btdmAntNum =1) (DPDT+1Ant case)
u1Byte singleAntPath; // current used for 8723b only, 1=>s0, 0=>s1
//BOOLEAN bBtExist;
} BTC_BOARD_INFO, *PBTC_BOARD_INFO;
typedef enum _BTC_DBG_OPCODE{
BTC_DBG_SET_COEX_NORMAL = 0x0,
BTC_DBG_SET_COEX_WIFI_ONLY = 0x1,
BTC_DBG_SET_COEX_BT_ONLY = 0x2,
BTC_DBG_SET_COEX_DEC_BT_PWR = 0x3,
BTC_DBG_SET_COEX_BT_AFH_MAP = 0x4,
BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT = 0x5,
BTC_DBG_MAX
}BTC_DBG_OPCODE,*PBTC_DBG_OPCODE;
typedef enum _BTC_RSSI_STATE{
BTC_RSSI_STATE_HIGH = 0x0,
BTC_RSSI_STATE_MEDIUM = 0x1,
BTC_RSSI_STATE_LOW = 0x2,
BTC_RSSI_STATE_STAY_HIGH = 0x3,
BTC_RSSI_STATE_STAY_MEDIUM = 0x4,
BTC_RSSI_STATE_STAY_LOW = 0x5,
BTC_RSSI_MAX
}BTC_RSSI_STATE,*PBTC_RSSI_STATE;
#define BTC_RSSI_HIGH(_rssi_) ((_rssi_==BTC_RSSI_STATE_HIGH||_rssi_==BTC_RSSI_STATE_STAY_HIGH)? TRUE:FALSE)
#define BTC_RSSI_MEDIUM(_rssi_) ((_rssi_==BTC_RSSI_STATE_MEDIUM||_rssi_==BTC_RSSI_STATE_STAY_MEDIUM)? TRUE:FALSE)
#define BTC_RSSI_LOW(_rssi_) ((_rssi_==BTC_RSSI_STATE_LOW||_rssi_==BTC_RSSI_STATE_STAY_LOW)? TRUE:FALSE)
typedef enum _BTC_WIFI_ROLE{
BTC_ROLE_STATION = 0x0,
BTC_ROLE_AP = 0x1,
BTC_ROLE_IBSS = 0x2,
BTC_ROLE_HS_MODE = 0x3,
BTC_ROLE_MAX
}BTC_WIFI_ROLE,*PBTC_WIFI_ROLE;
typedef enum _BTC_WIRELESS_FREQ{
BTC_FREQ_2_4G = 0x0,
BTC_FREQ_5G = 0x1,
BTC_FREQ_MAX
}BTC_WIRELESS_FREQ,*PBTC_WIRELESS_FREQ;
typedef enum _BTC_WIFI_BW_MODE{
BTC_WIFI_BW_LEGACY = 0x0,
BTC_WIFI_BW_HT20 = 0x1,
BTC_WIFI_BW_HT40 = 0x2,
BTC_WIFI_BW_HT80 = 0x3,
BTC_WIFI_BW_HT160 = 0x4,
BTC_WIFI_BW_MAX
}BTC_WIFI_BW_MODE,*PBTC_WIFI_BW_MODE;
typedef enum _BTC_WIFI_TRAFFIC_DIR{
BTC_WIFI_TRAFFIC_TX = 0x0,
BTC_WIFI_TRAFFIC_RX = 0x1,
BTC_WIFI_TRAFFIC_MAX
}BTC_WIFI_TRAFFIC_DIR,*PBTC_WIFI_TRAFFIC_DIR;
typedef enum _BTC_WIFI_PNP{
BTC_WIFI_PNP_WAKE_UP = 0x0,
BTC_WIFI_PNP_SLEEP = 0x1,
BTC_WIFI_PNP_MAX
}BTC_WIFI_PNP,*PBTC_WIFI_PNP;
//for 8723b-d cut large current issue
typedef enum _BT_WIFI_COEX_STATE{
BTC_WIFI_STAT_INIT,
BTC_WIFI_STAT_IQK,
BTC_WIFI_STAT_NORMAL_OFF,
BTC_WIFI_STAT_MP_OFF,
BTC_WIFI_STAT_NORMAL,
BTC_WIFI_STAT_ANT_DIV,
BTC_WIFI_STAT_MAX
}BT_WIFI_COEX_STATE,*PBT_WIFI_COEX_STATE;
typedef enum _BT_ANT_TYPE{
BTC_ANT_TYPE_0,
BTC_ANT_TYPE_1,
BTC_ANT_TYPE_2,
BTC_ANT_TYPE_3,
BTC_ANT_TYPE_4,
BTC_ANT_TYPE_MAX
}BT_ANT_TYPE,*PBT_ANT_TYPE;
// defined for BFP_BTC_GET
typedef enum _BTC_GET_TYPE{
// type BOOLEAN
BTC_GET_BL_HS_OPERATION,
BTC_GET_BL_HS_CONNECTING,
BTC_GET_BL_WIFI_CONNECTED,
BTC_GET_BL_WIFI_BUSY,
BTC_GET_BL_WIFI_SCAN,
BTC_GET_BL_WIFI_LINK,
BTC_GET_BL_WIFI_ROAM,
BTC_GET_BL_WIFI_4_WAY_PROGRESS,
BTC_GET_BL_WIFI_UNDER_5G,
BTC_GET_BL_WIFI_AP_MODE_ENABLE,
BTC_GET_BL_WIFI_ENABLE_ENCRYPTION,
BTC_GET_BL_WIFI_UNDER_B_MODE,
BTC_GET_BL_EXT_SWITCH,
BTC_GET_BL_WIFI_IS_IN_MP_MODE,
BTC_GET_BL_IS_ASUS_8723B,
// type s4Byte
BTC_GET_S4_WIFI_RSSI,
BTC_GET_S4_HS_RSSI,
// type u4Byte
BTC_GET_U4_WIFI_BW,
BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
BTC_GET_U4_WIFI_FW_VER,
BTC_GET_U4_WIFI_LINK_STATUS,
BTC_GET_U4_BT_PATCH_VER,
// type u1Byte
BTC_GET_U1_WIFI_DOT11_CHNL,
BTC_GET_U1_WIFI_CENTRAL_CHNL,
BTC_GET_U1_WIFI_HS_CHNL,
BTC_GET_U1_MAC_PHY_MODE,
BTC_GET_U1_AP_NUM,
BTC_GET_U1_ANT_TYPE,
//===== for 1Ant ======
BTC_GET_U1_LPS_MODE,
BTC_GET_MAX
}BTC_GET_TYPE,*PBTC_GET_TYPE;
// defined for BFP_BTC_SET
typedef enum _BTC_SET_TYPE{
// type BOOLEAN
BTC_SET_BL_BT_DISABLE,
BTC_SET_BL_BT_TRAFFIC_BUSY,
BTC_SET_BL_BT_LIMITED_DIG,
BTC_SET_BL_FORCE_TO_ROAM,
BTC_SET_BL_TO_REJ_AP_AGG_PKT,
BTC_SET_BL_BT_CTRL_AGG_SIZE,
BTC_SET_BL_INC_SCAN_DEV_NUM,
BTC_SET_BL_BT_TX_RX_MASK,
BTC_SET_BL_MIRACAST_PLUS_BT,
// type u1Byte
BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
BTC_SET_U1_AGG_BUF_SIZE,
// type trigger some action
BTC_SET_ACT_GET_BT_RSSI,
BTC_SET_ACT_AGGREGATE_CTRL,
//===== for 1Ant ======
// type BOOLEAN
// type u1Byte
BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE,
BTC_SET_U1_LPS_VAL,
BTC_SET_U1_RPWM_VAL,
// type trigger some action
BTC_SET_ACT_LEAVE_LPS,
BTC_SET_ACT_ENTER_LPS,
BTC_SET_ACT_NORMAL_LPS,
BTC_SET_ACT_DISABLE_LOW_POWER,
BTC_SET_ACT_UPDATE_RAMASK,
BTC_SET_ACT_SEND_MIMO_PS,
// BT Coex related
BTC_SET_ACT_CTRL_BT_INFO,
BTC_SET_ACT_CTRL_BT_COEX,
BTC_SET_ACT_CTRL_8723B_ANT,
//=================
BTC_SET_MAX
}BTC_SET_TYPE,*PBTC_SET_TYPE;
typedef enum _BTC_DBG_DISP_TYPE{
BTC_DBG_DISP_COEX_STATISTICS = 0x0,
BTC_DBG_DISP_BT_LINK_INFO = 0x1,
BTC_DBG_DISP_WIFI_STATUS = 0x2,
BTC_DBG_DISP_MAX
}BTC_DBG_DISP_TYPE,*PBTC_DBG_DISP_TYPE;
typedef enum _BTC_NOTIFY_TYPE_IPS{
BTC_IPS_LEAVE = 0x0,
BTC_IPS_ENTER = 0x1,
BTC_IPS_MAX
}BTC_NOTIFY_TYPE_IPS,*PBTC_NOTIFY_TYPE_IPS;
typedef enum _BTC_NOTIFY_TYPE_LPS{
BTC_LPS_DISABLE = 0x0,
BTC_LPS_ENABLE = 0x1,
BTC_LPS_MAX
}BTC_NOTIFY_TYPE_LPS,*PBTC_NOTIFY_TYPE_LPS;
typedef enum _BTC_NOTIFY_TYPE_SCAN{
BTC_SCAN_FINISH = 0x0,
BTC_SCAN_START = 0x1,
BTC_SCAN_MAX
}BTC_NOTIFY_TYPE_SCAN,*PBTC_NOTIFY_TYPE_SCAN;
typedef enum _BTC_NOTIFY_TYPE_ASSOCIATE{
BTC_ASSOCIATE_FINISH = 0x0,
BTC_ASSOCIATE_START = 0x1,
BTC_ASSOCIATE_MAX
}BTC_NOTIFY_TYPE_ASSOCIATE,*PBTC_NOTIFY_TYPE_ASSOCIATE;
typedef enum _BTC_NOTIFY_TYPE_MEDIA_STATUS{
BTC_MEDIA_DISCONNECT = 0x0,
BTC_MEDIA_CONNECT = 0x1,
BTC_MEDIA_MAX
}BTC_NOTIFY_TYPE_MEDIA_STATUS,*PBTC_NOTIFY_TYPE_MEDIA_STATUS;
typedef enum _BTC_NOTIFY_TYPE_SPECIAL_PACKET{
BTC_PACKET_UNKNOWN = 0x0,
BTC_PACKET_DHCP = 0x1,
BTC_PACKET_ARP = 0x2,
BTC_PACKET_EAPOL = 0x3,
BTC_PACKET_MAX
}BTC_NOTIFY_TYPE_SPECIAL_PACKET,*PBTC_NOTIFY_TYPE_SPECIAL_PACKET;
typedef enum _BTC_NOTIFY_TYPE_STACK_OPERATION{
BTC_STACK_OP_NONE = 0x0,
BTC_STACK_OP_INQ_PAGE_PAIR_START = 0x1,
BTC_STACK_OP_INQ_PAGE_PAIR_FINISH = 0x2,
BTC_STACK_OP_MAX
}BTC_NOTIFY_TYPE_STACK_OPERATION,*PBTC_NOTIFY_TYPE_STACK_OPERATION;
//Bryant Add
typedef enum _BTC_ANTENNA_POS{
BTC_ANTENNA_AT_MAIN_PORT = 0x1,
BTC_ANTENNA_AT_AUX_PORT = 0x2,
}BTC_ANTENNA_POS,*PBTC_ANTENNA_POS;
typedef u1Byte
(*BFP_BTC_R1)(
IN PVOID pBtcContext,
IN u4Byte RegAddr
);
typedef u2Byte
(*BFP_BTC_R2)(
IN PVOID pBtcContext,
IN u4Byte RegAddr
);
typedef u4Byte
(*BFP_BTC_R4)(
IN PVOID pBtcContext,
IN u4Byte RegAddr
);
typedef VOID
(*BFP_BTC_W1)(
IN PVOID pBtcContext,
IN u4Byte RegAddr,
IN u1Byte Data
);
typedef VOID
(*BFP_BTC_W1_BIT_MASK)(
IN PVOID pBtcContext,
IN u4Byte regAddr,
IN u1Byte bitMask,
IN u1Byte data1b
);
typedef VOID
(*BFP_BTC_W2)(
IN PVOID pBtcContext,
IN u4Byte RegAddr,
IN u2Byte Data
);
typedef VOID
(*BFP_BTC_W4)(
IN PVOID pBtcContext,
IN u4Byte RegAddr,
IN u4Byte Data
);
typedef VOID
(*BFP_BTC_LOCAL_REG_W1)(
IN PVOID pBtcContext,
IN u4Byte RegAddr,
IN u1Byte Data
);
typedef VOID
(*BFP_BTC_SET_BB_REG)(
IN PVOID pBtcContext,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
typedef u4Byte
(*BFP_BTC_GET_BB_REG)(
IN PVOID pBtcContext,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
typedef VOID
(*BFP_BTC_SET_RF_REG)(
IN PVOID pBtcContext,
IN u1Byte eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
typedef u4Byte
(*BFP_BTC_GET_RF_REG)(
IN PVOID pBtcContext,
IN u1Byte eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
typedef VOID
(*BFP_BTC_FILL_H2C)(
IN PVOID pBtcContext,
IN u1Byte elementId,
IN u4Byte cmdLen,
IN pu1Byte pCmdBuffer
);
typedef BOOLEAN
(*BFP_BTC_GET)(
IN PVOID pBtCoexist,
IN u1Byte getType,
OUT PVOID pOutBuf
);
typedef BOOLEAN
(*BFP_BTC_SET)(
IN PVOID pBtCoexist,
IN u1Byte setType,
OUT PVOID pInBuf
);
typedef VOID
(*BFP_BTC_SET_BT_REG)(
IN PVOID pBtcContext,
IN u1Byte regType,
IN u4Byte offset,
IN u4Byte value
);
typedef u4Byte
(*BFP_BTC_GET_BT_REG)(
IN PVOID pBtcContext,
IN u1Byte regType,
IN u4Byte offset
);
typedef VOID
(*BFP_BTC_DISP_DBG_MSG)(
IN PVOID pBtCoexist,
IN u1Byte dispType
);
typedef struct _BTC_BT_INFO{
BOOLEAN bBtDisabled;
u1Byte rssiAdjustForAgcTableOn;
u1Byte rssiAdjustFor1AntCoexType;
BOOLEAN bPreBtCtrlAggBufSize;
BOOLEAN bBtCtrlAggBufSize;
BOOLEAN bPreRejectAggPkt;
BOOLEAN bRejectAggPkt;
BOOLEAN bIncreaseScanDevNum;
BOOLEAN bBtTxRxMask;
u1Byte preAggBufSize;
u1Byte aggBufSize;
BOOLEAN bBtBusy;
BOOLEAN bLimitedDig;
u2Byte btHciVer;
u2Byte btRealFwVer;
u1Byte btFwVer;
u4Byte getBtFwVerCnt;
BOOLEAN bMiracastPlusBt;
BOOLEAN bBtDisableLowPwr;
BOOLEAN bBtCtrlLps;
BOOLEAN bBtLpsOn;
BOOLEAN bForceToRoam; // for 1Ant solution
u1Byte lpsVal;
u1Byte rpwmVal;
u4Byte raMask;
} BTC_BT_INFO, *PBTC_BT_INFO;
typedef struct _BTC_STACK_INFO{
BOOLEAN bProfileNotified;
u2Byte hciVersion; // stack hci version
u1Byte numOfLink;
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bAclExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
u1Byte numOfHid;
BOOLEAN bPanExist;
BOOLEAN bUnknownAclExist;
s1Byte minBtRssi;
} BTC_STACK_INFO, *PBTC_STACK_INFO;
typedef struct _BTC_BT_LINK_INFO{
BOOLEAN bBtLinkExist;
BOOLEAN bBtHiPriLinkExist;
BOOLEAN bScoExist;
BOOLEAN bScoOnly;
BOOLEAN bA2dpExist;
BOOLEAN bA2dpOnly;
BOOLEAN bHidExist;
BOOLEAN bHidOnly;
BOOLEAN bPanExist;
BOOLEAN bPanOnly;
BOOLEAN bSlaveRole;
BOOLEAN bAclBusy;
} BTC_BT_LINK_INFO, *PBTC_BT_LINK_INFO;
typedef struct _BTC_STATISTICS{
u4Byte cntBind;
u4Byte cntPowerOn;
u4Byte cntPreLoadFirmware;
u4Byte cntInitHwConfig;
u4Byte cntInitCoexDm;
u4Byte cntIpsNotify;
u4Byte cntLpsNotify;
u4Byte cntScanNotify;
u4Byte cntConnectNotify;
u4Byte cntMediaStatusNotify;
u4Byte cntSpecialPacketNotify;
u4Byte cntBtInfoNotify;
u4Byte cntRfStatusNotify;
u4Byte cntPeriodical;
u4Byte cntCoexDmSwitch;
u4Byte cntStackOperationNotify;
u4Byte cntDbgCtrl;
} BTC_STATISTICS, *PBTC_STATISTICS;
typedef struct _BTC_COEXIST{
BOOLEAN bBinded; // make sure only one adapter can bind the data context
PVOID Adapter; // default adapter
BTC_BOARD_INFO boardInfo;
BTC_BT_INFO btInfo; // some bt info referenced by non-bt module
BTC_STACK_INFO stackInfo;
BTC_BT_LINK_INFO btLinkInfo;
BTC_CHIP_INTERFACE chipInterface;
BOOLEAN bInitilized;
BOOLEAN bStopCoexDm;
BOOLEAN bManualControl;
pu1Byte cliBuf;
BTC_STATISTICS statistics;
u1Byte pwrModeVal[10];
// function pointers
// io related
BFP_BTC_R1 fBtcRead1Byte;
BFP_BTC_W1 fBtcWrite1Byte;
BFP_BTC_W1_BIT_MASK fBtcWrite1ByteBitMask;
BFP_BTC_R2 fBtcRead2Byte;
BFP_BTC_W2 fBtcWrite2Byte;
BFP_BTC_R4 fBtcRead4Byte;
BFP_BTC_W4 fBtcWrite4Byte;
BFP_BTC_LOCAL_REG_W1 fBtcWriteLocalReg1Byte;
// read/write bb related
BFP_BTC_SET_BB_REG fBtcSetBbReg;
BFP_BTC_GET_BB_REG fBtcGetBbReg;
// read/write rf related
BFP_BTC_SET_RF_REG fBtcSetRfReg;
BFP_BTC_GET_RF_REG fBtcGetRfReg;
// fill h2c related
BFP_BTC_FILL_H2C fBtcFillH2c;
// other
BFP_BTC_DISP_DBG_MSG fBtcDispDbgMsg;
// normal get/set related
BFP_BTC_GET fBtcGet;
BFP_BTC_SET fBtcSet;
BFP_BTC_GET_BT_REG fBtcGetBtReg;
BFP_BTC_SET_BT_REG fBtcSetBtReg;
} BTC_COEXIST, *PBTC_COEXIST;
extern BTC_COEXIST GLBtCoexist;
BOOLEAN
EXhalbtcoutsrc_InitlizeVariables(
IN PVOID Adapter
);
VOID
EXhalbtcoutsrc_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtcoutsrc_PreLoadFirmware(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtcoutsrc_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtcoutsrc_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtcoutsrc_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtcoutsrc_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtcoutsrc_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtcoutsrc_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte action
);
VOID
EXhalbtcoutsrc_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN RT_MEDIA_STATUS mediaStatus
);
VOID
EXhalbtcoutsrc_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pktType
);
VOID
EXhalbtcoutsrc_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtcoutsrc_RfStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtcoutsrc_StackOperationNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtcoutsrc_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtcoutsrc_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtcoutsrc_CoexDmSwitch(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtcoutsrc_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtcoutsrc_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);
VOID
EXhalbtcoutsrc_AntennaDetection(
IN PBTC_COEXIST pBtCoexist,
IN u4Byte centFreq,
IN u4Byte offset,
IN u4Byte span,
IN u4Byte seconds
);
VOID
EXhalbtcoutsrc_StackUpdateProfileInfo(
VOID
);
VOID
EXhalbtcoutsrc_SetHciVersion(
IN u2Byte hciVersion
);
VOID
EXhalbtcoutsrc_SetBtPatchVersion(
IN u2Byte btHciVersion,
IN u2Byte btPatchVersion
);
VOID
EXhalbtcoutsrc_UpdateMinBtRssi(
IN s1Byte btRssi
);
#if 0
VOID
EXhalbtcoutsrc_SetBtExist(
IN BOOLEAN bBtExist
);
#endif
VOID
EXhalbtcoutsrc_SetChipType(
IN u1Byte chipType
);
VOID
EXhalbtcoutsrc_SetAntNum(
IN u1Byte type,
IN u1Byte antNum
);
VOID
EXhalbtcoutsrc_SetSingleAntPath(
IN u1Byte singleAntPath
);
VOID
EXhalbtcoutsrc_DisplayBtCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtcoutsrc_DisplayAntIsolation(
IN PBTC_COEXIST pBtCoexist
);
#endif

57
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC-BTCoexist/Mp_Precomp.h
View File

@ -1,57 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2013 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __MP_PRECOMP_H__
#define __MP_PRECOMP_H__
#include <drv_types.h>
#include <hal_data.h>
#define BT_TMP_BUF_SIZE 100
#ifdef PLATFORM_LINUX
#define rsprintf snprintf
#elif defined(PLATFORM_WINDOWS)
#define rsprintf sprintf_s
#endif
#define DCMD_Printf DBG_BT_INFO
#define delay_ms(ms) rtw_mdelay_os(ms)
#ifdef bEnable
#undef bEnable
#endif
#include "HalBtcOutSrc.h"
#include "HalBtc8188c2Ant.h"
#include "HalBtc8192d2Ant.h"
#include "HalBtc8192e1Ant.h"
#include "HalBtc8192e2Ant.h"
#include "HalBtc8723a1Ant.h"
#include "HalBtc8723a2Ant.h"
#include "HalBtc8723b1Ant.h"
#include "HalBtc8723b2Ant.h"
#include "HalBtc8812a1Ant.h"
#include "HalBtc8812a2Ant.h"
#include "HalBtc8821a1Ant.h"
#include "HalBtc8821a2Ant.h"
#include "HalBtc8821aCsr2Ant.h"
#endif // __MP_PRECOMP_H__

530
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/HalPhyRf.c
View File

@ -1,530 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \
do {\
for(_offset = 0; _offset < _size; _offset++)\
{\
if(_deltaThermal < thermalThreshold[_direction][_offset])\
{\
if(_offset != 0)\
_offset--;\
break;\
}\
} \
if(_offset >= _size)\
_offset = _size-1;\
} while(0)
void ConfigureTxpowerTrack(
IN PDM_ODM_T pDM_Odm,
OUT PTXPWRTRACK_CFG pConfig
)
{
#if RTL8192E_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8192E)
ConfigureTxpowerTrack_8192E(pConfig);
#endif
#if RTL8821A_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8821)
ConfigureTxpowerTrack_8821A(pConfig);
#endif
#if RTL8812A_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8812)
ConfigureTxpowerTrack_8812A(pConfig);
#endif
#if RTL8188E_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8188E)
ConfigureTxpowerTrack_8188E(pConfig);
#endif
#if RTL8723B_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8723B)
ConfigureTxpowerTrack_8723B(pConfig);
#endif
}
//======================================================================
// <20121113, Kordan> This function should be called when TxAGC changed.
// Otherwise the previous compensation is gone, because we record the
// delta of temperature between two TxPowerTracking watch dogs.
//
// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
// need to call this function.
//======================================================================
VOID
ODM_ClearTxPowerTrackingState(
IN PDM_ODM_T pDM_Odm
)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
u1Byte p = 0;
pDM_Odm->BbSwingIdxCckBase = pDM_Odm->DefaultCckIndex;
pDM_Odm->BbSwingIdxCck = pDM_Odm->DefaultCckIndex;
pDM_Odm->RFCalibrateInfo.CCK_index = 0;
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p)
{
pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->DefaultOfdmIndex;
pDM_Odm->BbSwingIdxOfdm[p] = pDM_Odm->DefaultOfdmIndex;
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pDM_Odm->DefaultOfdmIndex;
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = 0;
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p] = 0;
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
pDM_Odm->Absolute_OFDMSwingIdx[p] = 0; // Initial Mix mode power tracking
pDM_Odm->Remnant_OFDMSwingIdx[p] = 0;
}
pDM_Odm->Modify_TxAGC_Flag_PathA= FALSE; //Initial at Modify Tx Scaling Mode
pDM_Odm->Modify_TxAGC_Flag_PathB= FALSE; //Initial at Modify Tx Scaling Mode
pDM_Odm->Remnant_CCKSwingIdx= 0;
pDM_Odm->RFCalibrateInfo.ThermalValue = pHalData->EEPROMThermalMeter;
pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = pHalData->EEPROMThermalMeter;
pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = pHalData->EEPROMThermalMeter;
}
VOID
ODM_TXPowerTrackingCallback_ThermalMeter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER Adapter
#endif
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
#endif
#endif
u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
u1Byte ThermalValue_AVG_count = 0;
u4Byte ThermalValue_AVG = 0;
u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur
u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel)
TXPWRTRACK_CFG c;
//4 1. The following TWO tables decide the final index of OFDM/CCK swing table.
pu1Byte deltaSwingTableIdx_TUP_A;
pu1Byte deltaSwingTableIdx_TDOWN_A;
pu1Byte deltaSwingTableIdx_TUP_B;
pu1Byte deltaSwingTableIdx_TDOWN_B;
//4 2. Initilization ( 7 steps in total )
ConfigureTxpowerTrack(pDM_Odm, &c);
(*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_A, (pu1Byte*)&deltaSwingTableIdx_TDOWN_A,
(pu1Byte*)&deltaSwingTableIdx_TUP_B, (pu1Byte*)&deltaSwingTableIdx_TDOWN_B);
pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; //cosa add for debug
pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = TRUE;
#if (MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = pHalData->TxPowerTrackControl; // <Kordan> We should keep updating the control variable according to HalData.
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
if (pDM_Odm->mp_mode == TRUE)
#endif
// <Kordan> RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files.
pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317;
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("===>ODM_TXPowerTrackingCallback_ThermalMeter, \
\n pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase[A]: %d, pDM_Odm->DefaultOfdmIndex: %d\n",
pDM_Odm->BbSwingIdxCckBase, pDM_Odm->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pDM_Odm->DefaultOfdmIndex));
ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E
if( ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl || pHalData->EEPROMThermalMeter == 0 ||
pHalData->EEPROMThermalMeter == 0xFF)
return;
//4 3. Initialize ThermalValues of RFCalibrateInfo
if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n"));
}
//4 4. Calculate average thermal meter
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue;
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++;
if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) //Average times = c.AverageThermalNum
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0;
for(i = 0; i < c.AverageThermalNum; i++)
{
if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i])
{
ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i];
ThermalValue_AVG_count++;
}
}
if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times
{
ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter));
}
//4 5. Calculate delta, delta_LCK, delta_IQK.
//"delta" here is used to determine whether thermal value changes or not.
delta = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue):(pDM_Odm->RFCalibrateInfo.ThermalValue - ThermalValue);
delta_LCK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_LCK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK):(pDM_Odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue);
delta_IQK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK):(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK));
//4 6. If necessary, do LCK.
if ((delta_LCK >= c.Threshold_IQK)) // Delta temperature is equal to or larger than 20 centigrade.
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK));
pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue;
if(c.PHY_LCCalibrate)
(*c.PHY_LCCalibrate)(pDM_Odm);
}
//3 7. If necessary, move the index of swing table to adjust Tx power.
if (delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
{
//"delta" here is used to record the absolute value of differrence.
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
#else
delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue);
#endif
if (delta >= TXPWR_TRACK_TABLE_SIZE)
delta = TXPWR_TRACK_TABLE_SIZE - 1;
//4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(ThermalValue > pHalData->EEPROMThermalMeter) {
#else
if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) {
#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta]));
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_A] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A];
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A] = deltaSwingTableIdx_TUP_A[delta];
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = deltaSwingTableIdx_TUP_A[delta]; // Record delta swing for mix mode power tracking
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A]));
if(c.RfPathCount > 1)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta]));
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_B] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B];
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B] = deltaSwingTableIdx_TUP_B[delta];
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = deltaSwingTableIdx_TUP_B[delta]; // Record delta swing for mix mode power tracking
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B]));
}
}
else {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta]));
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_A] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A];
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A] = -1 * deltaSwingTableIdx_TDOWN_A[delta];
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; // Record delta swing for mix mode power tracking
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A]));
if(c.RfPathCount > 1)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta]));
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_B] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B];
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B] = -1 * deltaSwingTableIdx_TDOWN_B[delta];
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; // Record delta swing for mix mode power tracking
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B]));
}
}
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("\n\n================================ [Path-%c] Calculating PowerIndexOffset ================================\n", (p == ODM_RF_PATH_A ? 'A' : 'B')));
if (pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] == pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]) // If Thermal value changes but lookup table value still the same
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
else
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]; // Power Index Diff between 2 times Power Tracking
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("[Path-%c] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n",
(p == ODM_RF_PATH_A ? 'A' : 'B'), pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p], pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p],
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]));
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pDM_Odm->BbSwingIdxOfdmBase[p] + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p];
pDM_Odm->RFCalibrateInfo.CCK_index = pDM_Odm->BbSwingIdxCckBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p];
pDM_Odm->BbSwingIdxCck = pDM_Odm->RFCalibrateInfo.CCK_index;
pDM_Odm->BbSwingIdxOfdm[p] = pDM_Odm->RFCalibrateInfo.OFDM_index[p];
// *************Print BB Swing Base and Index Offset*************
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n",
pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p]));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'OFDM' final index(%d) = BaseIndex[%c](%d) + PowerIndexOffset(%d)\n",
pDM_Odm->BbSwingIdxOfdm[p], (p == ODM_RF_PATH_A ? 'A' : 'B'), pDM_Odm->BbSwingIdxOfdmBase[p], pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p]));
//4 7.1 Handle boundary conditions of index.
if(pDM_Odm->RFCalibrateInfo.OFDM_index[p] > c.SwingTableSize_OFDM-1)
{
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = c.SwingTableSize_OFDM-1;
}
else if (pDM_Odm->RFCalibrateInfo.OFDM_index[p] < OFDM_min_index)
{
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = OFDM_min_index;
}
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("\n\n========================================================================================================\n"));
if(pDM_Odm->RFCalibrateInfo.CCK_index > c.SwingTableSize_CCK-1)
pDM_Odm->RFCalibrateInfo.CCK_index = c.SwingTableSize_CCK-1;
//else if (pDM_Odm->RFCalibrateInfo.CCK_index < 0)
//pDM_Odm->RFCalibrateInfo.CCK_index = 0;
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d\n",
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl, ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n",
pDM_Odm->RFCalibrateInfo.CCK_index, pDM_Odm->BbSwingIdxCckBase)); //Print Swing base & current
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%c]: %d\n",
pDM_Odm->RFCalibrateInfo.OFDM_index[p], (p == ODM_RF_PATH_A ? 'A' : 'B'), pDM_Odm->BbSwingIdxOfdmBase[p]));
}
if ((pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A] != 0 ||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B] != 0 ) &&
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
{
//4 7.2 Configure the Swing Table to adjust Tx Power.
pDM_Odm->RFCalibrateInfo.bTxPowerChanged = TRUE; // Always TRUE after Tx Power is adjusted by power tracking.
//
// 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
// to increase TX power. Otherwise, EVM will be bad.
//
// 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.
if (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature Increasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
if(c.RfPathCount > 1)
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature Increasing(B): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
}
else if (ThermalValue < pDM_Odm->RFCalibrateInfo.ThermalValue)// Low temperature
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature Decreasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
if(c.RfPathCount > 1)
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature Decreasing(B): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
if (ThermalValue > pHalData->EEPROMThermalMeter)
#else
if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)
#endif
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E ||
pDM_Odm->SupportICType == ODM_RTL8821 || pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking MIX_MODE**********\n"));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking BBSWING_MODE**********\n"));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
}
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E ||
pDM_Odm->SupportICType == ODM_RTL8821 || pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking MIX_MODE**********\n"));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel);
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking BBSWING_MODE**********\n"));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
}
}
pDM_Odm->BbSwingIdxCckBase = pDM_Odm->BbSwingIdxCck; // Record last time Power Tracking result as base.
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->BbSwingIdxOfdm[p];
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("pDM_Odm->RFCalibrateInfo.ThermalValue = %d ThermalValue= %d\n", pDM_Odm->RFCalibrateInfo.ThermalValue, ThermalValue));
pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; //Record last Power Tracking Thermal Value
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
#if (RTL8723B_SUPPORT == 0)
// Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).
if ((delta_IQK >= c.Threshold_IQK)) {
if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress)
(*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8);
}
#endif
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("<===ODM_TXPowerTrackingCallback_ThermalMeter\n"));
pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
}
//3============================================================
//3 IQ Calibration
//3============================================================
VOID
ODM_ResetIQKResult(
IN PDM_ODM_T pDM_Odm
)
{
u1Byte i;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
if (!IS_HARDWARE_TYPE_8192D(Adapter))
return;
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("PHY_ResetIQKResult:: settings regs %d default regs %d\n", (u4Byte)(sizeof(pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting)/sizeof(IQK_MATRIX_REGS_SETTING)), IQK_Matrix_Settings_NUM));
//0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc
for(i = 0; i < IQK_Matrix_Settings_NUM; i++)
{
{
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][0] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][2] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][4] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][6] = 0x100;
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][1] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][3] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][5] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][7] = 0x0;
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].bIQKDone = FALSE;
}
}
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl)
{
u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] =
{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165};
u1Byte place = chnl;
if(chnl > 14)
{
for(place = 14; place<sizeof(channel_all); place++)
{
if(channel_all[place] == chnl)
{
return place-13;
}
}
}
return 0;
}
#endif

89
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/HalPhyRf.h
View File

@ -1,89 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
typedef enum _SPUR_CAL_METHOD {
PLL_RESET,
AFE_PHASE_SEL
} SPUR_CAL_METHOD;
typedef enum _PWRTRACK_CONTROL_METHOD {
BBSWING,
TXAGC,
MIX_MODE
} PWRTRACK_METHOD;
typedef VOID (*FuncSetPwr)(PDM_ODM_T, PWRTRACK_METHOD, u1Byte, u1Byte);
typedef VOID (*FuncIQK)(PDM_ODM_T, u1Byte, u1Byte, u1Byte);
typedef VOID (*FuncLCK)(PDM_ODM_T);
typedef VOID (*FuncSwing)(PDM_ODM_T, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
typedef struct _TXPWRTRACK_CFG {
u1Byte SwingTableSize_CCK;
u1Byte SwingTableSize_OFDM;
u1Byte Threshold_IQK;
u1Byte AverageThermalNum;
u1Byte RfPathCount;
u4Byte ThermalRegAddr;
FuncSetPwr ODM_TxPwrTrackSetPwr;
FuncIQK DoIQK;
FuncLCK PHY_LCCalibrate;
FuncSwing GetDeltaSwingTable;
} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG;
void ConfigureTxpowerTrack(
IN PDM_ODM_T pDM_Odm,
OUT PTXPWRTRACK_CFG pConfig
);
VOID
ODM_ClearTxPowerTrackingState(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_TXPowerTrackingCallback_ThermalMeter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER Adapter
#endif
);
#define ODM_TARGET_CHNL_NUM_2G_5G 59
VOID
ODM_ResetIQKResult(
IN PDM_ODM_T pDM_Odm
);
u1Byte
ODM_GetRightChnlPlaceforIQK(
IN u1Byte chnl
);
#endif // #ifndef __HAL_PHY_RF_H__

24
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/Mp_Precomp.h
View File

@ -1,24 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//#include <Precomp.h>
//#include "phydm_precomp.h"
//#include "../phydm_precomp.h"

880
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/PhyDM_Adaptivity.c
View File

@ -1,880 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
VOID
Phydm_CheckAdaptivity(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)
{
if(pDM_Odm->bAdaOn == TRUE)
{
if(pDM_Odm->DynamicLinkAdaptivity == TRUE)
{
if(pDM_Odm->bLinked && pDM_Odm->bCheck == FALSE)
{
Phydm_NHMCounterStatistics(pDM_Odm);
Phydm_CheckEnvironment(pDM_Odm);
}
else if(!pDM_Odm->bLinked)
{
pDM_Odm->bCheck = FALSE;
}
}
else
{
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
pDM_Odm->adaptivity_flag = TRUE;
}
}
else
{
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
pDM_Odm->adaptivity_flag = FALSE;
}
}
}
VOID
Phydm_NHMCounterStatisticsInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
{
//PHY parameters initialize for ac series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, 0xC350); //0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff); //0x994[31:16]=0xffff th_9, th_10
//ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff5c); //0x998=0xffffff5c th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); //0x998=0xffffff52 th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); //0x99c=0xffffffff th_7, th_6, th_5, th_4
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); //0x9a0[7:0]=0xff th_8
//ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 0x7); //0x994[9:8]=3 enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 0x1); //0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1); //0x9e8[7]=1 max power among all RX ants
}
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
//PHY parameters initialize for n series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0xC350); //0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms
//ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0x4e20); //0x894[31:16]=0x4e20 Time duration for NHM unit: 4us, 0x4e20=80ms
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff); //0x890[31:16]=0xffff th_9, th_10
//ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff5c); //0x898=0xffffff5c th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); //0x898=0xffffff52 th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); //0x89c=0xffffffff th_7, th_6, th_5, th_4
ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); //0xe28[7:0]=0xff th_8
//ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); //0x890[9:8]=3 enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x1); //0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); //0xc0c[7]=1 max power among all RX ants
}
}
VOID
Phydm_NHMCounterStatistics(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
return;
// Get NHM report
Phydm_GetNHMCounterStatistics(pDM_Odm);
// Reset NHM counter
Phydm_NHMCounterStatisticsReset(pDM_Odm);
}
VOID
Phydm_GetNHMCounterStatistics(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u4Byte value32 = 0;
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord);
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord);
pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0);
pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1)>>8);
}
VOID
Phydm_NHMCounterStatisticsReset(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);
}
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);
}
}
VOID
Phydm_NHMBBInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pDM_Odm->adaptivity_flag = FALSE;
pDM_Odm->tolerance_cnt = 3;
pDM_Odm->NHMLastTxOkcnt = 0;
pDM_Odm->NHMLastRxOkcnt = 0;
pDM_Odm->NHMCurTxOkcnt = 0;
pDM_Odm->NHMCurRxOkcnt = 0;
}
VOID
Phydm_SetEDCCAThreshold(
IN PVOID pDM_VOID,
IN s1Byte H2L,
IN s1Byte L2H
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)L2H);
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)H2L);
}
else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
{
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte0, (u1Byte)L2H);
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte1, (u1Byte)H2L);
}
}
VOID
Phydm_SetTRxMux(
IN PVOID pDM_VOID,
IN PhyDM_Trx_MUX_Type txMode,
IN PhyDM_Trx_MUX_Type rxMode
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3|BIT2|BIT1, txMode); // set TXmod to standby mode to remove outside noise affect
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22|BIT21|BIT20, rxMode); // set RXmod to standby mode to remove outside noise affect
if(pDM_Odm->RFType > ODM_1T1R)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3|BIT2|BIT1, txMode); // set TXmod to standby mode to remove outside noise affect
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22|BIT21|BIT20, rxMode); // set RXmod to standby mode to remove outside noise affect
}
}
else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11|BIT10|BIT9|BIT8, txMode); // set TXmod to standby mode to remove outside noise affect
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7|BIT6|BIT5|BIT4, rxMode); // set RXmod to standby mode to remove outside noise affect
if(pDM_Odm->RFType > ODM_1T1R)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11|BIT10|BIT9|BIT8, txMode); // set TXmod to standby mode to remove outside noise affect
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7|BIT6|BIT5|BIT4, rxMode); // set RXmod to standby mode to remove outside noise affect
}
}
}
VOID
Phydm_MACEDCCAState(
IN PVOID pDM_VOID,
IN PhyDM_MACEDCCA_Type State
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(State == PhyDM_IGNORE_EDCCA)
{
ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1); //ignore EDCCA reg520[15]=1
ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0); //reg524[11]=0
}
else // don't set MAC ignore EDCCA signal
{
ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0); //don't ignore EDCCA reg520[15]=0
ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); //reg524[11]=1
}
pDM_Odm->EDCCA_enable_state = State;
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d \n", State));
}
BOOLEAN
Phydm_CalNHMcnt(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u2Byte Base = 0;
Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1;
if(Base != 0)
{
pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base;
pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base;
}
if((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100)
return TRUE; // clean environment
else
return FALSE; //noisy environment
}
VOID
Phydm_CheckEnvironment(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
BOOLEAN isCleanEnvironment = FALSE;
u1Byte i, clean = 0;
if(pDM_Odm->bFirstLink == TRUE)
{
pDM_Odm->adaptivity_flag = TRUE;
pDM_Odm->bFirstLink = FALSE;
return;
}
else
{
if(pDM_Odm->NHMWait < 3) // Start enter NHM after 4 NHMWait
{
pDM_Odm->NHMWait ++;
Phydm_NHMCounterStatistics(pDM_Odm);
return;
}
else
{
Phydm_NHMCounterStatistics(pDM_Odm);
isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);
if(isCleanEnvironment == TRUE)
{
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup; //mode 1
pDM_Odm->TH_EDCCA_HL_diff= pDM_Odm->TH_EDCCA_HL_diff_backup;
#endif
pDM_Odm->adaptivity_flag = TRUE;
}
else
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
#else
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; // for AP mode 2
pDM_Odm->TH_EDCCA_HL_diff= pDM_Odm->TH_EDCCA_HL_diff_mode2;
#endif
pDM_Odm->adaptivity_flag = FALSE;
}
pDM_Odm->bFirstLink = TRUE;
pDM_Odm->bCheck = TRUE;
}
}
}
VOID
Phydm_NHMBB(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
BOOLEAN bCleanEnvironment;
bCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);
pDM_Odm->NHMCurTxOkcnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_Odm->NHMLastTxOkcnt;
pDM_Odm->NHMCurRxOkcnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_Odm->NHMLastRxOkcnt;
pDM_Odm->NHMLastTxOkcnt = *(pDM_Odm->pNumTxBytesUnicast);
pDM_Odm->NHMLastRxOkcnt = *(pDM_Odm->pNumRxBytesUnicast);
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("cnt_0=%d, cnt_1=%d, bCleanEnvironment = %d, NHMCurTxOkcnt = %llu, NHMCurRxOkcnt = %llu\n",
pDM_Odm->NHM_cnt_0, pDM_Odm->NHM_cnt_1, bCleanEnvironment, pDM_Odm->NHMCurTxOkcnt, pDM_Odm->NHMCurRxOkcnt));
if(pDM_Odm->NHMWait < 4) // Start enter NHM after 4 NHMWait
{
pDM_Odm->NHMWait ++;
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
}
else if ( ((pDM_Odm->NHMCurTxOkcnt>>10) > 2) && ((pDM_Odm->NHMCurTxOkcnt) + 1 > (u8Byte)(pDM_Odm->NHMCurRxOkcnt<<2) + 1)) //Tx > 4*Rx and Tx > 2Mb possible for adaptivity test
{
if(bCleanEnvironment == TRUE || pDM_Odm->adaptivity_flag == TRUE)
{
//Enable EDCCA since it is possible running Adaptivity testing
pDM_Odm->adaptivity_flag = TRUE;
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
pDM_Odm->tolerance_cnt = 0;
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_backup ;
#endif
}
else
{
if(pDM_Odm->tolerance_cnt < 3)
pDM_Odm->tolerance_cnt ++;
else
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2 ;
#else
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
#endif
pDM_Odm->adaptivity_flag = FALSE;
}
}
}
else // TX<RX
{
if(pDM_Odm->adaptivity_flag == TRUE && bCleanEnvironment == FALSE)
{
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
pDM_Odm->tolerance_cnt = 0;
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_backup ;
#endif
}
#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23
#ifdef UNIVERSAL_REPEATER
else if((bCleanEnvironment == TRUE) && (pDM_Odm->VXD_bLinked) && ((pDM_Odm->NHMCurTxOkcnt>>10) > 1)) // clean environment and VXD linked and Tx TP>1Mb
{
pDM_Odm->adaptivity_flag = TRUE;
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
pDM_Odm->tolerance_cnt = 0;
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_backup ;
}
#endif
#endif // for repeater mode add by YuChen 2014.06.23
else
{
if(pDM_Odm->tolerance_cnt < 3)
pDM_Odm->tolerance_cnt ++;
else
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2 ;
#else
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
#endif
pDM_Odm->adaptivity_flag = FALSE;
}
}
}
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity_flag = %d\n ", pDM_Odm->adaptivity_flag));
}
VOID
Phydm_SearchPwdBLowerBound(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u4Byte value32 =0;
u1Byte cnt, IGI_Pause = 0x7f, IGI_Resume = 0x20, IGI = 0x50; //IGI = 0x50 for cal EDCCA lower bound
u1Byte txEdcca1 = 0, txEdcca0 = 0;
BOOLEAN bAdjust=TRUE;
s1Byte TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32;
s1Byte Diff;
Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
ODM_Write_DIG(pDM_Odm, IGI_Pause);
Diff = IGI_target -(s1Byte)IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
if(TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
ODM_delay_ms(5);
while(bAdjust)
{
for(cnt=0; cnt<20; cnt ++)
{
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
value32 = ODM_GetBBReg(pDM_Odm,ODM_REG_RPT_11N, bMaskDWord);
else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
value32 = ODM_GetBBReg(pDM_Odm,ODM_REG_RPT_11AC, bMaskDWord);
if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8723B|ODM_RTL8188E)))
txEdcca1 = txEdcca1 + 1;
else if(value32 & BIT29)
txEdcca1 = txEdcca1 + 1;
else
txEdcca0 = txEdcca0 + 1;
}
if(txEdcca1 > 9 )
{
IGI = IGI -1;
TH_L2H_dmc = TH_L2H_dmc + 1;
if(TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
txEdcca1 = 0;
txEdcca0 = 0;
if(TH_L2H_dmc == 10)
{
bAdjust = FALSE;
pDM_Odm->H2L_lb = TH_H2L_dmc;
pDM_Odm->L2H_lb = TH_L2H_dmc;
pDM_Odm->Adaptivity_IGI_upper = IGI;
}
}
else
{
bAdjust = FALSE;
pDM_Odm->H2L_lb = TH_H2L_dmc;
pDM_Odm->L2H_lb = TH_L2H_dmc;
pDM_Odm->Adaptivity_IGI_upper = IGI;
}
}
Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);
ODM_Write_DIG(pDM_Odm, IGI_Resume);
Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); // resume to no link state
}
VOID
Phydm_AdaptivityInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER pAdapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
pDM_Odm->Carrier_Sense_enable = (BOOLEAN)pMgntInfo->RegEnableCarrierSense;
pDM_Odm->NHM_enable = (BOOLEAN)pMgntInfo->RegNHMEnable;
pDM_Odm->DynamicLinkAdaptivity = (BOOLEAN)pMgntInfo->RegDmLinkAdaptivity;
#elif(DM_ODM_SUPPORT_TYPE == ODM_CE)
pDM_Odm->Carrier_Sense_enable = (pDM_Odm->Adapter->registrypriv.adaptivity_mode!=0)?TRUE:FALSE;
pDM_Odm->NHM_enable = (BOOLEAN)pDM_Odm->Adapter->registrypriv.nhm_en;
pDM_Odm->DynamicLinkAdaptivity = FALSE; // Jeff please add this
#endif
#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
if(pDM_Odm->Carrier_Sense_enable == FALSE)
{
#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
if( pMgntInfo->RegL2HForAdaptivity != 0 )
pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;
else
#endif
pDM_Odm->TH_L2H_ini = 0xf5; // -7
}
else
{
#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
if( pMgntInfo->RegL2HForAdaptivity != 0 )
pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;
else
#endif
pDM_Odm->TH_L2H_ini = 0xa;
}
pDM_Odm->AdapEn_RSSI = 20;
#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
if( pMgntInfo->RegHLDiffForAdaptivity != 0 )
pDM_Odm->TH_EDCCA_HL_diff = pMgntInfo->RegHLDiffForAdaptivity;
else
#endif
pDM_Odm->TH_EDCCA_HL_diff = 7;
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
if(pDM_Odm->Carrier_Sense_enable){
pDM_Odm->TH_L2H_ini = 10;
pDM_Odm->TH_EDCCA_HL_diff = 7;
pDM_Odm->AdapEn_RSSI = 30;
}
else
{
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup; //set by mib
pDM_Odm->TH_EDCCA_HL_diff = 7;
pDM_Odm->AdapEn_RSSI = 20;
}
pDM_Odm->TH_L2H_ini_mode2 = 20;
pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8;
//pDM_Odm->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini;
pDM_Odm->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff ;
if(priv->pshare->rf_ft_var.adaptivity_enable == 2)
pDM_Odm->DynamicLinkAdaptivity = TRUE;
else
pDM_Odm->DynamicLinkAdaptivity = FALSE;
// pDM_Odm->NHM_enable = FALSE;
#endif
pDM_Odm->IGI_Base = 0x32;
pDM_Odm->IGI_target = 0x1c;
pDM_Odm->ForceEDCCA = 0;
pDM_Odm->H2L_lb= 0;
pDM_Odm->L2H_lb= 0;
pDM_Odm->Adaptivity_IGI_upper = 0;
pDM_Odm->NHMWait = 0;
Phydm_NHMBBInit(pDM_Odm);
pDM_Odm->bCheck = FALSE;
pDM_Odm->bFirstLink = TRUE;
pDM_Odm->bAdaOn = TRUE;
ODM_SetBBReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); // stop counting if EDCCA is asserted
//Search pwdB lower bound
{
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
ODM_SetBBReg(pDM_Odm,ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);
else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
ODM_SetBBReg(pDM_Odm,ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);
Phydm_SearchPwdBLowerBound(pDM_Odm);
}
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
}
BOOLEAN
Phydm_Adaptivity(
IN PVOID pDM_VOID,
IN u1Byte IGI
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
s1Byte TH_L2H_dmc, TH_H2L_dmc, L2H_nolink_Band4 = 0x7f, H2L_nolink_Band4 = 0x7f;
s1Byte Diff, IGI_target;
BOOLEAN EDCCA_State = FALSE;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER pAdapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
BOOLEAN bFwCurrentInPSMode=FALSE;
PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
// Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
if(bFwCurrentInPSMode)
return FALSE;
#endif
if(!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Go to odm_DynamicEDCCA() \n"));
// Add by Neil Chen to enable edcca to MP Platform
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
// Adjust EDCCA.
if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
Phydm_DynamicEDCCA(pDM_Odm);
#endif
return FALSE;
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
if(pMgntInfo->RegEnableAdaptivity== 2)
#else
if (pDM_Odm->Adapter->registrypriv.adaptivity_en == 2)
#endif
{
if(pDM_Odm->Carrier_Sense_enable == FALSE) // check domain Code for Adaptivity or CarrierSense
{
if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
!(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d \n", pDM_Odm->odm_Regulation5G));
return FALSE;
}
else if((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
!(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d \n", pDM_Odm->odm_Regulation2_4G));
return FALSE;
}
else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n"));
return FALSE;
}
}
else
{
if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
!(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));
return FALSE;
}
else if((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
!(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));
return FALSE;
}
else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));
return FALSE;
}
}
}
#endif
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====> \n"));
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("ForceEDCCA=%d, IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d, AdapEn_RSSI = %d\n",
pDM_Odm->ForceEDCCA, pDM_Odm->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, pDM_Odm->AdapEn_RSSI));
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); //ADC_mask enable
if(*pDM_Odm->pBandWidth == ODM_BW20M) //CHANNEL_WIDTH_20
IGI_target = pDM_Odm->IGI_Base;
else if(*pDM_Odm->pBandWidth == ODM_BW40M)
IGI_target = pDM_Odm->IGI_Base + 2;
else if(*pDM_Odm->pBandWidth == ODM_BW80M)
IGI_target = pDM_Odm->IGI_Base + 2;
else
IGI_target = pDM_Odm->IGI_Base;
pDM_Odm->IGI_target = (u1Byte) IGI_target;
if(*pDM_Odm->pChannel >= 149) // Band4 -> for AP : mode2, for sd4 and sd7 : turnoff adaptivity
{
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
if(pDM_Odm->bLinked)
{
Diff = IGI_target -(s1Byte)IGI;
L2H_nolink_Band4 = pDM_Odm->TH_L2H_ini_mode2 + Diff;
if(L2H_nolink_Band4 > 10)
L2H_nolink_Band4 = 10;
H2L_nolink_Band4 = L2H_nolink_Band4 - pDM_Odm->TH_EDCCA_HL_diff_mode2;
}
#endif
Phydm_SetEDCCAThreshold(pDM_Odm, H2L_nolink_Band4, L2H_nolink_Band4);
return FALSE;
}
if(!pDM_Odm->ForceEDCCA)
{
if(pDM_Odm->RSSI_Min > pDM_Odm->AdapEn_RSSI)
EDCCA_State = 1;
else if(pDM_Odm->RSSI_Min < (pDM_Odm->AdapEn_RSSI - 5))
EDCCA_State = 0;
}
else
EDCCA_State = 1;
if(pDM_Odm->Carrier_Sense_enable == FALSE && pDM_Odm->NHM_enable == TRUE)
Phydm_NHMBB(pDM_Odm);
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d, EDCCA_enable_state = %d\n",
(*pDM_Odm->pBandWidth==ODM_BW80M)?"80M":((*pDM_Odm->pBandWidth==ODM_BW40M)?"40M":"20M"), IGI_target, EDCCA_State, pDM_Odm->EDCCA_enable_state));
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, AdapIGIUpper= 0x %x\n", pDM_Odm->RSSI_Min, pDM_Odm->Adaptivity_IGI_upper));
if(EDCCA_State == 1)
{
Diff = IGI_target -(s1Byte)IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
if(TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
//replace lower bound to prevent EDCCA always equal 1
if(TH_H2L_dmc < pDM_Odm->H2L_lb)
TH_H2L_dmc = pDM_Odm->H2L_lb;
if(TH_L2H_dmc < pDM_Odm->L2H_lb)
TH_L2H_dmc = pDM_Odm->L2H_lb;
}
else
{
TH_L2H_dmc = 0x7f;
TH_H2L_dmc = 0x7f;
}
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d, adaptivity_flg = %d, bAdaOn = %d, DynamicLinkAdaptivity = %d, NHM_enable = %d\n",
IGI, TH_L2H_dmc, TH_H2L_dmc, pDM_Odm->adaptivity_flag, pDM_Odm->bAdaOn, pDM_Odm->DynamicLinkAdaptivity, pDM_Odm->NHM_enable));
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
return TRUE;
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
Phydm_EnableEDCCA(
IN PVOID pDM_VOID
)
{
// This should be moved out of OUTSRC
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
// Enable EDCCA. The value is suggested by SD3 Wilson.
//
// Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13.
//
if((pDM_Odm->SupportICType == ODM_RTL8723A)&&(IS_WIRELESS_MODE_G(pAdapter)))
{
//PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x00);
ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x00);
ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0xFD);
}
else
{
//PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x03);
ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x03);
ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0x00);
}
//PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold+2, 0x00);
}
VOID
Phydm_DisableEDCCA(
IN PVOID pDM_VOID
)
{
// Disable EDCCA..
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x7f);
ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold+2, 0x7f);
}
//
// Description: According to initial gain value to determine to enable or disable EDCCA.
//
// Suggested by SD3 Wilson. Added by tynli. 2011.11.25.
//
VOID
Phydm_DynamicEDCCA(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u1Byte RegC50, RegC58;
BOOLEAN bEDCCAenable = FALSE;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
BOOLEAN bFwCurrentInPSMode=FALSE;
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
// Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
if(bFwCurrentInPSMode)
return;
#endif
//
// 2013/11/14 Ken According to BB team Jame's suggestion, we need to disable soft AP mode EDCCA.
// 2014/01/08 MH For Miracst AP mode test. We need to disable EDCCA. Otherwise, we may stop
// to send beacon in noisy environment or platform.
//
if(ACTING_AS_AP(pAdapter) || ACTING_AS_AP(GetFirstAPAdapter(pAdapter)))
//if(ACTING_AS_AP(pAdapter))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("At least One Port as AP disable EDCCA\n"));
Phydm_DisableEDCCA(pDM_Odm);
if(pHalData->bPreEdccaEnable)
Phydm_DisableEDCCA(pDM_Odm);
pHalData->bPreEdccaEnable = FALSE;
return;
}
RegC50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);
RegC58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0);
if((RegC50 > 0x28 && RegC58 > 0x28) ||
((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50>0x26)) ||
(pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28))
{
if(!pHalData->bPreEdccaEnable)
{
Phydm_EnableEDCCA(pDM_Odm);
pHalData->bPreEdccaEnable = TRUE;
}
}
else if((RegC50 < 0x25 && RegC58 < 0x25) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25))
{
if(pHalData->bPreEdccaEnable)
{
Phydm_DisableEDCCA(pDM_Odm);
pHalData->bPreEdccaEnable = FALSE;
}
}
}
#endif

146
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/PhyDM_Adaptivity.h
View File

@ -1,146 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMADAPTIVITY_H__
#define __PHYDMADAPTIVITY_H__
#define ADAPTIVITY_VERSION "7.1"
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
typedef enum _tag_PhyDM_REGULATION_Type {
REGULATION_FCC = 0,
REGULATION_MKK = 1,
REGULATION_ETSI = 2,
REGULATION_WW = 3,
MAX_REGULATION_NUM = 4
} PhyDM_REGULATION_TYPE;
#endif
typedef enum tag_PhyDM_TRx_MUX_Type
{
PhyDM_SHUTDOWN = 0,
PhyDM_STANDBY_MODE = 1,
PhyDM_TX_MODE = 2,
PhyDM_RX_MODE = 3
}PhyDM_Trx_MUX_Type;
typedef enum tag_PhyDM_MACEDCCA_Type
{
PhyDM_IGNORE_EDCCA = 0,
PhyDM_DONT_IGNORE_EDCCA = 1
}PhyDM_MACEDCCA_Type;
VOID
Phydm_CheckAdaptivity(
IN PVOID pDM_VOID
);
VOID
Phydm_CheckEnvironment(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatisticsInit(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatistics(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMBBInit(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMBB(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatisticsReset(
IN PVOID pDM_VOID
);
VOID
Phydm_GetNHMCounterStatistics(
IN PVOID pDM_VOID
);
VOID
Phydm_MACEDCCAState(
IN PVOID pDM_VOID,
IN PhyDM_MACEDCCA_Type State
);
VOID
Phydm_SetEDCCAThreshold(
IN PVOID pDM_VOID,
IN s1Byte H2L,
IN s1Byte L2H
);
VOID
Phydm_SetTRxMux(
IN PVOID pDM_VOID,
IN PhyDM_Trx_MUX_Type txMode,
IN PhyDM_Trx_MUX_Type rxMode
);
BOOLEAN
Phydm_CalNHMcnt(
IN PVOID pDM_VOID
);
VOID
Phydm_SearchPwdBLowerBound(
IN PVOID pDM_VOID
);
VOID
Phydm_AdaptivityInit(
IN PVOID pDM_VOID
);
BOOLEAN
Phydm_Adaptivity(
IN PVOID pDM_VOID,
IN u1Byte IGI
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
Phydm_DisableEDCCA(
IN PVOID pDM_VOID
);
VOID
Phydm_DynamicEDCCA(
IN PVOID pDM_VOID
);
#endif
#endif

2397
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm.c
View File

File diff suppressed because it is too large Load Diff

2000
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm.h
View File

File diff suppressed because it is too large Load Diff

213
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_ACS.c
View File

@ -1,213 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
u1Byte
ODM_GetAutoChannelSelectResult(
IN PVOID pDM_VOID,
IN u1Byte Band
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PACS pACS = &pDM_Odm->DM_ACS;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(Band == ODM_BAND_2_4G)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_2G(%d)\n", pACS->CleanChannel_2G));
return (u1Byte)pACS->CleanChannel_2G;
}
else
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_5G(%d)\n", pACS->CleanChannel_5G));
return (u1Byte)pACS->CleanChannel_5G;
}
#else
return (u1Byte)pACS->CleanChannel_2G;
#endif
}
VOID
odm_AutoChannelSelectSetting(
IN PVOID pDM_VOID,
IN BOOLEAN IsEnable
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u2Byte period = 0x2710;// 40ms in default
u2Byte NHMType = 0x7;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSetting()=========> \n"));
if(IsEnable)
{//20 ms
period = 0x1388;
NHMType = 0x1;
}
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
{
//PHY parameters initialize for ac series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, period); //0x990[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms
//ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, NHMType); //0x994[9:8]=3 enable CCX
}
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
//PHY parameters initialize for n series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, period); //0x894[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms
//ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, NHMType); //0x890[9:8]=3 enable CCX
}
#endif
}
VOID
odm_AutoChannelSelectInit(
IN PVOID pDM_VOID
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PACS pACS = &pDM_Odm->DM_ACS;
u1Byte i;
if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
return;
if(pACS->bForceACSResult)
return;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectInit()=========> \n"));
pACS->CleanChannel_2G = 1;
pACS->CleanChannel_5G = 36;
for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i)
{
pACS->Channel_Info_2G[0][i] = 0;
pACS->Channel_Info_2G[1][i] = 0;
}
if(pDM_Odm->SupportICType & (ODM_IC_11AC_SERIES|ODM_RTL8192D))
{
for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i)
{
pACS->Channel_Info_5G[0][i] = 0;
pACS->Channel_Info_5G[1][i] = 0;
}
}
#endif
}
VOID
odm_AutoChannelSelectReset(
IN PVOID pDM_VOID
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PACS pACS = &pDM_Odm->DM_ACS;
if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
return;
if(pACS->bForceACSResult)
return;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectReset()=========> \n"));
odm_AutoChannelSelectSetting(pDM_Odm,TRUE);// for 20ms measurement
Phydm_NHMCounterStatisticsReset(pDM_Odm);
#endif
}
VOID
odm_AutoChannelSelect(
IN PVOID pDM_VOID,
IN u1Byte Channel
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PACS pACS = &pDM_Odm->DM_ACS;
u1Byte ChannelIDX = 0, SearchIDX = 0;
u2Byte MaxScore=0;
if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Return: SupportAbility ODM_BB_NHM_CNT is disabled\n"));
return;
}
if(pACS->bForceACSResult)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Force 2G clean channel = %d, 5G clean channel = %d\n",
pACS->CleanChannel_2G, pACS->CleanChannel_5G));
return;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel = %d=========> \n", Channel));
Phydm_GetNHMCounterStatistics(pDM_Odm);
odm_AutoChannelSelectSetting(pDM_Odm,FALSE);
if(Channel >=1 && Channel <=14)
{
ChannelIDX = Channel - 1;
pACS->Channel_Info_2G[1][ChannelIDX]++;
if(pACS->Channel_Info_2G[1][ChannelIDX] >= 2)
pACS->Channel_Info_2G[0][ChannelIDX] = (pACS->Channel_Info_2G[0][ChannelIDX] >> 1) +
(pACS->Channel_Info_2G[0][ChannelIDX] >> 2) + (pDM_Odm->NHM_cnt_0>>2);
else
pACS->Channel_Info_2G[0][ChannelIDX] = pDM_Odm->NHM_cnt_0;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): NHM_cnt_0 = %d \n", pDM_Odm->NHM_cnt_0));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n", ChannelIDX, pACS->Channel_Info_2G[0][ChannelIDX], ChannelIDX, pACS->Channel_Info_2G[1][ChannelIDX]));
for(SearchIDX = 0; SearchIDX < ODM_MAX_CHANNEL_2G; SearchIDX++)
{
if(pACS->Channel_Info_2G[1][SearchIDX] != 0)
{
if(pACS->Channel_Info_2G[0][SearchIDX] >= MaxScore)
{
MaxScore = pACS->Channel_Info_2G[0][SearchIDX];
pACS->CleanChannel_2G = SearchIDX+1;
}
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("(1)odm_AutoChannelSelect(): 2G: CleanChannel_2G = %d, MaxScore = %d \n",
pACS->CleanChannel_2G, MaxScore));
}
else if(Channel >= 36)
{
// Need to do
pACS->CleanChannel_5G = Channel;
}
#endif
}

61
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_ACS.h
View File

@ -1,61 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMACS_H__
#define __PHYDMACS_H__
#define ACS_VERSION "1.0"
#define ODM_MAX_CHANNEL_2G 14
#define ODM_MAX_CHANNEL_5G 24
typedef struct _ACS_
{
BOOLEAN bForceACSResult;
u1Byte CleanChannel_2G;
u1Byte CleanChannel_5G;
u2Byte Channel_Info_2G[2][ODM_MAX_CHANNEL_2G]; //Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times
u2Byte Channel_Info_5G[2][ODM_MAX_CHANNEL_5G];
}ACS, *PACS;
VOID
odm_AutoChannelSelectInit(
IN PVOID pDM_VOID
);
VOID
odm_AutoChannelSelectReset(
IN PVOID pDM_VOID
);
VOID
odm_AutoChannelSelect(
IN PVOID pDM_VOID,
IN u1Byte Channel
);
u1Byte
ODM_GetAutoChannelSelectResult(
IN PVOID pDM_VOID,
IN u1Byte Band
);
#endif

1206
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_AntDect.c
View File

File diff suppressed because it is too large Load Diff

76
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_AntDect.h
View File

@ -1,76 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMANTDECT_H__
#define __PHYDMANTDECT_H__
#define ANTDECT_VERSION "1.0"
#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))
//1 [1. Single Tone Method] ===================================================
VOID
ODM_SingleDualAntennaDefaultSetting(
IN PDM_ODM_T pDM_Odm
);
BOOLEAN
ODM_SingleDualAntennaDetection(
IN PDM_ODM_T pDM_Odm,
IN u1Byte mode
);
//1 [2. Scan AP RSSI Method] ==================================================
VOID
odm_SwAntDetectInit(
IN PDM_ODM_T pDM_Odm
);
#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink
BOOLEAN
ODM_SwAntDivCheckBeforeLink(
IN PDM_ODM_T pDM_Odm
);
//1 [3. PSD Method] ==========================================================
VOID
ODM_SingleDualAntennaDetection_PSD(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif

2850
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_AntDiv.c
View File

File diff suppressed because it is too large Load Diff

217
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_AntDiv.h
View File

@ -1,217 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMANTDIV_H__
#define __PHYDMANTDIV_H__
#define ANTDIV_VERSION "1.0"
#define ANT1_2G 0 // = ANT2_5G
#define ANT2_2G 1 // = ANT1_5G
//Antenna Diversty Control Type
#define ODM_AUTO_ANT 0
#define ODM_FIX_MAIN_ANT 1
#define ODM_FIX_AUX_ANT 2
#define TX_BY_REG 0
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#define ODM_RTL8881A 0 //Just for windows driver to jointly use ODM-driver
#endif
#define ODM_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)
#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E)
#define ODM_OLD_IC_ANTDIV_SUPPORT (ODM_RTL8723A|ODM_RTL8192C|ODM_RTL8192D)
#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A)
#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_ANTDIV_2G BIT0
#define ODM_ANTDIV_5G BIT1
#define ANTDIV_ON 1
#define ANTDIV_OFF 0
#define INIT_ANTDIV_TIMMER 0
#define CANCEL_ANTDIV_TIMMER 1
#define RELEASE_ANTDIV_TIMMER 2
VOID
ODM_StopAntennaSwitchDm(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_SetAntConfig(
IN PDM_ODM_T pDM_Odm,
IN u1Byte antSetting // 0=A, 1=B, 2=C, ....
);
#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
VOID ODM_SwAntDivRestAfterLink( IN PDM_ODM_T pDM_Odm);
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
VOID
ODM_UpdateRxIdleAnt(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Ant
);
VOID
odm_AntselStatistics(
IN PDM_ODM_T pDM_Odm,
IN u1Byte antsel_tr_mux,
IN u4Byte MacId,
IN u4Byte RxPWDBAll
);
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
ODM_SW_AntDiv_Callback(
IN PRT_TIMER pTimer
);
VOID
ODM_SW_AntDiv_WorkitemCallback(
IN PVOID pContext
);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
VOID
ODM_SW_AntDiv_Callback(void *FunctionContext);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
odm_S0S1_SwAntDivByCtrlFrame(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Step
);
VOID
odm_AntselStatisticsOfCtrlFrame(
IN PDM_ODM_T pDM_Odm,
IN u1Byte antsel_tr_mux,
IN u4Byte RxPWDBAll
);
VOID
odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(
IN PDM_ODM_T pDM_Odm,
IN PODM_PHY_INFO_T pPhyInfo,
IN PODM_PACKET_INFO_T pPktinfo
);
#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#endif
#if(RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
VOID
odm_FastAntTraining(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_FastAntTrainingCallback(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_FastAntTrainingWorkItemCallback(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif
VOID
ODM_AntDivInit(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_AntDivReset(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_AntDiv(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_Process_RSSIForAntDiv(
IN OUT PDM_ODM_T pDM_Odm,
IN PODM_PHY_INFO_T pPhyInfo,
IN PODM_PACKET_INFO_T pPktinfo
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
ODM_SetTxAntByTxInfo(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte pDesc,
IN u1Byte macId
);
#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
ODM_SetTxAntByTxInfo(
//IN PDM_ODM_T pDM_Odm,
struct rtl8192cd_priv *priv,
struct tx_desc *pdesc,
struct tx_insn *txcfg,
unsigned short aid
);
#endif
VOID
ODM_AntDiv_Config(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_UpdateRxIdleAnt_8723B(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Ant,
IN u4Byte DefaultAnt,
IN u4Byte OptionalAnt
);
VOID
ODM_AntDivTimers(
IN PDM_ODM_T pDM_Odm,
IN u1Byte state
);
#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
#endif //#ifndef __ODMANTDIV_H__

357
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_CfoTracking.c
View File

@ -1,357 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
VOID
odm_SetCrystalCap(
IN PVOID pDM_VOID,
IN u1Byte CrystalCap
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
BOOLEAN bEEPROMCheck;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
bEEPROMCheck = (pHalData->EEPROMVersion >= 0x01)?TRUE:FALSE;
#else
bEEPROMCheck = TRUE;
#endif
if(pCfoTrack->CrystalCap == CrystalCap)
return;
pCfoTrack->CrystalCap = CrystalCap;
if(pDM_Odm->SupportICType & ODM_RTL8192D)
{
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x000000F0, CrystalCap & 0x0F);
ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0xF0000000, ((CrystalCap & 0xF0) >> 4));
}
else if(pDM_Odm->SupportICType & ODM_RTL8188E)
{
// write 0x24[22:17] = 0x24[16:11] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x007ff800, (CrystalCap | (CrystalCap << 6)));
}
else if(pDM_Odm->SupportICType & ODM_RTL8812)
{
// write 0x2C[30:25] = 0x2C[24:19] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap | (CrystalCap << 6)));
}
else if (((pDM_Odm->SupportICType & ODM_RTL8723A) && bEEPROMCheck) ||
(pDM_Odm->SupportICType & ODM_RTL8723B) ||(pDM_Odm->SupportICType & ODM_RTL8192E) ||
(pDM_Odm->SupportICType & ODM_RTL8821))
{
// 0x2C[23:18] = 0x2C[17:12] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x00FFF000, (CrystalCap | (CrystalCap << 6)));
}
else if(pDM_Odm->SupportICType & ODM_RTL8821B)
{
// write 0x28[6:1] = 0x24[30:25] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7E000000, CrystalCap);
ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7E, CrystalCap);
}
else if(pDM_Odm->SupportICType & ODM_RTL8814A)
{
// write 0x2C[26:21] = 0x2C[20:15] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x07FF8000, (CrystalCap | (CrystalCap << 6)));
}
else
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): Use default setting.\n"));
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6)));
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): CrystalCap = 0x%x\n", CrystalCap));
}
u1Byte
odm_GetDefaultCrytaltalCap(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u1Byte CrystalCap = 0x20;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
CrystalCap = pHalData->CrystalCap;
#else
prtl8192cd_priv priv = pDM_Odm->priv;
if(priv->pmib->dot11RFEntry.xcap > 0)
CrystalCap = priv->pmib->dot11RFEntry.xcap;
#endif
CrystalCap = CrystalCap & 0x3f;
return CrystalCap;
}
VOID
odm_SetATCStatus(
IN PVOID pDM_VOID,
IN BOOLEAN ATCStatus
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
if(pCfoTrack->bATCStatus == ATCStatus)
return;
ODM_SetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm), ATCStatus);
pCfoTrack->bATCStatus = ATCStatus;
}
BOOLEAN
odm_GetATCStatus(
IN PVOID pDM_VOID
)
{
BOOLEAN ATCStatus;
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
ATCStatus = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm));
return ATCStatus;
}
VOID
ODM_CfoTrackingReset(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
u1Byte CrystalCap;
pCfoTrack->DefXCap = odm_GetDefaultCrytaltalCap(pDM_Odm);
pCfoTrack->bAdjust = TRUE;
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap);
odm_SetATCStatus(pDM_Odm, TRUE);
#else
if(pCfoTrack->CrystalCap > pCfoTrack->DefXCap)
{
for(CrystalCap = pCfoTrack->CrystalCap; CrystalCap >= pCfoTrack->DefXCap; CrystalCap--)
odm_SetCrystalCap(pDM_Odm, CrystalCap);
}
else
{
for(CrystalCap = pCfoTrack->CrystalCap; CrystalCap <= pCfoTrack->DefXCap; CrystalCap++)
odm_SetCrystalCap(pDM_Odm, CrystalCap);
}
#endif
}
VOID
ODM_CfoTrackingInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
pCfoTrack->DefXCap = pCfoTrack->CrystalCap = odm_GetDefaultCrytaltalCap(pDM_Odm);
pCfoTrack->bATCStatus = odm_GetATCStatus(pDM_Odm);
pCfoTrack->bAdjust = TRUE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========> \n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): bATCStatus = %d, CrystalCap = 0x%x \n",pCfoTrack->bATCStatus, pCfoTrack->DefXCap));
}
VOID
ODM_CfoTracking(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
int CFO_kHz_A, CFO_kHz_B, CFO_ave = 0;
int CFO_ave_diff;
int CrystalCap = (int)pCfoTrack->CrystalCap;
u1Byte Adjust_Xtal = 1;
//4 Support ability
if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING))
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Return: SupportAbility ODM_BB_CFO_TRACKING is disabled\n"));
return;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking()=========> \n"));
if(!pDM_Odm->bLinked || !pDM_Odm->bOneEntryOnly)
{
//4 No link or more than one entry
ODM_CfoTrackingReset(pDM_Odm);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Reset: bLinked = %d, bOneEntryOnly = %d\n",
pDM_Odm->bLinked, pDM_Odm->bOneEntryOnly));
}
else
{
//3 1. CFO Tracking
//4 1.1 No new packet
if(pCfoTrack->packetCount == pCfoTrack->packetCount_pre)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): packet counter doesn't change\n"));
return;
}
pCfoTrack->packetCount_pre = pCfoTrack->packetCount;
//4 1.2 Calculate CFO
CFO_kHz_A = (int)(pCfoTrack->CFO_tail[0] * 3125) / 1280;
CFO_kHz_B = (int)(pCfoTrack->CFO_tail[1] * 3125) / 1280;
if(pDM_Odm->RFType < ODM_2T2R)
CFO_ave = CFO_kHz_A;
else
CFO_ave = (int)(CFO_kHz_A + CFO_kHz_B) >> 1;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): CFO_kHz_A = %dkHz, CFO_kHz_B = %dkHz, CFO_ave = %dkHz\n",
CFO_kHz_A, CFO_kHz_B, CFO_ave));
//4 1.3 Avoid abnormal large CFO
CFO_ave_diff = (pCfoTrack->CFO_ave_pre >= CFO_ave)?(pCfoTrack->CFO_ave_pre - CFO_ave):(CFO_ave - pCfoTrack->CFO_ave_pre);
if(CFO_ave_diff > 20 && pCfoTrack->largeCFOHit == 0 && !pCfoTrack->bAdjust)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): first large CFO hit\n"));
pCfoTrack->largeCFOHit = 1;
return;
}
else
pCfoTrack->largeCFOHit = 0;
pCfoTrack->CFO_ave_pre = CFO_ave;
//4 1.4 Dynamic Xtal threshold
if(pCfoTrack->bAdjust == FALSE)
{
if(CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH))
pCfoTrack->bAdjust = TRUE;
}
else
{
if(CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW))
pCfoTrack->bAdjust = FALSE;
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
//4 1.5 BT case: Disable CFO tracking
if(pDM_Odm->bBtEnabled)
{
pCfoTrack->bAdjust = FALSE;
odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable CFO tracking for BT!!\n"));
}
//4 1.6 Big jump
if(pCfoTrack->bAdjust)
{
if(CFO_ave > CFO_TH_XTAL_LOW)
Adjust_Xtal = Adjust_Xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2);
else if(CFO_ave < (-CFO_TH_XTAL_LOW))
Adjust_Xtal = Adjust_Xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap offset = %d\n", Adjust_Xtal));
}
#endif
//4 1.7 Adjust Crystal Cap.
if(pCfoTrack->bAdjust)
{
if(CFO_ave > CFO_TH_XTAL_LOW)
CrystalCap = CrystalCap + Adjust_Xtal;
else if(CFO_ave < (-CFO_TH_XTAL_LOW))
CrystalCap = CrystalCap - Adjust_Xtal;
if(CrystalCap > 0x3f)
CrystalCap = 0x3f;
else if (CrystalCap < 0)
CrystalCap = 0;
odm_SetCrystalCap(pDM_Odm, (u1Byte)CrystalCap);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n",
pCfoTrack->CrystalCap, pCfoTrack->DefXCap));
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
return;
//3 2. Dynamic ATC switch
if(CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC)
{
odm_SetATCStatus(pDM_Odm, FALSE);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable ATC!!\n"));
}
else
{
odm_SetATCStatus(pDM_Odm, TRUE);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Enable ATC!!\n"));
}
#endif
}
}
VOID
ODM_ParsingCFO(
IN PVOID pDM_VOID,
IN PVOID pPktinfo_VOID,
IN s1Byte* pcfotail
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PODM_PACKET_INFO_T pPktinfo = (PODM_PACKET_INFO_T)pPktinfo_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
u1Byte i;
if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING))
return;
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(pPktinfo->bPacketMatchBSSID)
#else
if(pPktinfo->StationID != 0)
#endif
{
//3 Update CFO report for path-A & path-B
// Only paht-A and path-B have CFO tail and short CFO
for(i = ODM_RF_PATH_A; i <= ODM_RF_PATH_B; i++)
{
pCfoTrack->CFO_tail[i] = (int)pcfotail[i];
}
//3 Update packet counter
if(pCfoTrack->packetCount == 0xffffffff)
pCfoTrack->packetCount = 0;
else
pCfoTrack->packetCount++;
}
}

68
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_CfoTracking.h
View File

@ -1,68 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMCFOTRACK_H__
#define __PHYDMCFOTRACK_H__
#define CFO_TRACKING_VERSION "1.0"
#define CFO_TH_XTAL_HIGH 20 // kHz
#define CFO_TH_XTAL_LOW 10 // kHz
#define CFO_TH_ATC 80 // kHz
typedef struct _CFO_TRACKING_
{
BOOLEAN bATCStatus;
BOOLEAN largeCFOHit;
BOOLEAN bAdjust;
u1Byte CrystalCap;
u1Byte DefXCap;
int CFO_tail[2];
int CFO_ave_pre;
u4Byte packetCount;
u4Byte packetCount_pre;
BOOLEAN bForceXtalCap;
BOOLEAN bReset;
}CFO_TRACKING, *PCFO_TRACKING;
VOID
ODM_CfoTrackingReset(
IN PVOID pDM_VOID
);
VOID
ODM_CfoTrackingInit(
IN PVOID pDM_VOID
);
VOID
ODM_CfoTracking(
IN PVOID pDM_VOID
);
VOID
ODM_ParsingCFO(
IN PVOID pDM_VOID,
IN PVOID pPktinfo_VOID,
IN s1Byte* pcfotail
);
#endif

2023
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_DIG.c
View File

File diff suppressed because it is too large Load Diff

309
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_DIG.h
View File

@ -1,309 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMDIG_H__
#define __PHYDMDIG_H__
#define DIG_VERSION "1.1"
typedef struct _Dynamic_Initial_Gain_Threshold_
{
BOOLEAN bStopDIG; // for debug
BOOLEAN bPauseDIG;
BOOLEAN bIgnoreDIG;
BOOLEAN bPSDInProgress;
u1Byte Dig_Enable_Flag;
u1Byte Dig_Ext_Port_Stage;
int RssiLowThresh;
int RssiHighThresh;
u4Byte FALowThresh;
u4Byte FAHighThresh;
u1Byte CurSTAConnectState;
u1Byte PreSTAConnectState;
u1Byte CurMultiSTAConnectState;
u1Byte PreIGValue;
u1Byte CurIGValue;
u1Byte BackupIGValue; //MP DIG
u1Byte BT30_CurIGI;
u1Byte IGIBackup;
s1Byte BackoffVal;
s1Byte BackoffVal_range_max;
s1Byte BackoffVal_range_min;
u1Byte rx_gain_range_max;
u1Byte rx_gain_range_min;
u1Byte Rssi_val_min;
u1Byte PreCCK_CCAThres;
u1Byte CurCCK_CCAThres;
u1Byte PreCCKPDState;
u1Byte CurCCKPDState;
u1Byte CCKPDBackup;
u1Byte LargeFAHit;
u1Byte ForbiddenIGI;
u4Byte Recover_cnt;
u1Byte DIG_Dynamic_MIN_0;
u1Byte DIG_Dynamic_MIN_1;
BOOLEAN bMediaConnect_0;
BOOLEAN bMediaConnect_1;
u4Byte AntDiv_RSSI_max;
u4Byte RSSI_max;
u1Byte *pbP2pLinkInProgress;
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
BOOLEAN bTpTarget;
BOOLEAN bNoiseEst;
u4Byte TpTrainTH_min;
u1Byte IGIOffset_A;
u1Byte IGIOffset_B;
#endif
}DIG_T,*pDIG_T;
typedef struct _FALSE_ALARM_STATISTICS{
u4Byte Cnt_Parity_Fail;
u4Byte Cnt_Rate_Illegal;
u4Byte Cnt_Crc8_fail;
u4Byte Cnt_Mcs_fail;
u4Byte Cnt_Ofdm_fail;
u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A
u4Byte Cnt_Cck_fail;
u4Byte Cnt_all;
u4Byte Cnt_Fast_Fsync;
u4Byte Cnt_SB_Search_fail;
u4Byte Cnt_OFDM_CCA;
u4Byte Cnt_CCK_CCA;
u4Byte Cnt_CCA_all;
u4Byte Cnt_BW_USC; //Gary
u4Byte Cnt_BW_LSC; //Gary
}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
{
DIG_TYPE_THRESH_HIGH = 0,
DIG_TYPE_THRESH_LOW = 1,
DIG_TYPE_BACKOFF = 2,
DIG_TYPE_RX_GAIN_MIN = 3,
DIG_TYPE_RX_GAIN_MAX = 4,
DIG_TYPE_ENABLE = 5,
DIG_TYPE_DISABLE = 6,
DIG_OP_TYPE_MAX
}DM_DIG_OP_E;
typedef enum tag_ODM_PauseDIG_Type {
ODM_PAUSE_DIG = BIT0,
ODM_RESUME_DIG = BIT1
} ODM_Pause_DIG_TYPE;
typedef enum tag_ODM_PauseCCKPD_Type {
ODM_PAUSE_CCKPD = BIT0,
ODM_RESUME_CCKPD = BIT1
} ODM_Pause_CCKPD_TYPE;
/*
typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition
{
CCK_PD_STAGE_LowRssi = 0,
CCK_PD_STAGE_HighRssi = 1,
CCK_PD_STAGE_MAX = 3,
}DM_CCK_PDTH_E;
typedef enum tag_DIG_EXT_PORT_ALGO_Definition
{
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
}DM_DIG_EXT_PORT_ALG_E;
typedef enum tag_DIG_Connect_Definition
{
DIG_STA_DISCONNECT = 0,
DIG_STA_CONNECT = 1,
DIG_STA_BEFORE_CONNECT = 2,
DIG_MultiSTA_DISCONNECT = 3,
DIG_MultiSTA_CONNECT = 4,
DIG_CONNECT_MAX
}DM_DIG_CONNECT_E;
#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \
DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT)
#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \
DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT)
*/
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
#define DM_FALSEALARM_THRESH_LOW 400
#define DM_FALSEALARM_THRESH_HIGH 1000
#define DM_DIG_MAX_NIC 0x3e
#define DM_DIG_MIN_NIC 0x1e //0x22//0x1c
#define DM_DIG_MAX_OF_MIN_NIC 0x3e
#define DM_DIG_MAX_AP 0x3e
#define DM_DIG_MIN_AP 0x1c
#define DM_DIG_MAX_OF_MIN 0x2A //0x32
#define DM_DIG_MIN_AP_DFS 0x20
#define DM_DIG_MAX_NIC_HP 0x46
#define DM_DIG_MIN_NIC_HP 0x2e
#define DM_DIG_MAX_AP_HP 0x42
#define DM_DIG_MIN_AP_HP 0x30
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#define DM_DIG_MAX_AP_COVERAGR 0x26
#define DM_DIG_MIN_AP_COVERAGE 0x1c
#define DM_DIG_MAX_OF_MIN_COVERAGE 0x22
#define DM_DIG_TP_Target_TH0 500
#define DM_DIG_TP_Target_TH1 1000
#define DM_DIG_TP_Training_Period 10
#endif
//vivi 92c&92d has different definition, 20110504
//this is for 92c
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
#define DM_DIG_FA_TH0 0x80//0x20
#else
#define DM_DIG_FA_TH0 0x200//0x20
#endif
#else
#define DM_DIG_FA_TH0 0x200//0x20
#endif
#define DM_DIG_FA_TH1 0x300
#define DM_DIG_FA_TH2 0x400
//this is for 92d
#define DM_DIG_FA_TH0_92D 0x100
#define DM_DIG_FA_TH1_92D 0x400
#define DM_DIG_FA_TH2_92D 0x600
#define DM_DIG_BACKOFF_MAX 12
#define DM_DIG_BACKOFF_MIN -4
#define DM_DIG_BACKOFF_DEFAULT 10
#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps
#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps
#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps
#define RSSI_OFFSET_DIG 0x05
VOID
ODM_ChangeDynamicInitGainThresh(
IN PVOID pDM_VOID,
IN u4Byte DM_Type,
IN u4Byte DM_Value
);
VOID
ODM_Write_DIG(
IN PVOID pDM_VOID,
IN u1Byte CurrentIGI
);
VOID
odm_PauseDIG(
IN PVOID pDM_VOID,
IN ODM_Pause_DIG_TYPE PauseType,
IN u1Byte IGIValue
);
VOID
odm_DIGInit(
IN PVOID pDM_VOID
);
VOID
odm_DIG(
IN PVOID pDM_VOID
);
VOID
odm_DIGbyRSSI_LPS(
IN PVOID pDM_VOID
);
VOID
odm_FalseAlarmCounterStatistics(
IN PVOID pDM_VOID
);
VOID
odm_PauseCCKPacketDetection(
IN PVOID pDM_VOID,
IN ODM_Pause_CCKPD_TYPE PauseType,
IN u1Byte CCKPDThreshold
);
VOID
odm_CCKPacketDetectionThresh(
IN PVOID pDM_VOID
);
VOID
ODM_Write_CCK_CCA_Thres(
IN PVOID pDM_VOID,
IN u1Byte CurCCK_CCAThres
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
odm_MPT_DIGCallback(
PRT_TIMER pTimer
);
VOID
odm_MPT_DIGWorkItemCallback(
IN PVOID pContext
);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
VOID
odm_MPT_DIGCallback(
IN PVOID pDM_VOID
);
#endif
#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
VOID
ODM_MPT_DIG(
IN PVOID pDM_VOID
);
#endif
#endif

218
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_DynamicBBPowerSaving.c
View File

@ -1,218 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
VOID
odm_DynamicBBPowerSavingInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
pDM_PSTable->PreCCAState = CCA_MAX;
pDM_PSTable->CurCCAState = CCA_MAX;
pDM_PSTable->PreRFState = RF_MAX;
pDM_PSTable->CurRFState = RF_MAX;
pDM_PSTable->Rssi_val_min = 0;
pDM_PSTable->initialize = 0;
}
VOID
odm_DynamicBBPowerSaving(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if (pDM_Odm->SupportICType != ODM_RTL8723A)
return;
if(!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE))
return;
if(!(pDM_Odm->SupportPlatform & (ODM_WIN|ODM_CE)))
return;
//1 2.Power Saving for 92C
if((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R))
{
odm_1R_CCA(pDM_Odm);
}
// 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable.
// 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns.
//1 3.Power Saving for 88C
else
{
ODM_RF_Saving(pDM_Odm, FALSE);
}
#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
}
VOID
odm_1R_CCA(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
if(pDM_Odm->RSSI_Min!= 0xFF)
{
if(pDM_PSTable->PreCCAState == CCA_2R)
{
if(pDM_Odm->RSSI_Min >= 35)
pDM_PSTable->CurCCAState = CCA_1R;
else
pDM_PSTable->CurCCAState = CCA_2R;
}
else{
if(pDM_Odm->RSSI_Min <= 30)
pDM_PSTable->CurCCAState = CCA_2R;
else
pDM_PSTable->CurCCAState = CCA_1R;
}
}
else{
pDM_PSTable->CurCCAState=CCA_MAX;
}
if(pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState)
{
if(pDM_PSTable->CurCCAState == CCA_1R)
{
if( pDM_Odm->RFType ==ODM_2T2R )
{
ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x13);
//PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x20);
}
else
{
ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x23);
//PHY_SetBBReg(pAdapter, 0xe70, 0x7fc00000, 0x10c); // Set RegE70[30:22] = 9b'100001100
}
}
else
{
ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x33);
//PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63);
}
pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState;
}
}
void
ODM_RF_Saving(
IN PVOID pDM_VOID,
IN u1Byte bForceInNormal
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
u1Byte Rssi_Up_bound = 30 ;
u1Byte Rssi_Low_bound = 25;
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV
{
Rssi_Up_bound = 50 ;
Rssi_Low_bound = 45;
}
#endif
if(pDM_PSTable->initialize == 0){
pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3;
pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
//Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord);
pDM_PSTable->initialize = 1;
}
if(!bForceInNormal)
{
if(pDM_Odm->RSSI_Min != 0xFF)
{
if(pDM_PSTable->PreRFState == RF_Normal)
{
if(pDM_Odm->RSSI_Min >= Rssi_Up_bound)
pDM_PSTable->CurRFState = RF_Save;
else
pDM_PSTable->CurRFState = RF_Normal;
}
else{
if(pDM_Odm->RSSI_Min <= Rssi_Low_bound)
pDM_PSTable->CurRFState = RF_Normal;
else
pDM_PSTable->CurRFState = RF_Save;
}
}
else
pDM_PSTable->CurRFState=RF_MAX;
}
else
{
pDM_PSTable->CurRFState = RF_Normal;
}
if(pDM_PSTable->PreRFState != pDM_PSTable->CurRFState)
{
if(pDM_PSTable->CurRFState == RF_Save)
{
// <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode.
// Suggested by SD3 Yu-Nan. 2011.01.20.
if(pDM_Odm->SupportICType == ODM_RTL8723A)
{
ODM_SetBBReg(pDM_Odm, 0x874 , BIT5, 0x1); //Reg874[5]=1b'1
}
ODM_SetBBReg(pDM_Odm, 0x874 , 0x1C0000, 0x2); //Reg874[20:18]=3'b010
ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0
ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63
ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10
ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3
ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0
ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1
}
else
{
ODM_SetBBReg(pDM_Odm, 0x874 , 0x1CC000, pDM_PSTable->Reg874);
ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70);
ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0);
if(pDM_Odm->SupportICType == ODM_RTL8723A)
{
ODM_SetBBReg(pDM_Odm,0x874 , BIT5, 0x0); //Reg874[5]=1b'0
}
}
pDM_PSTable->PreRFState =pDM_PSTable->CurRFState;
}
#endif
}

63
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_DynamicBBPowerSaving.h
View File

@ -1,63 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMDYNAMICBBPOWERSAVING_H__
#define __PHYDMDYNAMICBBPOWERSAVING_H__
#define DYNAMIC_BBPWRSAV_VERSION "1.0"
typedef struct _Dynamic_Power_Saving_
{
u1Byte PreCCAState;
u1Byte CurCCAState;
u1Byte PreRFState;
u1Byte CurRFState;
int Rssi_val_min;
u1Byte initialize;
u4Byte Reg874,RegC70,Reg85C,RegA74;
}PS_T,*pPS_T;
#define dm_RF_Saving ODM_RF_Saving
void ODM_RF_Saving(
IN PVOID pDM_VOID,
IN u1Byte bForceInNormal
);
VOID
odm_DynamicBBPowerSavingInit(
IN PVOID pDM_VOID
);
VOID
odm_DynamicBBPowerSaving(
IN PVOID pDM_VOID
);
VOID
odm_1R_CCA(
IN PVOID pDM_VOID
);
#endif

882
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_DynamicTxPower.c
View File

@ -1,882 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
VOID
odm_DynamicTxPowerInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
#if DEV_BUS_TYPE==RT_USB_INTERFACE
if(RT_GetInterfaceSelection(Adapter) == INTF_SEL1_USB_High_Power)
{
odm_DynamicTxPowerSavePowerIndex(pDM_Odm);
pMgntInfo->bDynamicTxPowerEnable = TRUE;
}
else
#else
//so 92c pci do not need dynamic tx power? vivi check it later
if(IS_HARDWARE_TYPE_8192D(Adapter))
pMgntInfo->bDynamicTxPowerEnable = TRUE;
else
pMgntInfo->bDynamicTxPowerEnable = FALSE;
#endif
pHalData->LastDTPLvl = TxHighPwrLevel_Normal;
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
pdmpriv->bDynamicTxPowerEnable = _FALSE;
#if (RTL8192C_SUPPORT==1)
#ifdef CONFIG_USB_HCI
#ifdef CONFIG_INTEL_PROXIM
if((pHalData->BoardType == BOARD_USB_High_PA)||(Adapter->proximity.proxim_support==_TRUE))
#else
if(pHalData->BoardType == BOARD_USB_High_PA)
#endif
{
//odm_SavePowerIndex(Adapter);
odm_DynamicTxPowerSavePowerIndex(pDM_Odm);
pdmpriv->bDynamicTxPowerEnable = _TRUE;
}
else
#else
pdmpriv->bDynamicTxPowerEnable = _FALSE;
#endif
#endif
pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
#endif
}
VOID
odm_DynamicTxPowerSavePowerIndex(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
u1Byte index;
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
for(index = 0; index< 6; index++)
pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
for(index = 0; index< 6; index++)
pdmpriv->PowerIndex_backup[index] = rtw_read8(Adapter, Power_Index_REG[index]);
#endif
#endif
}
VOID
odm_DynamicTxPowerRestorePowerIndex(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
u1Byte index;
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
for(index = 0; index< 6; index++)
PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], pHalData->PowerIndex_backup[index]);
#elif(DM_ODM_SUPPORT_TYPE == ODM_CE)
struct dm_priv *pdmpriv = &pHalData->dmpriv;
for(index = 0; index< 6; index++)
rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]);
#endif
#endif
}
VOID
odm_DynamicTxPowerWritePowerIndex(
IN PVOID pDM_VOID,
IN u1Byte Value)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u1Byte index;
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
for(index = 0; index< 6; index++)
//PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value);
ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value);
}
VOID
odm_DynamicTxPower(
IN PVOID pDM_VOID
)
{
//
// For AP/ADSL use prtl8192cd_priv
// For CE/NIC use PADAPTER
//
//PADAPTER pAdapter = pDM_Odm->Adapter;
// prtl8192cd_priv priv = pDM_Odm->priv;
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
return;
//
// 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
// at the same time. In the stage2/3, we need to prive universal interface and merge all
// HW dynamic mechanism.
//
switch (pDM_Odm->SupportPlatform)
{
case ODM_WIN:
case ODM_CE:
odm_DynamicTxPowerNIC(pDM_Odm);
break;
case ODM_AP:
odm_DynamicTxPowerAP(pDM_Odm);
break;
case ODM_ADSL:
//odm_DIGAP(pDM_Odm);
break;
}
}
VOID
odm_DynamicTxPowerNIC(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
return;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(pDM_Odm->SupportICType == ODM_RTL8192C)
{
odm_DynamicTxPower_92C(pDM_Odm);
}
else if(pDM_Odm->SupportICType == ODM_RTL8192D)
{
odm_DynamicTxPower_92D(pDM_Odm);
}
else if (pDM_Odm->SupportICType == ODM_RTL8821)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(Adapter);
if (pMgntInfo->RegRspPwr == 1)
{
if(pDM_Odm->RSSI_Min > 60)
{
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 1); // Resp TXAGC offset = -3dB
}
else if(pDM_Odm->RSSI_Min < 55)
{
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 0); // Resp TXAGC offset = 0dB
}
}
#endif
}
#endif
}
VOID
odm_DynamicTxPowerAP(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
//#if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1))
prtl8192cd_priv priv = pDM_Odm->priv;
s4Byte i;
s2Byte pwr_thd = TX_POWER_NEAR_FIELD_THRESH_AP;
if(!priv->pshare->rf_ft_var.tx_pwr_ctrl)
return;
#if ((RTL8812E_SUPPORT==1) || (RTL8881A_SUPPORT==1))
if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8881A))
pwr_thd = TX_POWER_NEAR_FIELD_THRESH_8812;
#endif
#if defined(CONFIG_RTL_92D_SUPPORT) || defined(CONFIG_RTL_92C_SUPPORT)
if(CHIP_VER_92X_SERIES(priv))
{
#ifdef HIGH_POWER_EXT_PA
if(pDM_Odm->ExtPA)
tx_power_control(priv);
#endif
}
#endif
/*
* Check if station is near by to use lower tx power
*/
if ((priv->up_time % 3) == 0 ) {
int disable_pwr_ctrl = ((pDM_Odm->FalseAlmCnt.Cnt_all > 1000 ) || ((pDM_Odm->FalseAlmCnt.Cnt_all > 300 ) && ((RTL_R8(0xc50) & 0x7f) >= 0x32))) ? 1 : 0;
for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
if(IS_STA_VALID(pstat) ) {
if(disable_pwr_ctrl)
pstat->hp_level = 0;
else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd))
pstat->hp_level = 1;
else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd-8)))
pstat->hp_level = 0;
}
}
#if defined(CONFIG_WLAN_HAL_8192EE)
if (GET_CHIP_VER(priv) == VERSION_8192E) {
if( !disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff) ) {
if(pDM_Odm->RSSI_Min > pwr_thd)
RRSR_power_control_11n(priv, 1 );
else if(pDM_Odm->RSSI_Min < (pwr_thd-8))
RRSR_power_control_11n(priv, 0 );
} else {
RRSR_power_control_11n(priv, 0 );
}
}
#endif
}
//#endif
#endif
}
VOID
odm_DynamicTxPower_92C(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
s4Byte UndecoratedSmoothedPWDB;
// 2012/01/12 MH According to Luke's suggestion, only high power will support the feature.
if (pDM_Odm->ExtPA == FALSE)
return;
// STA not connected and AP not connected
if((!pMgntInfo->bMediaConnect) &&
(pHalData->EntryMinUndecoratedSmoothedPWDB == 0))
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any \n"));
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
//the LastDTPlvl should reset when disconnect,
//otherwise the tx power level wouldn't change when disconnect and connect again.
// Maddest 20091220.
pHalData->LastDTPLvl=TxHighPwrLevel_Normal;
return;
}
#if (INTEL_PROXIMITY_SUPPORT == 1)
// Intel set fixed tx power
if(pMgntInfo->IntelProximityModeInfo.PowerOutput > 0)
{
switch(pMgntInfo->IntelProximityModeInfo.PowerOutput){
case 1:
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_100\n"));
break;
case 2:
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_70;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_70\n"));
break;
case 3:
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_50;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_50\n"));
break;
case 4:
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_35;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_35\n"));
break;
case 5:
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_15;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_15\n"));
break;
default:
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_100\n"));
break;
}
}
else
#endif
{
if( (pMgntInfo->bDynamicTxPowerEnable != TRUE) ||
pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
}
else
{
if(pMgntInfo->bMediaConnect) // Default port
{
if(ACTING_AS_AP(Adapter) || ACTING_AS_IBSS(Adapter))
{
UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
else
{
UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
}
else // associated entry pwdb
{
UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
}
else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
}
else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
}
}
}
if( pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl )
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192C() Channel = %d \n" , pHalData->CurrentChannel));
PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
if( (pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) &&
(pHalData->LastDTPLvl == TxHighPwrLevel_Level1 || pHalData->LastDTPLvl == TxHighPwrLevel_Level2)) //TxHighPwrLevel_Normal
odm_DynamicTxPowerRestorePowerIndex(pDM_Odm);
else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14);
else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10);
}
pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#if (RTL8192C_SUPPORT==1)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
int UndecoratedSmoothedPWDB;
if(!pdmpriv->bDynamicTxPowerEnable)
return;
#ifdef CONFIG_INTEL_PROXIM
if(Adapter->proximity.proxim_on== _TRUE){
struct proximity_priv *prox_priv=Adapter->proximity.proximity_priv;
// Intel set fixed tx power
printk("\n %s Adapter->proximity.proxim_on=%d prox_priv->proxim_modeinfo->power_output=%d \n",__FUNCTION__,Adapter->proximity.proxim_on,prox_priv->proxim_modeinfo->power_output);
if(prox_priv!=NULL){
if(prox_priv->proxim_modeinfo->power_output> 0)
{
switch(prox_priv->proxim_modeinfo->power_output)
{
case 1:
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
printk("TxHighPwrLevel_100\n");
break;
case 2:
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_70;
printk("TxHighPwrLevel_70\n");
break;
case 3:
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_50;
printk("TxHighPwrLevel_50\n");
break;
case 4:
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_35;
printk("TxHighPwrLevel_35\n");
break;
case 5:
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_15;
printk("TxHighPwrLevel_15\n");
break;
default:
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
printk("TxHighPwrLevel_100\n");
break;
}
}
}
}
else
#endif
{
// STA not connected and AP not connected
if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) &&
(pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
{
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
//the LastDTPlvl should reset when disconnect,
//otherwise the tx power level wouldn't change when disconnect and connect again.
// Maddest 20091220.
pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal;
return;
}
if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port
{
#if 0
//todo: AP Mode
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
else
{
UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
#else
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
#endif
}
else // associated entry pwdb
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
}
else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
}
else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
}
}
if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) )
{
PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) // HP1 -> Normal or HP2 -> Normal
odm_DynamicTxPowerRestorePowerIndex(pDM_Odm);
else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14);
else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10);
}
pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl;
#endif
#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
}
VOID
odm_DynamicTxPower_92D(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
s4Byte UndecoratedSmoothedPWDB;
PADAPTER BuddyAdapter = Adapter->BuddyAdapter;
BOOLEAN bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(Adapter);
u1Byte HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1;
// 2012/01/12 MH According to Luke's suggestion, only high power will support the feature.
if (pDM_Odm->ExtPA == FALSE)
return;
// If dynamic high power is disabled.
if( (pMgntInfo->bDynamicTxPowerEnable != TRUE) ||
pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
return;
}
// STA not connected and AP not connected
if((!pMgntInfo->bMediaConnect) &&
(pHalData->EntryMinUndecoratedSmoothedPWDB == 0))
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any \n"));
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
//the LastDTPlvl should reset when disconnect,
//otherwise the tx power level wouldn't change when disconnect and connect again.
// Maddest 20091220.
pHalData->LastDTPLvl=TxHighPwrLevel_Normal;
return;
}
if(pMgntInfo->bMediaConnect) // Default port
{
if(ACTING_AS_AP(Adapter) || pMgntInfo->mIbss)
{
UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
else
{
UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
}
else // associated entry pwdb
{
UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
if(IS_HARDWARE_TYPE_8192D(Adapter) && GET_HAL_DATA(Adapter)->CurrentBandType == 1){
if(UndecoratedSmoothedPWDB >= 0x33)
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n"));
}
else if((UndecoratedSmoothedPWDB <0x33) &&
(UndecoratedSmoothedPWDB >= 0x2b) )
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
}
else if(UndecoratedSmoothedPWDB < 0x2b)
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n"));
}
}
else
{
if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
}
else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
}
else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
{
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
}
}
//sherry delete flag 20110517
if(bGetValueFromBuddyAdapter)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1 \n"));
if(Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() change value \n"));
HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl;
pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP;
PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0;
Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = FALSE;
}
}
if( (pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl) )
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d \n" , pHalData->CurrentChannel));
if(Adapter->DualMacSmartConcurrent == TRUE)
{
if(BuddyAdapter == NULL)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case \n"));
if(!Adapter->bSlaveOfDMSP)
{
PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
}
}
else
{
if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP \n"));
if(Adapter->bSlaveOfDMSP)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() bslave case \n"));
BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = TRUE;
BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl;
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() master case \n"));
if(!bGetValueFromBuddyAdapter)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0 \n"));
PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
}
}
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n"));
PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
}
}
}
else
{
PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
}
}
pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#if (RTL8192D_SUPPORT==1)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
DM_ODM_T *podmpriv = &pHalData->odmpriv;
int UndecoratedSmoothedPWDB;
#if (RTL8192D_EASY_SMART_CONCURRENT == 1)
PADAPTER BuddyAdapter = Adapter->BuddyAdapter;
BOOLEAN bGetValueFromBuddyAdapter = DualMacGetParameterFromBuddyAdapter(Adapter);
u8 HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1;
#endif
// If dynamic high power is disabled.
if( (pdmpriv->bDynamicTxPowerEnable != _TRUE) ||
(!(podmpriv->SupportAbility& ODM_BB_DYNAMIC_TXPWR)) )
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
return;
}
// STA not connected and AP not connected
if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) &&
(pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
{
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
//the LastDTPlvl should reset when disconnect,
//otherwise the tx power level wouldn't change when disconnect and connect again.
// Maddest 20091220.
pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal;
return;
}
if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port
{
#if 0
//todo: AP Mode
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
else
{
UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
#else
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
#endif
}
else // associated entry pwdb
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
#if TX_POWER_FOR_5G_BAND == 1
if(pHalData->CurrentBandType92D == BAND_ON_5G){
if(UndecoratedSmoothedPWDB >= 0x33)
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n"));
}
else if((UndecoratedSmoothedPWDB <0x33) &&
(UndecoratedSmoothedPWDB >= 0x2b) )
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
}
else if(UndecoratedSmoothedPWDB < 0x2b)
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n"));
}
}
else
#endif
{
if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
}
else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
}
else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
{
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
}
}
#if (RTL8192D_EASY_SMART_CONCURRENT == 1)
if(bGetValueFromBuddyAdapter)
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1 \n"));
if(Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP)
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() change value \n"));
HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl;
pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP;
PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0;
Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = _FALSE;
}
}
#endif
if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) )
{
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d \n" , pHalData->CurrentChannel));
#if (RTL8192D_EASY_SMART_CONCURRENT == 1)
if(BuddyAdapter == NULL)
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case \n"));
if(!Adapter->bSlaveOfDMSP)
{
PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
}
}
else
{
if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP \n"));
if(Adapter->bSlaveOfDMSP)
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() bslave case \n"));
BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = _TRUE;
BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl;
}
else
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() master case \n"));
if(!bGetValueFromBuddyAdapter)
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0 \n"));
PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
}
}
}
else
{
//ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n"));
PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
}
}
#else
PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
#endif
}
pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl;
#endif
#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
}

89
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_DynamicTxPower.h
View File

@ -1,89 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMDYNAMICTXPOWER_H__
#define __PHYDMDYNAMICTXPOWER_H__
#define DYNAMIC_TXPWR_VERSION "1.0"
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
#define TX_POWER_NEAR_FIELD_THRESH_8812 60
#define TxHighPwrLevel_Normal 0
#define TxHighPwrLevel_Level1 1
#define TxHighPwrLevel_Level2 2
#define TxHighPwrLevel_BT1 3
#define TxHighPwrLevel_BT2 4
#define TxHighPwrLevel_15 5
#define TxHighPwrLevel_35 6
#define TxHighPwrLevel_50 7
#define TxHighPwrLevel_70 8
#define TxHighPwrLevel_100 9
VOID
odm_DynamicTxPowerInit(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerRestorePowerIndex(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerNIC(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
odm_DynamicTxPowerSavePowerIndex(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerWritePowerIndex(
IN PVOID pDM_VOID,
IN u1Byte Value);
VOID
odm_DynamicTxPower_92C(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPower_92D(
IN PVOID pDM_VOID
);
#endif
VOID
odm_DynamicTxPower(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerAP(
IN PVOID pDM_VOID
);
#endif

1915
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_EdcaTurboCheck.c
View File

File diff suppressed because it is too large Load Diff

152
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_EdcaTurboCheck.h
View File

@ -1,152 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMEDCATURBOCHECK_H__
#define __PHYDMEDCATURBOCHECK_H__
#define EDCATURBO_VERSION "1.0"
typedef struct _EDCA_TURBO_
{
BOOLEAN bCurrentTurboEDCA;
BOOLEAN bIsCurRDLState;
#if(DM_ODM_SUPPORT_TYPE == ODM_CE )
u4Byte prv_traffic_idx; // edca turbo
#endif
}EDCA_T,*pEDCA_T;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU MARVELL 92U_AP SELF_AP(DownLink/Tx)
{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP(UpLink/Rx)
{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP
{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
//============================================================
// EDCA Paramter for AP/ADSL by Mingzhi 2011-11-22
//============================================================
#elif (DM_ODM_SUPPORT_TYPE &ODM_ADSL)
enum qos_prio { BK, BE, VI, VO, VI_AG, VO_AG };
static const struct ParaRecord rtl_ap_EDCA[] =
{
//ACM,AIFSN, ECWmin, ECWmax, TXOplimit
{0, 7, 4, 10, 0}, //BK
{0, 3, 4, 6, 0}, //BE
{0, 1, 3, 4, 188}, //VI
{0, 1, 2, 3, 102}, //VO
{0, 1, 3, 4, 94}, //VI_AG
{0, 1, 2, 3, 47}, //VO_AG
};
static const struct ParaRecord rtl_sta_EDCA[] =
{
//ACM,AIFSN, ECWmin, ECWmax, TXOplimit
{0, 7, 4, 10, 0},
{0, 3, 4, 10, 0},
{0, 2, 3, 4, 188},
{0, 2, 2, 3, 102},
{0, 2, 3, 4, 94},
{0, 2, 2, 3, 47},
};
#endif
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#ifdef WIFI_WMM
VOID
ODM_IotEdcaSwitch(
IN PVOID pDM_VOID,
IN unsigned char enable
);
#endif
BOOLEAN
ODM_ChooseIotMainSTA(
IN PVOID pDM_VOID,
IN PSTA_INFO_T pstat
);
#endif
VOID
odm_EdcaTurboCheck(
IN PVOID pDM_VOID
);
VOID
ODM_EdcaTurboInit(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
VOID
odm_EdcaTurboCheckMP(
IN PVOID pDM_VOID
);
//check if edca turbo is disabled
BOOLEAN
odm_IsEdcaTurboDisable(
IN PVOID pDM_VOID
);
//choose edca paramter for special IOT case
VOID
ODM_EdcaParaSelByIot(
IN PVOID pDM_VOID,
OUT u4Byte *EDCA_BE_UL,
OUT u4Byte *EDCA_BE_DL
);
//check if it is UL or DL
VOID
odm_EdcaChooseTrafficIdx(
IN PVOID pDM_VOID,
IN u8Byte cur_tx_bytes,
IN u8Byte cur_rx_bytes,
IN BOOLEAN bBiasOnRx,
OUT BOOLEAN *pbIsCurRDLState
);
#elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
VOID
odm_EdcaTurboCheckCE(
IN PVOID pDM_VOID
);
#else
VOID
odm_IotEngine(
IN PVOID pDM_VOID
);
VOID
odm_EdcaParaInit(
IN PVOID pDM_VOID
);
#endif
#endif

2362
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_HWConfig.c
View File

File diff suppressed because it is too large Load Diff

237
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_HWConfig.h
View File

@ -1,237 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALHWOUTSRC_H__
#define __HALHWOUTSRC_H__
/*--------------------------Define -------------------------------------------*/
//#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \
sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \
sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
#define AGC_DIFF_CONFIG(ic, band) do {\
if (pDM_Odm->bIsMPChip)\
AGC_DIFF_CONFIG_MP(ic,band);\
else\
AGC_DIFF_CONFIG_TC(ic,band);\
} while(0)
//============================================================
// structure and define
//============================================================
typedef struct _Phy_Rx_AGC_Info
{
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte gain:7,trsw:1;
#else
u1Byte trsw:1,gain:7;
#endif
} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T;
typedef struct _Phy_Status_Rpt_8192cd
{
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_corr[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_rpt_b_ofdm_cfosho_b;
u1Byte rsvd_1;//ch_corr_msb;
u1Byte noise_power_db_msb;
s1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte noise_power_db_lsb;
u1Byte rsvd_2[3];
u1Byte stream_csi[2];
u1Byte stream_target_csi[2];
s1Byte sig_evm;
u1Byte rsvd_3;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
u1Byte sgi_en:1;
u1Byte rxsc:2;
u1Byte idle_long:1;
u1Byte r_ant_train_en:1;
u1Byte ant_sel_b:1;
u1Byte ant_sel:1;
#else // _BIG_ENDIAN_
u1Byte ant_sel:1;
u1Byte ant_sel_b:1;
u1Byte r_ant_train_en:1;
u1Byte idle_long:1;
u1Byte rxsc:2;
u1Byte sgi_en:1;
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
#endif
} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
typedef struct _Phy_Status_Rpt_8812
{
#if 0
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_num[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_bb_pwr_ofdm_cfosho_b;
u1Byte cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition)
u1Byte rsvd_1;
u1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte rsvd_2[2];
u1Byte stream_snr[2];
u1Byte stream_csi[2];
u1Byte rsvd_3[2];
s1Byte sig_evm;
u1Byte rsvd_4;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antidx_anta:3;
u1Byte antidx_antb:3;
u1Byte rsvd_5:2;
#else // _BIG_ENDIAN_
u1Byte rsvd_5:2;
u1Byte antidx_antb:3;
u1Byte antidx_anta:3;
#endif
#endif
//2012.05.24 LukeLee: This structure should take big/little endian in consideration later.....
//DWORD 0
u1Byte gain_trsw[2];
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u2Byte chl_num:10;
u2Byte sub_chnl:4;
u2Byte r_RFMOD:2;
#else // _BIG_ENDIAN_
u2Byte r_RFMOD:2;
u2Byte sub_chnl:4;
u2Byte chl_num:10;
#endif
//DWORD 1
u1Byte pwdb_all;
u1Byte cfosho[4]; // DW 1 byte 1 DW 2 byte 0
//DWORD 2
s1Byte cfotail[4]; // DW 2 byte 1 DW 3 byte 0
//DWORD 3
s1Byte rxevm[2]; // DW 3 byte 1 DW 3 byte 2
s1Byte rxsnr[2]; // DW 3 byte 3 DW 4 byte 0
//DWORD 4
u1Byte PCTS_MSK_RPT[2];
u1Byte pdsnr[2]; // DW 4 byte 3 DW 5 Byte 0
//DWORD 5
u1Byte csi_current[2];
u1Byte rx_gain_c;
//DWORD 6
u1Byte rx_gain_d;
s1Byte sigevm;
u1Byte resvd_0;
u1Byte antidx_anta:3;
u1Byte antidx_antb:3;
u1Byte resvd_1:2;
} PHY_STATUS_RPT_8812_T,*PPHY_STATUS_RPT_8812_T;
VOID
odm_Init_RSSIForDM(
IN OUT PDM_ODM_T pDM_Odm
);
VOID
ODM_PhyStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
);
VOID
ODM_MacStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
IN pu1Byte pMacStatus,
IN u1Byte MacID,
IN BOOLEAN bPacketMatchBSSID,
IN BOOLEAN bPacketToSelf,
IN BOOLEAN bPacketBeacon
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP))
HAL_STATUS
ODM_ConfigRFWithTxPwrTrackHeaderFile(
IN PDM_ODM_T pDM_Odm
);
HAL_STATUS
ODM_ConfigRFWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_Config_Type ConfigType,
IN ODM_RF_RADIO_PATH_E eRFPath
);
HAL_STATUS
ODM_ConfigBBWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_BB_Config_Type ConfigType
);
HAL_STATUS
ODM_ConfigMACWithHeaderFile(
IN PDM_ODM_T pDM_Odm
);
HAL_STATUS
ODM_ConfigFWWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_FW_Config_Type ConfigType,
OUT u1Byte *pFirmware,
OUT u4Byte *pSize
);
u4Byte
ODM_GetHWImgVersion(
IN PDM_ODM_T pDM_Odm
);
s4Byte
odm_SignalScaleMapping(
IN OUT PDM_ODM_T pDM_Odm,
IN s4Byte CurrSig
);
#endif
#endif

197
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_NoiseMonitor.c
View File

@ -1,197 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
//#include "Mp_Precomp.h"
#include "phydm_precomp.h"
//=================================================
// This function is for inband noise test utility only
// To obtain the inband noise level(dbm), do the following.
// 1. disable DIG and Power Saving
// 2. Set initial gain = 0x1a
// 3. Stop updating idle time pwer report (for driver read)
// - 0x80c[25]
//
//=================================================
#define Valid_Min -35
#define Valid_Max 10
#define ValidCnt 5
s2Byte odm_InbandNoise_Monitor_NSeries(PDM_ODM_T pDM_Odm,u8 bPauseDIG,u8 IGIValue,u32 max_time)
{
u4Byte tmp4b;
u1Byte max_rf_path=0,rf_path;
u1Byte reg_c50, reg_c58,valid_done=0;
struct noise_level noise_data;
u32 start = 0, func_start=0, func_end = 0;
func_start = ODM_GetCurrentTime(pDM_Odm);
pDM_Odm->noise_level.noise_all = 0;
if((pDM_Odm->RFType == ODM_1T2R) ||(pDM_Odm->RFType == ODM_2T2R))
max_rf_path = 2;
else
max_rf_path = 1;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("odm_DebugControlInbandNoise_Nseries() ==> \n"));
ODM_Memory_Set(pDM_Odm,&noise_data,0,sizeof(struct noise_level));
//
// Step 1. Disable DIG && Set initial gain.
//
if(bPauseDIG)
{
odm_PauseDIG(pDM_Odm,ODM_PAUSE_DIG,IGIValue);
}
//
// Step 2. Disable all power save for read registers
//
//dcmd_DebugControlPowerSave(pAdapter, PSDisable);
//
// Step 3. Get noise power level
//
start = ODM_GetCurrentTime(pDM_Odm);
while(1)
{
//Stop updating idle time pwer report (for driver read)
ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 1);
//Read Noise Floor Report
tmp4b = ODM_GetBBReg(pDM_Odm, 0x8f8,bMaskDWord );
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b));
//ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, TestInitialGain);
//if(max_rf_path == 2)
// ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, TestInitialGain);
//update idle time pwer report per 5us
ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 0);
noise_data.value[ODM_RF_PATH_A] = (u1Byte)(tmp4b&0xff);
noise_data.value[ODM_RF_PATH_B] = (u1Byte)((tmp4b&0xff00)>>8);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n",
noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_B], noise_data.value[ODM_RF_PATH_B]));
for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++)
{
noise_data.sval[rf_path] = (s1Byte)noise_data.value[rf_path];
noise_data.sval[rf_path] /= 2;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("sval_a = %d, sval_b = %d\n",
noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B]));
//ODM_delay_ms(10);
//ODM_sleep_ms(10);
for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++)
{
if( (noise_data.valid_cnt[rf_path] < ValidCnt) && (noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min))
{
noise_data.valid_cnt[rf_path]++;
noise_data.sum[rf_path] += noise_data.sval[rf_path];
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("RF_Path:%d Valid sval = %d\n", rf_path,noise_data.sval[rf_path]));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Sum of sval = %d, \n", noise_data.sum[rf_path]));
if(noise_data.valid_cnt[rf_path] == ValidCnt)
{
valid_done++;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("After divided, RF_Path:%d ,sum = %d \n", rf_path,noise_data.sum[rf_path]));
}
}
}
//printk("####### valid_done:%d #############\n",valid_done);
if ((valid_done==max_rf_path) || (ODM_GetProgressingTime(pDM_Odm,start) > max_time))
{
for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++)
{
//printk("%s PATH_%d - sum = %d, valid_cnt = %d \n",__FUNCTION__,rf_path,noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]);
if(noise_data.valid_cnt[rf_path])
noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path];
else
noise_data.sum[rf_path] = 0;
}
break;
}
}
reg_c50 = (s4Byte)ODM_GetBBReg(pDM_Odm,rOFDM0_XAAGCCore1,bMaskByte0);
reg_c50 &= ~BIT7;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("0x%x = 0x%02x(%d)\n", rOFDM0_XAAGCCore1, reg_c50, reg_c50));
pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = -110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A];
pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A];
if(max_rf_path == 2){
reg_c58 = (s4Byte)ODM_GetBBReg(pDM_Odm,rOFDM0_XBAGCCore1,bMaskByte0);
reg_c58 &= ~BIT7;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("0x%x = 0x%02x(%d)\n", rOFDM0_XBAGCCore1, reg_c58, reg_c58));
pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = -110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B];
pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B];
}
pDM_Odm->noise_level.noise_all /= max_rf_path;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("noise_a = %d, noise_b = %d\n",
pDM_Odm->noise_level.noise[ODM_RF_PATH_A],
pDM_Odm->noise_level.noise[ODM_RF_PATH_B]));
//
// Step 4. Recover the Dig
//
if(bPauseDIG)
{
odm_PauseDIG(pDM_Odm,ODM_RESUME_DIG,IGIValue);
}
func_end = ODM_GetProgressingTime(pDM_Odm,func_start) ;
//printk("%s noise_a = %d, noise_b = %d noise_all:%d (%d ms)\n",__FUNCTION__,
// pDM_Odm->noise_level.noise[ODM_RF_PATH_A],
// pDM_Odm->noise_level.noise[ODM_RF_PATH_B],
// pDM_Odm->noise_level.noise_all,func_end);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("odm_DebugControlInbandNoise_Nseries() <== \n"));
return pDM_Odm->noise_level.noise_all;
}
s2Byte ODM_InbandNoise_Monitor(PVOID pDM_VOID,u8 bPauseDIG,u8 IGIValue,u32 max_time)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES )
{
//odm_InbandNoise_Monitor_JaguarSeries(pDM_Odm,bPauseDIG,IGIValue,max_time);
return 0;
}
else
{
return odm_InbandNoise_Monitor_NSeries(pDM_VOID,bPauseDIG,IGIValue,max_time);
}
}

49
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_NoiseMonitor.h
View File

@ -1,49 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
*****************************************************************************/
#ifndef __ODMNOISEMONITOR_H__
#define __ODMNOISEMONITOR_H__
#define ODM_MAX_CHANNEL_NUM 38//14+24
struct noise_level
{
//u1Byte value_a, value_b;
u1Byte value[MAX_RF_PATH];
//s1Byte sval_a, sval_b;
s1Byte sval[MAX_RF_PATH];
//s4Byte noise_a=0, noise_b=0,sum_a=0, sum_b=0;
//s4Byte noise[ODM_RF_PATH_MAX];
s4Byte sum[MAX_RF_PATH];
//u1Byte valid_cnt_a=0, valid_cnt_b=0,
u1Byte valid[MAX_RF_PATH];
u1Byte valid_cnt[MAX_RF_PATH];
};
typedef struct _ODM_NOISE_MONITOR_
{
s1Byte noise[MAX_RF_PATH];
s2Byte noise_all;
}ODM_NOISE_MONITOR;
s2Byte ODM_InbandNoise_Monitor(PVOID pDM_VOID,u8 bPauseDIG,u8 IGIValue,u32 max_time);
#endif

1585
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_PathDiv.c
View File

File diff suppressed because it is too large Load Diff

193
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_PathDiv.h
View File

@ -1,193 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMPATHDIV_H__
#define __PHYDMPATHDIV_H__
#define PATHDIV_VERSION "1.0"
VOID
odm_PathDiversityInit(
IN PVOID pDM_VOID
);
VOID
odm_PathDiversity(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
//#define PATHDIV_ENABLE 1
#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi
#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C
typedef struct _PathDiv_Parameter_define_
{
u4Byte org_5g_RegE30;
u4Byte org_5g_RegC14;
u4Byte org_5g_RegCA0;
u4Byte swt_5g_RegE30;
u4Byte swt_5g_RegC14;
u4Byte swt_5g_RegCA0;
//for 2G IQK information
u4Byte org_2g_RegC80;
u4Byte org_2g_RegC4C;
u4Byte org_2g_RegC94;
u4Byte org_2g_RegC14;
u4Byte org_2g_RegCA0;
u4Byte swt_2g_RegC80;
u4Byte swt_2g_RegC4C;
u4Byte swt_2g_RegC94;
u4Byte swt_2g_RegC14;
u4Byte swt_2g_RegCA0;
}PATHDIV_PARA,*pPATHDIV_PARA;
VOID
odm_PathDiversityInit_92C(
IN PADAPTER Adapter
);
VOID
odm_2TPathDiversityInit_92C(
IN PADAPTER Adapter
);
VOID
odm_1TPathDiversityInit_92C(
IN PADAPTER Adapter
);
BOOLEAN
odm_IsConnected_92C(
IN PADAPTER Adapter
);
BOOLEAN
ODM_PathDiversityBeforeLink92C(
//IN PADAPTER Adapter
IN PDM_ODM_T pDM_Odm
);
VOID
odm_PathDiversityAfterLink_92C(
IN PADAPTER Adapter
);
VOID
odm_SetRespPath_92C(
IN PADAPTER Adapter,
IN u1Byte DefaultRespPath
);
VOID
odm_OFDMTXPathDiversity_92C(
IN PADAPTER Adapter
);
VOID
odm_CCKTXPathDiversity_92C(
IN PADAPTER Adapter
);
VOID
odm_ResetPathDiversity_92C(
IN PADAPTER Adapter
);
VOID
odm_CCKTXPathDiversityCallback(
PRT_TIMER pTimer
);
VOID
odm_CCKTXPathDiversityWorkItemCallback(
IN PVOID pContext
);
VOID
odm_PathDivChkAntSwitchCallback(
PRT_TIMER pTimer
);
VOID
odm_PathDivChkAntSwitchWorkitemCallback(
IN PVOID pContext
);
VOID
odm_PathDivChkAntSwitch(
PDM_ODM_T pDM_Odm
);
VOID
ODM_CCKPathDiversityChkPerPktRssi(
PADAPTER Adapter,
BOOLEAN bIsDefPort,
BOOLEAN bMatchBSSID,
PRT_WLAN_STA pEntry,
PRT_RFD pRfd,
pu1Byte pDesc
);
VOID
ODM_PathDivChkPerPktRssi(
PADAPTER Adapter,
BOOLEAN bIsDefPort,
BOOLEAN bMatchBSSID,
PRT_WLAN_STA pEntry,
PRT_RFD pRfd
);
VOID
ODM_PathDivRestAfterLink(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_FillTXPathInTXDESC(
IN PADAPTER Adapter,
IN PRT_TCB pTcb,
IN pu1Byte pDesc
);
VOID
odm_PathDivInit_92D(
IN PDM_ODM_T pDM_Odm
);
u1Byte
odm_SwAntDivSelectScanChnl(
IN PADAPTER Adapter
);
VOID
odm_SwAntDivConstructScanChnl(
IN PADAPTER Adapter,
IN u1Byte ScanChnl
);
#endif //#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
#endif //#ifndef __ODMPATHDIV_H__

687
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_PowerTracking.c
View File

@ -1,687 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
//============================================================
// Global var
//============================================================
u4Byte OFDMSwingTable[OFDM_TABLE_SIZE] = {
0x7f8001fe, // 0, +6.0dB
0x788001e2, // 1, +5.5dB
0x71c001c7, // 2, +5.0dB
0x6b8001ae, // 3, +4.5dB
0x65400195, // 4, +4.0dB
0x5fc0017f, // 5, +3.5dB
0x5a400169, // 6, +3.0dB
0x55400155, // 7, +2.5dB
0x50800142, // 8, +2.0dB
0x4c000130, // 9, +1.5dB
0x47c0011f, // 10, +1.0dB
0x43c0010f, // 11, +0.5dB
0x40000100, // 12, +0dB
0x3c8000f2, // 13, -0.5dB
0x390000e4, // 14, -1.0dB
0x35c000d7, // 15, -1.5dB
0x32c000cb, // 16, -2.0dB
0x300000c0, // 17, -2.5dB
0x2d4000b5, // 18, -3.0dB
0x2ac000ab, // 19, -3.5dB
0x288000a2, // 20, -4.0dB
0x26000098, // 21, -4.5dB
0x24000090, // 22, -5.0dB
0x22000088, // 23, -5.5dB
0x20000080, // 24, -6.0dB
0x1e400079, // 25, -6.5dB
0x1c800072, // 26, -7.0dB
0x1b00006c, // 27. -7.5dB
0x19800066, // 28, -8.0dB
0x18000060, // 29, -8.5dB
0x16c0005b, // 30, -9.0dB
0x15800056, // 31, -9.5dB
0x14400051, // 32, -10.0dB
0x1300004c, // 33, -10.5dB
0x12000048, // 34, -11.0dB
0x11000044, // 35, -11.5dB
0x10000040, // 36, -12.0dB
};
u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB <== default
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB
};
u1Byte CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = {
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB <== default
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB
};
u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE] = {
0x0b40002d, // 0, -15.0dB
0x0c000030, // 1, -14.5dB
0x0cc00033, // 2, -14.0dB
0x0d800036, // 3, -13.5dB
0x0e400039, // 4, -13.0dB
0x0f00003c, // 5, -12.5dB
0x10000040, // 6, -12.0dB
0x11000044, // 7, -11.5dB
0x12000048, // 8, -11.0dB
0x1300004c, // 9, -10.5dB
0x14400051, // 10, -10.0dB
0x15800056, // 11, -9.5dB
0x16c0005b, // 12, -9.0dB
0x18000060, // 13, -8.5dB
0x19800066, // 14, -8.0dB
0x1b00006c, // 15, -7.5dB
0x1c800072, // 16, -7.0dB
0x1e400079, // 17, -6.5dB
0x20000080, // 18, -6.0dB
0x22000088, // 19, -5.5dB
0x24000090, // 20, -5.0dB
0x26000098, // 21, -4.5dB
0x288000a2, // 22, -4.0dB
0x2ac000ab, // 23, -3.5dB
0x2d4000b5, // 24, -3.0dB
0x300000c0, // 25, -2.5dB
0x32c000cb, // 26, -2.0dB
0x35c000d7, // 27, -1.5dB
0x390000e4, // 28, -1.0dB
0x3c8000f2, // 29, -0.5dB
0x40000100, // 30, +0dB
0x43c0010f, // 31, +0.5dB
0x47c0011f, // 32, +1.0dB
0x4c000130, // 33, +1.5dB
0x50800142, // 34, +2.0dB
0x55400155, // 35, +2.5dB
0x5a400169, // 36, +3.0dB
0x5fc0017f, // 37, +3.5dB
0x65400195, // 38, +4.0dB
0x6b8001ae, // 39, +4.5dB
0x71c001c7, // 40, +5.0dB
0x788001e2, // 41, +5.5dB
0x7f8001fe // 42, +6.0dB
};
u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = {
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 20, -6.0dB
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB
};
u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= {
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB
};
u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] =
{
0x081, // 0, -12.0dB
0x088, // 1, -11.5dB
0x090, // 2, -11.0dB
0x099, // 3, -10.5dB
0x0A2, // 4, -10.0dB
0x0AC, // 5, -9.5dB
0x0B6, // 6, -9.0dB
0x0C0, // 7, -8.5dB
0x0CC, // 8, -8.0dB
0x0D8, // 9, -7.5dB
0x0E5, // 10, -7.0dB
0x0F2, // 11, -6.5dB
0x101, // 12, -6.0dB
0x110, // 13, -5.5dB
0x120, // 14, -5.0dB
0x131, // 15, -4.5dB
0x143, // 16, -4.0dB
0x156, // 17, -3.5dB
0x16A, // 18, -3.0dB
0x180, // 19, -2.5dB
0x197, // 20, -2.0dB
0x1AF, // 21, -1.5dB
0x1C8, // 22, -1.0dB
0x1E3, // 23, -0.5dB
0x200, // 24, +0 dB
0x21E, // 25, +0.5dB
0x23E, // 26, +1.0dB
0x261, // 27, +1.5dB
0x285, // 28, +2.0dB
0x2AB, // 29, +2.5dB
0x2D3, // 30, +3.0dB
0x2FE, // 31, +3.5dB
0x32B, // 32, +4.0dB
0x35C, // 33, +4.5dB
0x38E, // 34, +5.0dB
0x3C4, // 35, +5.5dB
0x3FE // 36, +6.0dB
};
#ifdef AP_BUILD_WORKAROUND
unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = {
/* +6.0dB */ 0x7f8001fe,
/* +5.5dB */ 0x788001e2,
/* +5.0dB */ 0x71c001c7,
/* +4.5dB */ 0x6b8001ae,
/* +4.0dB */ 0x65400195,
/* +3.5dB */ 0x5fc0017f,
/* +3.0dB */ 0x5a400169,
/* +2.5dB */ 0x55400155,
/* +2.0dB */ 0x50800142,
/* +1.5dB */ 0x4c000130,
/* +1.0dB */ 0x47c0011f,
/* +0.5dB */ 0x43c0010f,
/* 0.0dB */ 0x40000100,
/* -0.5dB */ 0x3c8000f2,
/* -1.0dB */ 0x390000e4,
/* -1.5dB */ 0x35c000d7,
/* -2.0dB */ 0x32c000cb,
/* -2.5dB */ 0x300000c0,
/* -3.0dB */ 0x2d4000b5,
/* -3.5dB */ 0x2ac000ab,
/* -4.0dB */ 0x288000a2,
/* -4.5dB */ 0x26000098,
/* -5.0dB */ 0x24000090,
/* -5.5dB */ 0x22000088,
/* -6.0dB */ 0x20000080,
/* -6.5dB */ 0x1a00006c,
/* -7.0dB */ 0x1c800072,
/* -7.5dB */ 0x18000060,
/* -8.0dB */ 0x19800066,
/* -8.5dB */ 0x15800056,
/* -9.0dB */ 0x26c0005b,
/* -9.5dB */ 0x14400051,
/* -10.0dB */ 0x24400051,
/* -10.5dB */ 0x1300004c,
/* -11.0dB */ 0x12000048,
/* -11.5dB */ 0x11000044,
/* -12.0dB */ 0x10000040
};
#endif
VOID
odm_TXPowerTrackingInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
if(!(pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_IC_11N_SERIES)))
return;
#endif
odm_TXPowerTrackingThermalMeterInit(pDM_Odm);
}
u1Byte
getSwingIndex(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u1Byte i = 0;
u4Byte bbSwing;
u4Byte swingTableSize;
pu4Byte pSwingTable;
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B ||
pDM_Odm->SupportICType == ODM_RTL8192E)
{
bbSwing = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, 0xFFC00000);
pSwingTable = OFDMSwingTable_New;
swingTableSize = OFDM_TABLE_SIZE;
} else {
#if ((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1))
if (pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8821)
{
bbSwing = PHY_GetTxBBSwing_8812A(Adapter, pHalData->CurrentBandType, ODM_RF_PATH_A);
pSwingTable = TxScalingTable_Jaguar;
swingTableSize = TXSCALE_TABLE_SIZE;
}
else
#endif
{
bbSwing = 0;
pSwingTable = OFDMSwingTable;
swingTableSize = OFDM_TABLE_SIZE;
}
}
for (i = 0; i < swingTableSize; ++i) {
u4Byte tableValue = pSwingTable[i];
if (tableValue >= 0x100000 )
tableValue >>= 22;
if (bbSwing == tableValue)
break;
}
return i;
}
VOID
odm_TXPowerTrackingThermalMeterInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u1Byte defaultSwingIndex = getSwingIndex(pDM_Odm);
u1Byte p = 0;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if(pDM_Odm->mp_mode == FALSE)
pHalData->TxPowerTrackControl = TRUE;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if (pDM_Odm->SupportICType >= ODM_RTL8188E)
{
pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE;
pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE;
if(pDM_Odm->mp_mode == FALSE)
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;
else
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE;
MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl);
}
else
{
struct dm_priv *pdmpriv = &pHalData->dmpriv;
pdmpriv->bTXPowerTracking = _TRUE;
pdmpriv->TXPowercount = 0;
pdmpriv->bTXPowerTrackingInit = _FALSE;
//#if (MP_DRIVER != 1) //for mp driver, turn off txpwrtracking as default
if(pDM_Odm->mp_mode == FALSE)
pdmpriv->TxPowerTrackControl = _TRUE;
else
pdmpriv->TxPowerTrackControl = _FALSE;
//MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
}
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#ifdef RTL8188E_SUPPORT
{
pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE;
pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE;
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;
}
#endif
#endif
//pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE;
pDM_Odm->RFCalibrateInfo.ThermalValue = pHalData->EEPROMThermalMeter;
pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = pHalData->EEPROMThermalMeter;
pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = pHalData->EEPROMThermalMeter;
// The index of "0 dB" in SwingTable.
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B ||
pDM_Odm->SupportICType == ODM_RTL8192E)
{
pDM_Odm->DefaultOfdmIndex = (defaultSwingIndex >= OFDM_TABLE_SIZE) ? 30 : defaultSwingIndex;
pDM_Odm->DefaultCckIndex = 20;
}
else
{
pDM_Odm->DefaultOfdmIndex = (defaultSwingIndex >= TXSCALE_TABLE_SIZE) ? 24 : defaultSwingIndex;
pDM_Odm->DefaultCckIndex = 24;
}
pDM_Odm->BbSwingIdxCckBase = pDM_Odm->DefaultCckIndex;
pDM_Odm->RFCalibrateInfo.CCK_index = pDM_Odm->DefaultCckIndex;
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p)
{
pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->DefaultOfdmIndex;
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pDM_Odm->DefaultOfdmIndex;
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = 0;
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p] = 0;
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
}
}
VOID
ODM_TXPowerTrackingCheck(
IN PVOID pDM_VOID
)
{
//
// 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
// at the same time. In the stage2/3, we need to prive universal interface and merge all
// HW dynamic mechanism.
//
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
switch (pDM_Odm->SupportPlatform)
{
case ODM_WIN:
odm_TXPowerTrackingCheckMP(pDM_Odm);
break;
case ODM_CE:
odm_TXPowerTrackingCheckCE(pDM_Odm);
break;
case ODM_AP:
odm_TXPowerTrackingCheckAP(pDM_Odm);
break;
case ODM_ADSL:
//odm_DIGAP(pDM_Odm);
break;
}
}
VOID
odm_TXPowerTrackingCheckCE(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
#if( (RTL8192C_SUPPORT==1) || (RTL8723A_SUPPORT==1) )
if(IS_HARDWARE_TYPE_8192C(Adapter)){
rtl8192c_odm_CheckTXPowerTracking(Adapter);
return;
}
#endif
#if (RTL8192D_SUPPORT==1)
if(IS_HARDWARE_TYPE_8192D(Adapter)){
#if (RTL8192D_EASY_SMART_CONCURRENT == 1)
if(!Adapter->bSlaveOfDMSP)
#endif
rtl8192d_odm_CheckTXPowerTracking(Adapter);
return;
}
#endif
#if(((RTL8188E_SUPPORT==1) || (RTL8812A_SUPPORT==1) || (RTL8821A_SUPPORT==1) || (RTL8192E_SUPPORT==1) || (RTL8723B_SUPPORT==1) ))
if(!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK))
{
return;
}
if(!pDM_Odm->RFCalibrateInfo.TM_Trigger) //at least delay 1 sec
{
//pHalData->TxPowerCheckCnt++; //cosa add for debug
if(IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter)||IS_HARDWARE_TYPE_8723B(Adapter))
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT17 | BIT16), 0x03);
else
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_OLD, bRFRegOffsetMask, 0x60);
//DBG_871X("Trigger Thermal Meter!!\n");
pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
return;
}
else
{
//DBG_871X("Schedule TxPowerTracking direct call!!\n");
ODM_TXPowerTrackingCallback_ThermalMeter(Adapter);
pDM_Odm->RFCalibrateInfo.TM_Trigger = 0;
}
#endif
#endif
}
VOID
odm_TXPowerTrackingCheckMP(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
if (ODM_CheckPowerStatus(Adapter) == FALSE)
{
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>ODM_CheckPowerStatus() return FALSE\n"));
return;
}
if(IS_HARDWARE_TYPE_8723A(Adapter))
return;
if(!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE)
odm_TXPowerTrackingThermalMeterCheck(Adapter);
else {
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE\n"));
}
#endif
}
VOID
odm_TXPowerTrackingCheckAP(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
prtl8192cd_priv priv = pDM_Odm->priv;
if ( (priv->pmib->dot11RFEntry.ther) && ((priv->up_time % priv->pshare->rf_ft_var.tpt_period) == 0)){
#ifdef CONFIG_RTL_92D_SUPPORT
if (GET_CHIP_VER(priv)==VERSION_8192D){
tx_power_tracking_92D(priv);
} else
#endif
{
#ifdef CONFIG_RTL_92C_SUPPORT
tx_power_tracking(priv);
#endif
}
}
#endif
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
odm_TXPowerTrackingThermalMeterCheck(
IN PADAPTER Adapter
)
{
#ifndef AP_BUILD_WORKAROUND
static u1Byte TM_Trigger = 0;
if(!(GET_HAL_DATA(Adapter)->DM_OutSrc.SupportAbility & ODM_RF_TX_PWR_TRACK))
{
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
("===>odm_TXPowerTrackingThermalMeterCheck(),pMgntInfo->bTXPowerTracking is FALSE, return!!\n"));
return;
}
if(!TM_Trigger) //at least delay 1 sec
{
if(IS_HARDWARE_TYPE_8192D(Adapter))
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_92D, BIT17 | BIT16, 0x03);
else if(IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) ||
IS_HARDWARE_TYPE_8723B(Adapter))
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03);
else
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger Thermal Meter!!\n"));
TM_Trigger = 1;
return;
}
else
{
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n"));
odm_TXPowerTrackingDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18.
TM_Trigger = 0;
}
#endif
}
#endif

248
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_PowerTracking.h
View File

@ -1,248 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMPOWERTRACKING_H__
#define __PHYDMPOWERTRACKING_H__
#define POWRTRACKING_VERSION "1.0"
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
#define OFDM_TABLE_SIZE 43
#define CCK_TABLE_SIZE 33
#define TXSCALE_TABLE_SIZE 37
#define TXPWR_TRACK_TABLE_SIZE 30
#define DELTA_SWINGIDX_SIZE 30
#define BAND_NUM 4
#define AVG_THERMAL_NUM 8
#define HP_THERMAL_NUM 8
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM_MAX 10
#if (RTL8192D_SUPPORT==1)
#define IQK_BB_REG_NUM 10
#else
#define IQK_BB_REG_NUM 9
#endif
#define IQK_Matrix_REG_NUM 8
#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G
extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE];
extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE];
extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8];
extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table.
static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
typedef struct _IQK_MATRIX_REGS_SETTING{
BOOLEAN bIQKDone;
s4Byte Value[3][IQK_Matrix_REG_NUM];
BOOLEAN bBWIqkResultSaved[3];
}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;
typedef struct ODM_RF_Calibration_Structure
{
//for tx power tracking
u4Byte RegA24; // for TempCCK
s4Byte RegE94;
s4Byte RegE9C;
s4Byte RegEB4;
s4Byte RegEBC;
u1Byte TXPowercount;
BOOLEAN bTXPowerTrackingInit;
BOOLEAN bTXPowerTracking;
u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u1Byte TM_Trigger;
u1Byte InternalPA5G[2]; //pathA / pathB
u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
u1Byte ThermalValue;
u1Byte ThermalValue_LCK;
u1Byte ThermalValue_IQK;
u1Byte ThermalValue_DPK;
u1Byte ThermalValue_AVG[AVG_THERMAL_NUM];
u1Byte ThermalValue_AVG_index;
u1Byte ThermalValue_RxGain;
u1Byte ThermalValue_Crystal;
u1Byte ThermalValue_DPKstore;
u1Byte ThermalValue_DPKtrack;
BOOLEAN TxPowerTrackingInProgress;
BOOLEAN bReloadtxpowerindex;
u1Byte bRfPiEnable;
u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug
//------------------------- Tx power Tracking -------------------------//
u1Byte bCCKinCH14;
u1Byte CCK_index;
u1Byte OFDM_index[MAX_RF_PATH];
s1Byte PowerIndexOffset[MAX_RF_PATH];
s1Byte DeltaPowerIndex[MAX_RF_PATH];
s1Byte DeltaPowerIndexLast[MAX_RF_PATH];
BOOLEAN bTxPowerChanged;
u1Byte ThermalValue_HP[HP_THERMAL_NUM];
u1Byte ThermalValue_HP_index;
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
u1Byte Delta_LCK;
s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB
u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
//--------------------------------------------------------------------//
//for IQK
u4Byte RegC04;
u4Byte Reg874;
u4Byte RegC08;
u4Byte RegB68;
u4Byte RegB6C;
u4Byte Reg870;
u4Byte Reg860;
u4Byte Reg864;
BOOLEAN bIQKInitialized;
BOOLEAN bLCKInProgress;
BOOLEAN bAntennaDetected;
BOOLEAN bNeedIQK;
BOOLEAN bIQKInProgress;
u1Byte Delta_IQK;
u4Byte ADDA_backup[IQK_ADDA_REG_NUM];
u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM];
u4Byte IQK_BB_backup_recover[9];
u4Byte IQK_BB_backup[IQK_BB_REG_NUM];
u4Byte TxIQC_8723B[2][3][2]; // { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}
u4Byte RxIQC_8723B[2][2][2]; // { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}
// <James> IQK time measurement
u8Byte IQK_StartTime;
u8Byte IQK_ProgressingTime;
//for APK
u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a
u1Byte bAPKdone;
u1Byte bAPKThermalMeterIgnore;
// DPK
BOOLEAN bDPKFail;
u1Byte bDPdone;
u1Byte bDPPathAOK;
u1Byte bDPPathBOK;
u4Byte TxLOK[2];
}ODM_RF_CAL_T,*PODM_RF_CAL_T;
VOID
ODM_TXPowerTrackingCheck(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingInit(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingCheckAP(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingThermalMeterInit(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingInit(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingCheckMP(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingCheckCE(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
VOID
odm_TXPowerTrackingCallbackThermalMeter92C(
IN PADAPTER Adapter
);
VOID
odm_TXPowerTrackingCallbackRXGainThermalMeter92D(
IN PADAPTER Adapter
);
VOID
odm_TXPowerTrackingCallbackThermalMeter92D(
IN PADAPTER Adapter
);
VOID
odm_TXPowerTrackingDirectCall92C(
IN PADAPTER Adapter
);
VOID
odm_TXPowerTrackingThermalMeterCheck(
IN PADAPTER Adapter
);
#endif
#endif

1685
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_RXHP.c
View File

File diff suppressed because it is too large Load Diff

105
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_RXHP.h
View File

@ -1,105 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMRXHP_H__
#define __PHYDMRXHP_H__
#define RXHP_VERSION "1.0"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD
#define MODE_40M 0 //0:20M, 1:40M
#define PSD_TH2 3
#define PSD_CHMIN 20 // Minimum channel number for BT AFH
#define SIR_STEP_SIZE 3
#define Smooth_Size_1 5
#define Smooth_TH_1 3
#define Smooth_Size_2 10
#define Smooth_TH_2 4
#define Smooth_Size_3 20
#define Smooth_TH_3 4
#define Smooth_Step_Size 5
#define Adaptive_SIR 1
#define PSD_RESCAN 4
#define PSD_SCAN_INTERVAL 700 //ms
typedef struct _RX_High_Power_
{
u1Byte RXHP_flag;
u1Byte PSD_func_trigger;
u1Byte PSD_bitmap_RXHP[80];
u1Byte Pre_IGI;
u1Byte Cur_IGI;
u1Byte Pre_pw_th;
u1Byte Cur_pw_th;
BOOLEAN First_time_enter;
BOOLEAN RXHP_enable;
u1Byte TP_Mode;
RT_TIMER PSDTimer;
#if USE_WORKITEM
RT_WORK_ITEM PSDTimeWorkitem;
#endif
}RXHP_T, *pRXHP_T;
#define dm_PSDMonitorCallback odm_PSDMonitorCallback
VOID odm_PSDMonitorCallback(PRT_TIMER pTimer);
VOID
odm_PSDMonitorInit(
IN PVOID pDM_VOID
);
void odm_RXHPInit(
IN PVOID pDM_VOID);
void odm_RXHP(
IN PVOID pDM_VOID);
VOID
odm_PSD_RXHPCallback(
PRT_TIMER pTimer
);
VOID
ODM_PSDDbgControl(
IN PADAPTER Adapter,
IN u4Byte mode,
IN u4Byte btRssi
);
VOID
odm_PSD_RXHPCallback(
PRT_TIMER pTimer
);
VOID
odm_PSD_RXHPWorkitemCallback(
IN PVOID pContext
);
VOID
odm_PSDMonitorWorkItemCallback(
IN PVOID pContext
);
#endif
#endif

1595
drivers/net/wireless/rockchip_wlan/rtl8723bs-vq0/hal/OUTSRC/phydm_RaInfo.c
View File

File diff suppressed because it is too large Load Diff

Some files were not shown because too many files have changed in this diff Show More