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riscv: dts: sophgo: sg2044: add pmu configuration

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Add PMU configuration for the cpu of sg2044, which is the V2
version of C920.

Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Han Gao <rabenda.cn@gmail.com>
Link: https://lore.kernel.org/r/20250703003844.84617-1-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
This commit is contained in:
Inochi Amaoto 2025-07-03 08:38:43 +08:00
parent a1de92f0cd
commit 3f859e8382
1 changed files with 91 additions and 0 deletions
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91
arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
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@ -2778,6 +2778,97 @@ l3_cache: cache-controller-16 {
};
};
pmu {
compatible = "riscv,pmu";
riscv,event-to-mhpmevent =
<0x00003 0x00000000 0x00000010>,
<0x00004 0x00000000 0x00000011>,
<0x00005 0x00000000 0x00000007>,
<0x00006 0x00000000 0x00000006>,
<0x00008 0x00000000 0x00000027>,
<0x00009 0x00000000 0x00000028>,
<0x10000 0x00000000 0x0000000c>,
<0x10001 0x00000000 0x0000000d>,
<0x10002 0x00000000 0x0000000e>,
<0x10003 0x00000000 0x0000000f>,
<0x10008 0x00000000 0x00000001>,
<0x10009 0x00000000 0x00000002>,
<0x10010 0x00000000 0x00000010>,
<0x10011 0x00000000 0x00000011>,
<0x10012 0x00000000 0x00000012>,
<0x10013 0x00000000 0x00000013>,
<0x10019 0x00000000 0x00000004>,
<0x10021 0x00000000 0x00000003>,
<0x10030 0x00000000 0x0000001c>,
<0x10031 0x00000000 0x0000001b>;
riscv,event-to-mhpmcounters =
<0x00003 0x00003 0xfffffff8>,
<0x00004 0x00004 0xfffffff8>,
<0x00005 0x00005 0xfffffff8>,
<0x00006 0x00006 0xfffffff8>,
<0x00007 0x00007 0xfffffff8>,
<0x00008 0x00008 0xfffffff8>,
<0x00009 0x00009 0xfffffff8>,
<0x0000a 0x0000a 0xfffffff8>,
<0x10000 0x10000 0xfffffff8>,
<0x10001 0x10001 0xfffffff8>,
<0x10002 0x10002 0xfffffff8>,
<0x10003 0x10003 0xfffffff8>,
<0x10008 0x10008 0xfffffff8>,
<0x10009 0x10009 0xfffffff8>,
<0x10010 0x10010 0xfffffff8>,
<0x10011 0x10011 0xfffffff8>,
<0x10012 0x10012 0xfffffff8>,
<0x10013 0x10013 0xfffffff8>,
<0x10019 0x10019 0xfffffff8>,
<0x10021 0x10021 0xfffffff8>,
<0x10030 0x10030 0xfffffff8>,
<0x10031 0x10031 0xfffffff8>;
riscv,raw-event-to-mhpmcounters =
<0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>,
<0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>;
};
soc {
intc: interrupt-controller@6d40000000 {
compatible = "sophgo,sg2044-plic", "thead,c900-plic";