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drm/amd/display: Add clear DCC and Tiling callback for DCE

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Introduce the DCC and Tiling reset callback to all DCE versions that can
call it.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rodrigo Siqueira 2025-02-04 08:59:35 -07:00 committed by Alex Deucher
parent 2b04d04de9
commit 3f670b745d
6 changed files with 9 additions and 16 deletions
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18
drivers/gpu/drm/amd/display/dc/core/dc_surface.c
View File

@ -290,21 +290,7 @@ void dc_plane_force_dcc_and_tiling_disable(struct dc_plane_state *plane_state,
if (!pipe_ctx)
continue;
if (dc->ctx->dce_version >= DCE_VERSION_MAX) {
if (dc->hwss.clear_surface_dcc_and_tiling)
dc->hwss.clear_surface_dcc_and_tiling(pipe_ctx, plane_state, clear_tiling);
} else {
struct mem_input *mi = pipe_ctx->plane_res.mi;
if (!mi)
continue;
/* if framebuffer is tiled, disable tiling */
if (clear_tiling && mi->funcs->mem_input_clear_tiling)
mi->funcs->mem_input_clear_tiling(mi);
/* force page flip to see the new content of the framebuffer */
mi->funcs->mem_input_program_surface_flip_and_addr(mi,
&plane_state->address,
true);
}
if (dc->hwss.clear_surface_dcc_and_tiling)
dc->hwss.clear_surface_dcc_and_tiling(pipe_ctx, plane_state, clear_tiling);
}
}

1
drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
View File

@ -428,5 +428,6 @@ void dce60_hw_sequencer_construct(struct dc *dc)
dc->hwss.pipe_control_lock = dce60_pipe_control_lock;
dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;
}

1
drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
View File

@ -138,6 +138,7 @@ void dce100_hw_sequencer_construct(struct dc *dc)
dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;
}
/**

2
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
View File

@ -33,6 +33,7 @@
#include "dce110_hwseq.h"
#include "dce110/dce110_timing_generator.h"
#include "dce/dce_hwseq.h"
#include "dce100/dce100_hwseq.h"
#include "gpio_service_interface.h"
#include "dce110/dce110_compressor.h"
@ -3332,6 +3333,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.post_unlock_program_front_end = dce110_post_unlock_program_front_end,
.update_plane_addr = update_plane_addr,
.update_pending_status = dce110_update_pending_status,
.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling,
.enable_accelerated_mode = dce110_enable_accelerated_mode,
.enable_timing_synchronization = dce110_enable_timing_synchronization,
.enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,

2
drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
View File

@ -29,6 +29,7 @@
#include "dce120_hwseq.h"
#include "dce/dce_hwseq.h"
#include "dce100/dce100_hwseq.h"
#include "dce110/dce110_hwseq.h"
#include "dce/dce_12_0_offset.h"
@ -264,5 +265,6 @@ void dce120_hw_sequencer_construct(struct dc *dc)
dce110_hw_sequencer_construct(dc);
dc->hwseq->funcs.enable_display_power_gating = dce120_enable_display_power_gating;
dc->hwss.update_dchub = dce120_update_dchub;
dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;
}

1
drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c
View File

@ -50,5 +50,6 @@ void dce80_hw_sequencer_construct(struct dc *dc)
dc->hwss.pipe_control_lock = dce_pipe_control_lock;
dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;
}