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Merge branch kvm-arm64/psci-relay-fixes into kvmarm/next
* kvm-arm64/psci-relay-fixes: : Fixes for CPU on/resume with pKVM, courtesy Quentin Perret. : : A consequence of deprivileging the host is that pKVM relays PSCI calls : on behalf of the host. pKVM's CPU initialization failed to fully : initialize the CPU's EL2 state, which notably led to unexpected SVE : traps resulting in a hyp panic. : : The issue is addressed by reusing parts of __finalise_el2 to restore CPU : state in the PSCI relay. KVM: arm64: Finalise EL2 state from pKVM PSCI relay KVM: arm64: Use sanitized values in __check_override in nVHE KVM: arm64: Introduce finalise_el2_state macro KVM: arm64: Provide sanitized SYS_ID_AA64SMFR0_EL1 to nVHE
This commit is contained in:
Oliver Upton
commit
3f1a14af5e
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@ -196,4 +196,103 @@
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__init_el2_nvhe_prepare_eret
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.endm
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#ifndef __KVM_NVHE_HYPERVISOR__
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// This will clobber tmp1 and tmp2, and expect tmp1 to contain
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// the id register value as read from the HW
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.macro __check_override idreg, fld, width, pass, fail, tmp1, tmp2
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ubfx \tmp1, \tmp1, #\fld, #\width
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cbz \tmp1, \fail
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adr_l \tmp1, \idreg\()_override
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ldr \tmp2, [\tmp1, FTR_OVR_VAL_OFFSET]
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ldr \tmp1, [\tmp1, FTR_OVR_MASK_OFFSET]
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ubfx \tmp2, \tmp2, #\fld, #\width
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ubfx \tmp1, \tmp1, #\fld, #\width
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cmp \tmp1, xzr
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and \tmp2, \tmp2, \tmp1
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csinv \tmp2, \tmp2, xzr, ne
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cbnz \tmp2, \pass
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b \fail
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.endm
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// This will clobber tmp1 and tmp2
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.macro check_override idreg, fld, pass, fail, tmp1, tmp2
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mrs \tmp1, \idreg\()_el1
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__check_override \idreg \fld 4 \pass \fail \tmp1 \tmp2
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.endm
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#else
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// This will clobber tmp
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.macro __check_override idreg, fld, width, pass, fail, tmp, ignore
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ldr_l \tmp, \idreg\()_el1_sys_val
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ubfx \tmp, \tmp, #\fld, #\width
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cbnz \tmp, \pass
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b \fail
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.endm
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.macro check_override idreg, fld, pass, fail, tmp, ignore
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__check_override \idreg \fld 4 \pass \fail \tmp \ignore
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.endm
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#endif
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.macro finalise_el2_state
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check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\@, .Lskip_sve_\@, x1, x2
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.Linit_sve_\@: /* SVE register access */
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mrs x0, cptr_el2 // Disable SVE traps
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bic x0, x0, #CPTR_EL2_TZ
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msr cptr_el2, x0
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isb
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mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
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msr_s SYS_ZCR_EL2, x1 // length for EL1.
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.Lskip_sve_\@:
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check_override id_aa64pfr1, ID_AA64PFR1_EL1_SME_SHIFT, .Linit_sme_\@, .Lskip_sme_\@, x1, x2
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.Linit_sme_\@: /* SME register access and priority mapping */
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mrs x0, cptr_el2 // Disable SME traps
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bic x0, x0, #CPTR_EL2_TSM
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msr cptr_el2, x0
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isb
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mrs x1, sctlr_el2
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orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps
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msr sctlr_el2, x1
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isb
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mov x0, #0 // SMCR controls
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// Full FP in SM?
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mrs_s x1, SYS_ID_AA64SMFR0_EL1
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__check_override id_aa64smfr0, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, .Linit_sme_fa64_\@, .Lskip_sme_fa64_\@, x1, x2
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.Linit_sme_fa64_\@:
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orr x0, x0, SMCR_ELx_FA64_MASK
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.Lskip_sme_fa64_\@:
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// ZT0 available?
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mrs_s x1, SYS_ID_AA64SMFR0_EL1
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__check_override id_aa64smfr0, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, .Linit_sme_zt0_\@, .Lskip_sme_zt0_\@, x1, x2
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.Linit_sme_zt0_\@:
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orr x0, x0, SMCR_ELx_EZT0_MASK
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.Lskip_sme_zt0_\@:
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orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector
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msr_s SYS_SMCR_EL2, x0 // length for EL1.
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mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported?
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ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1
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cbz x1, .Lskip_sme_\@
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msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal
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mrs x1, id_aa64mmfr1_el1 // HCRX_EL2 present?
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ubfx x1, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4
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cbz x1, .Lskip_sme_\@
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mrs_s x1, SYS_HCRX_EL2
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orr x1, x1, #HCRX_EL2_SMPME_MASK // Enable priority mapping
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msr_s SYS_HCRX_EL2, x1
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.Lskip_sme_\@:
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.endm
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#endif /* __ARM_KVM_INIT_H__ */
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@ -122,6 +122,7 @@ extern u64 kvm_nvhe_sym(id_aa64isar2_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64mmfr0_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64mmfr1_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64mmfr2_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64smfr0_el1_sys_val);
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extern unsigned long kvm_nvhe_sym(__icache_flags);
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extern unsigned int kvm_nvhe_sym(kvm_arm_vmid_bits);
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@ -16,30 +16,6 @@
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#include <asm/ptrace.h>
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#include <asm/virt.h>
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// Warning, hardcoded register allocation
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// This will clobber x1 and x2, and expect x1 to contain
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// the id register value as read from the HW
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.macro __check_override idreg, fld, width, pass, fail
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ubfx x1, x1, #\fld, #\width
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cbz x1, \fail
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adr_l x1, \idreg\()_override
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ldr x2, [x1, FTR_OVR_VAL_OFFSET]
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ldr x1, [x1, FTR_OVR_MASK_OFFSET]
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ubfx x2, x2, #\fld, #\width
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ubfx x1, x1, #\fld, #\width
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cmp x1, xzr
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and x2, x2, x1
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csinv x2, x2, xzr, ne
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cbnz x2, \pass
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b \fail
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.endm
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.macro check_override idreg, fld, pass, fail
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mrs x1, \idreg\()_el1
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__check_override \idreg \fld 4 \pass \fail
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.endm
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.text
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.pushsection .hyp.text, "ax"
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@ -98,65 +74,7 @@ SYM_CODE_START_LOCAL(elx_sync)
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SYM_CODE_END(elx_sync)
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SYM_CODE_START_LOCAL(__finalise_el2)
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check_override id_aa64pfr0 ID_AA64PFR0_EL1_SVE_SHIFT .Linit_sve .Lskip_sve
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.Linit_sve: /* SVE register access */
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mrs x0, cptr_el2 // Disable SVE traps
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bic x0, x0, #CPTR_EL2_TZ
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msr cptr_el2, x0
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isb
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mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
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msr_s SYS_ZCR_EL2, x1 // length for EL1.
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.Lskip_sve:
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check_override id_aa64pfr1 ID_AA64PFR1_EL1_SME_SHIFT .Linit_sme .Lskip_sme
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.Linit_sme: /* SME register access and priority mapping */
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mrs x0, cptr_el2 // Disable SME traps
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bic x0, x0, #CPTR_EL2_TSM
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msr cptr_el2, x0
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isb
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mrs x1, sctlr_el2
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orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps
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msr sctlr_el2, x1
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isb
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mov x0, #0 // SMCR controls
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// Full FP in SM?
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mrs_s x1, SYS_ID_AA64SMFR0_EL1
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__check_override id_aa64smfr0 ID_AA64SMFR0_EL1_FA64_SHIFT 1 .Linit_sme_fa64 .Lskip_sme_fa64
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.Linit_sme_fa64:
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orr x0, x0, SMCR_ELx_FA64_MASK
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.Lskip_sme_fa64:
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// ZT0 available?
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mrs_s x1, SYS_ID_AA64SMFR0_EL1
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__check_override id_aa64smfr0 ID_AA64SMFR0_EL1_SMEver_SHIFT 4 .Linit_sme_zt0 .Lskip_sme_zt0
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.Linit_sme_zt0:
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orr x0, x0, SMCR_ELx_EZT0_MASK
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.Lskip_sme_zt0:
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orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector
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msr_s SYS_SMCR_EL2, x0 // length for EL1.
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mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported?
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ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1
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cbz x1, .Lskip_sme
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msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal
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mrs x1, id_aa64mmfr1_el1 // HCRX_EL2 present?
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ubfx x1, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4
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cbz x1, .Lskip_sme
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mrs_s x1, SYS_HCRX_EL2
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orr x1, x1, #HCRX_EL2_SMPME_MASK // Enable priority mapping
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msr_s SYS_HCRX_EL2, x1
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.Lskip_sme:
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finalise_el2_state
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// nVHE? No way! Give me the real thing!
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// Sanity check: MMU *must* be off
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@ -164,7 +82,7 @@ SYM_CODE_START_LOCAL(__finalise_el2)
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tbnz x1, #0, 1f
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// Needs to be VHE capable, obviously
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check_override id_aa64mmfr1 ID_AA64MMFR1_EL1_VH_SHIFT 2f 1f
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check_override id_aa64mmfr1 ID_AA64MMFR1_EL1_VH_SHIFT 2f 1f x1 x2
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1: mov_q x0, HVC_STUB_ERR
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eret
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@ -1899,6 +1899,7 @@ static void kvm_hyp_init_symbols(void)
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kvm_nvhe_sym(id_aa64mmfr0_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
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kvm_nvhe_sym(id_aa64mmfr1_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
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kvm_nvhe_sym(id_aa64mmfr2_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1);
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kvm_nvhe_sym(id_aa64smfr0_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64SMFR0_EL1);
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kvm_nvhe_sym(__icache_flags) = __icache_flags;
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kvm_nvhe_sym(kvm_arm_vmid_bits) = kvm_arm_vmid_bits;
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}
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@ -183,6 +183,7 @@ SYM_CODE_START_LOCAL(__kvm_hyp_init_cpu)
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/* Initialize EL2 CPU state to sane values. */
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init_el2_state // Clobbers x0..x2
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finalise_el2_state
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/* Enable MMU, set vectors and stack. */
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mov x0, x28
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@ -26,6 +26,7 @@ u64 id_aa64isar2_el1_sys_val;
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u64 id_aa64mmfr0_el1_sys_val;
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u64 id_aa64mmfr1_el1_sys_val;
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u64 id_aa64mmfr2_el1_sys_val;
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u64 id_aa64smfr0_el1_sys_val;
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/*
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* Inject an unknown/undefined exception to an AArch64 guest while most of its
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