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drm/amdgpu/vpe: fix vpe dpm clk ratio setup failed

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Some version of BIOS does not enable all clock levels,
resulting in high level clock frequency of 0.
The number of valid CLKs must be confirmed in advance.

Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: Lang Yu <lang.yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Peyton Lee 2024-04-30 22:09:09 +08:00 committed by Alex Deucher
parent c6f79832b8
commit 3f19cffde9
1 changed files with 11 additions and 2 deletions
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13
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
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@ -128,6 +128,7 @@ int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe)
struct dpm_clock *VPEClks;
struct dpm_clock *SOCClks;
uint32_t idx;
uint32_t vpeclk_enalbled_num = 0;
uint32_t pratio_vmax_vnorm = 0, pratio_vnorm_vmid = 0, pratio_vmid_vmin = 0;
uint16_t pratio_vmin_freq = 0, pratio_vmid_freq = 0, pratio_vnorm_freq = 0, pratio_vmax_freq = 0;
@ -144,6 +145,14 @@ int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe)
SOCClks = clock_table.SocClocks;
VPEClks = clock_table.VPEClocks;
/* Comfirm enabled vpe clk num
* Enabled VPE clocks are ordered from low to high in VPEClks
* The highest valid clock index+1 is the number of VPEClks
*/
for (idx = PP_SMU_NUM_VPECLK_DPM_LEVELS; idx && !vpeclk_enalbled_num; idx--)
if (VPEClks[idx-1].Freq)
vpeclk_enalbled_num = idx;
/* vpe dpm only cares 4 levels. */
for (idx = 0; idx < VPE_MAX_DPM_LEVEL; idx++) {
uint32_t soc_dpm_level;
@ -155,8 +164,8 @@ int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe)
soc_dpm_level = (idx * 2) + 1;
/* clamp the max level */
if (soc_dpm_level > PP_SMU_NUM_VPECLK_DPM_LEVELS - 1)
soc_dpm_level = PP_SMU_NUM_VPECLK_DPM_LEVELS - 1;
if (soc_dpm_level > vpeclk_enalbled_num - 1)
soc_dpm_level = vpeclk_enalbled_num - 1;
min_freq = (SOCClks[soc_dpm_level].Freq < VPEClks[soc_dpm_level].Freq) ?
SOCClks[soc_dpm_level].Freq : VPEClks[soc_dpm_level].Freq;