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drm/i915/display: Add helper to enable DC counter

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Add xe3lpd_enable_dc_count() to enable the DC_COUNT_EN register.
Also define DC_STATE_DC3CO_RESIDENCY to read DC3CO residency.
Needed to retrieve DC residency for DC3CO.

v2:
- Add a guard to xe3lpd_enable_dc_count() instead of relying
on caller. [Animesh]

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patch.msgid.link/20260616162154.2630995-14-dibin.moolakadan.subrahmanian@intel.com
This commit is contained in:
Dibin Moolakadan Subrahmanian 2026-06-16 21:51:51 +05:30 committed by Animesh Manna
parent d49e3c5c81
commit 3f0f348606
4 changed files with 16 additions and 0 deletions
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8
drivers/gpu/drm/i915/display/intel_display_power_well.c
View File

@ -866,6 +866,14 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
power_domains->dc_state = val & mask;
}
void xe3lpd_enable_dc_count(struct intel_display *display)
{
if (DISPLAY_VER(display) < 35)
return;
intel_de_write(display, DC_COUNT_EN, DC_COUNT_EN_COUNTER_ENABLE);
}
static void assert_can_enable_dc3co(struct intel_display *display)
{
drm_WARN_ONCE(display->drm,

1
drivers/gpu/drm/i915/display/intel_display_power_well.h
View File

@ -159,6 +159,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state);
void gen9_disable_dc_states(struct intel_display *display);
void bxt_enable_dc9(struct intel_display *display);
void bxt_disable_dc9(struct intel_display *display);
void xe3lpd_enable_dc_count(struct intel_display *display);
extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
extern const struct i915_power_well_ops chv_pipe_power_well_ops;

5
drivers/gpu/drm/i915/display/intel_display_regs.h
View File

@ -3086,6 +3086,11 @@ enum skl_power_gate {
#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
#define DC_COUNT_EN _MMIO(0x457B4)
#define DC_COUNT_EN_COUNTER_ENABLE REG_BIT(31)
#define DC_STATE_DC3CO_RESIDENCY _MMIO(0x457B8)
#define D_COMP_BDW _MMIO(0x138144)
/* Pipe WM_LINETIME - watermark line time */

2
drivers/gpu/drm/i915/display/intel_dmc.c
View File

@ -941,6 +941,8 @@ void intel_dmc_load_program(struct intel_display *display)
gen9_set_dc_state_debugmask(display);
xe3lpd_enable_dc_count(display);
pipedmc_clock_gating_wa(display, false);
}