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wifi: rtw89: read hardware capabilities part 1 via firmware command

Browse Source 
Firmware after version 0.35.51.0 defines and exports more hardware
capabilities, which driver will consider reported QAM field as
EHT MCS capability to register hardware.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20250108020955.14668-2-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih 2025-01-08 10:09:54 +08:00
parent ba4bb0402c
commit 3f0e689089
4 changed files with 95 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/net/wireless/realtek/rtw89/core.h
View File

@ -4471,6 +4471,7 @@ enum rtw89_fw_feature {
RTW89_FW_FEATURE_NOTIFY_AP_INFO,
RTW89_FW_FEATURE_CH_INFO_BE_V0,
RTW89_FW_FEATURE_LPS_CH_INFO,
RTW89_FW_FEATURE_NO_PHYCAP_P1,
};
struct rtw89_fw_suit {

1
drivers/net/wireless/realtek/rtw89/fw.c
View File

@ -734,6 +734,7 @@ static const struct __fw_feat_cfg fw_feat_tbl[] = {
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 46, 0, NOTIFY_AP_INFO),
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 47, 0, CH_INFO_BE_V0),
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 49, 0, RFK_PRE_NOTIFY_V1),
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 51, 0, NO_PHYCAP_P1),
};
static void rtw89_fw_iterate_feature_cfg(struct rtw89_fw_info *fw,

16
drivers/net/wireless/realtek/rtw89/fw.h
View File

@ -47,6 +47,19 @@ struct rtw89_c2hreg_phycap {
#define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
#define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
#define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
#define RTW89_C2HREG_PHYCAP_W3_BAND_SEL GENMASK(31, 24)
#define RTW89_C2HREG_PHYCAP_P1_W0_B1_RX_NSS GENMASK(23, 16)
#define RTW89_C2HREG_PHYCAP_P1_W0_B1_BW GENMASK(31, 24)
#define RTW89_C2HREG_PHYCAP_P1_W1_B1_TX_NSS GENMASK(7, 0)
#define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_TX_NUM GENMASK(15, 8)
#define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_RX_NUM GENMASK(23, 16)
#define RTW89_C2HREG_PHYCAP_P1_W1_B1_BAND_SEL GENMASK(31, 24)
#define RTW89_C2HREG_PHYCAP_P1_W2_QAM GENMASK(7, 0)
#define RTW89_C2HREG_PHYCAP_P1_W2_QAM_256 0x1
#define RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024 0x2
#define RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096 0x3
#define RTW89_C2HREG_PHYCAP_P1_W2_B1_QAM GENMASK(15, 8)
#define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16)
#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0)
@ -92,6 +105,8 @@ struct rtw89_h2creg_sch_tx_en {
#define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)
#define RTW89_H2CREG_GET_FEATURE_PART_NUM GENMASK(23, 16)
#define RTW89_H2CREG_MAX 4
#define RTW89_C2HREG_MAX 4
#define RTW89_C2HREG_HDR_LEN 2
@ -138,6 +153,7 @@ enum rtw89_mac_c2h_type {
RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA,
RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1 = 0xC,
RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF,
};

87
drivers/net/wireless/realtek/rtw89/mac.c
View File

@ -2898,22 +2898,42 @@ static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
}
static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev,
struct rtw89_mac_c2h_info *c2h_info)
struct rtw89_mac_c2h_info *c2h_info, u8 part_num)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
struct rtw89_mac_h2c_info h2c_info = {0};
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_mac_h2c_info h2c_info = {};
enum rtw89_mac_c2h_type c2h_type;
u8 content_len;
u32 ret;
if (chip->chip_gen == RTW89_CHIP_AX)
content_len = 0;
else
content_len = 2;
switch (part_num) {
case 0:
c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP;
break;
case 1:
c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1;
break;
default:
return -EINVAL;
}
mac->cnv_efuse_state(rtwdev, false);
h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE;
h2c_info.content_len = 0;
h2c_info.content_len = content_len;
h2c_info.u.hdr.w0 = u32_encode_bits(part_num, RTW89_H2CREG_GET_FEATURE_PART_NUM);
ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info);
if (ret)
goto out;
if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP)
if (c2h_info->id != c2h_type)
ret = -EINVAL;
out:
@ -2922,20 +2942,20 @@ static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev,
return ret;
}
int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)
static int rtw89_mac_setup_phycap_part0(struct rtw89_dev *rtwdev)
{
struct rtw89_efuse *efuse = &rtwdev->efuse;
struct rtw89_hal *hal = &rtwdev->hal;
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_mac_c2h_info c2h_info = {0};
const struct rtw89_c2hreg_phycap *phycap;
struct rtw89_efuse *efuse = &rtwdev->efuse;
struct rtw89_mac_c2h_info c2h_info = {};
struct rtw89_hal *hal = &rtwdev->hal;
u8 tx_nss;
u8 rx_nss;
u8 tx_ant;
u8 rx_ant;
u32 ret;
int ret;
ret = rtw89_mac_read_phycap(rtwdev, &c2h_info);
ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 0);
if (ret)
return ret;
@ -2979,6 +2999,53 @@ int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)
return 0;
}
static int rtw89_mac_setup_phycap_part1(struct rtw89_dev *rtwdev)
{
const struct rtw89_c2hreg_phycap *phycap;
struct rtw89_mac_c2h_info c2h_info = {};
u8 qam_raw, qam;
int ret;
ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 1);
if (ret)
return ret;
phycap = &c2h_info.u.phycap;
qam_raw = u32_get_bits(phycap->w2, RTW89_C2HREG_PHYCAP_P1_W2_QAM);
switch (qam_raw) {
case RTW89_C2HREG_PHYCAP_P1_W2_QAM_256:
case RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024:
case RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096:
qam = qam_raw;
break;
default:
qam = RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096;
break;
}
rtw89_debug(rtwdev, RTW89_DBG_FW, "phycap qam=%d/%d\n", qam_raw, qam);
return 0;
}
int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
int ret;
ret = rtw89_mac_setup_phycap_part0(rtwdev);
if (ret)
return ret;
if (chip->chip_gen == RTW89_CHIP_AX ||
RTW89_CHK_FW_FEATURE(NO_PHYCAP_P1, &rtwdev->fw))
return 0;
return rtw89_mac_setup_phycap_part1(rtwdev);
}
static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band,
u16 tx_en_u16, u16 mask_u16)
{