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drm/amd/display: [FW Promotion] Release 0.1.34.0
Release hightlights
DCN35/36
* Dynamically clock gate before and after prefetch
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Taimur Hassan
Alex Deucher
parent
678c901443
commit
3f0c27edd8
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@ -599,6 +599,104 @@ union replay_hw_flags {
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uint32_t u32All;
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};
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/**
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* Flags that can be set by driver to change some Panel Replay behaviour.
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*/
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union pr_debug_flags {
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struct {
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/**
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* 0x1 (bit 0)
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* Enable visual confirm in FW.
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*/
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uint32_t visual_confirm : 1;
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/**
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* 0x2 (bit 1)
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* @skip_crc: Set if need to skip CRC.
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*/
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uint32_t skip_crc : 1;
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/**
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* 0x4 (bit 2)
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* @force_link_power_on: Force disable ALPM control
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*/
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uint32_t force_link_power_on : 1;
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/**
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* 0x8 (bit 3)
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* @force_phy_power_on: Force phy power on
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*/
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uint32_t force_phy_power_on : 1;
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/**
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* 0x10 (bit 4)
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* @skip_crtc_disabled: CRTC disable skipped
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*/
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uint32_t skip_crtc_disabled : 1;
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/*
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* 0x20 (bit 5)
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* @visual_confirm_rate_control: Enable Visual Confirm rate control detection
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*/
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uint32_t visual_confirm_rate_control : 1;
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uint32_t reserved : 26;
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} bitfields;
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uint32_t u32All;
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};
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union pr_hw_flags {
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struct {
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/**
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* @allow_alpm_fw_standby_mode: To indicate whether the
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* ALPM FW standby mode is allowed
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*/
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uint32_t allow_alpm_fw_standby_mode : 1;
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/*
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* @dsc_enable_status: DSC enable status in driver
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*/
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uint32_t dsc_enable_status : 1;
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/**
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* @fec_enable_status: receive fec enable/disable status from driver
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*/
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uint32_t fec_enable_status : 1;
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/*
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* @smu_optimizations_en: SMU power optimization.
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* Only when active display is Replay capable and display enters Replay.
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* Trigger interrupt to SMU to powerup/down.
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*/
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uint32_t smu_optimizations_en : 1;
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/**
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* @phy_power_state: Indicates current phy power state
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*/
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uint32_t phy_power_state : 1;
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/**
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* @link_power_state: Indicates current link power state
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*/
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uint32_t link_power_state : 1;
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/**
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* Use TPS3 signal when restore main link.
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*/
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uint32_t force_wakeup_by_tps3 : 1;
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/**
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* @is_alpm_initialized: Indicates whether ALPM is initialized
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*/
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uint32_t is_alpm_initialized : 1;
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/**
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* @alpm_mode: Indicates ALPM mode selected
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*/
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uint32_t alpm_mode : 2;
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} bitfields;
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uint32_t u32All;
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};
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union fw_assisted_mclk_switch_version {
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struct {
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uint8_t minor : 5;
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@ -1732,9 +1830,15 @@ enum dmub_cmd_type {
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DMUB_CMD__CURSOR_OFFLOAD = 92,
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/**
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* Command type used for all SMART_POWER_HDR commands.
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* Command type used for all SMART_POWER_OLED commands.
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*/
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DMUB_CMD__SMART_POWER_HDR = 93,
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DMUB_CMD__SMART_POWER_OLED = 93,
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/**
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* Command type use for all Panel Replay commands.
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*/
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DMUB_CMD__PR = 94,
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/**
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* Command type use for VBIOS shared commands.
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@ -4147,6 +4251,33 @@ enum replay_state {
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REPLAY_STATE_INVALID = 0xFF,
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};
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/**
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* Definition of a panel replay state
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*/
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enum pr_state {
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PR_STATE_0 = 0x00, // State 0 steady state
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// Pending SDP and Unlock before back to State 0
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PR_STATE_0_PENDING_SDP_AND_UNLOCK = 0x01,
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PR_STATE_1 = 0x10, // State 1
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PR_STATE_2 = 0x20, // State 2 steady state
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// Pending frame transmission before transition to State 2
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PR_STATE_2_PENDING_FRAME_TRANSMISSION = 0x30,
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// Active and Powered Up
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PR_STATE_2_POWERED = 0x31,
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// Active and Powered Down, but need to blank HUBP after DPG_EN latch
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PR_STATE_2_PENDING_HUBP_BLANK = 0x32,
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// Active and Pending Power Up
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PR_STATE_2_PENDING_POWER_UP = 0x33,
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// Active and Powered Up, Pending DPG latch
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PR_STATE_2_PENDING_LOCK_FOR_DPG_POWER_ON = 0x34,
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// Active and Powered Up, Pending SDP and Unlock
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PR_STATE_2_PENDING_SDP_AND_UNLOCK = 0x35,
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// Pending transmission of AS SDP for timing sync, but no rfb update
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PR_STATE_2_PENDING_AS_SDP = 0x36,
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// Invalid
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PR_STATE_INVALID = 0xFF,
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};
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/**
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* Replay command sub-types.
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*/
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@ -4197,6 +4328,25 @@ enum dmub_cmd_replay_type {
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DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16,
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};
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/*
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* Panel Replay sub-types
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*/
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enum dmub_cmd_panel_replay_type {
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DMUB_CMD__PR_ENABLE = 0,
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DMUB_CMD__PR_COPY_SETTINGS = 1,
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DMUB_CMD__PR_UPDATE_STATE = 2,
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DMUB_CMD__PR_GENERAL_CMD = 3,
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};
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enum dmub_cmd_panel_replay_state_update_subtype {
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PR_STATE_UPDATE_COASTING_VTOTAL = 0x1,
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PR_STATE_UPDATE_SYNC_MODE = 0x2,
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};
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enum dmub_cmd_panel_replay_general_subtype {
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PR_GENERAL_CMD_DEBUG_OPTION = 0x1,
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};
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/**
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* Replay general command sub-types.
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*/
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@ -4349,17 +4499,13 @@ struct dmub_cmd_replay_set_version_data {
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*/
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uint8_t panel_inst;
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/**
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* PSR version that FW should implement.
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* Replay version that FW should implement.
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*/
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enum replay_version version;
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/**
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* PSR control version.
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*/
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uint8_t cmd_version;
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/**
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* Explicit padding to 4 byte boundary.
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*/
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uint8_t pad[2];
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uint8_t pad[3];
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};
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/**
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@ -4405,11 +4551,11 @@ enum replay_enable {
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};
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/**
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* Data passed from driver to FW in a DMUB_CMD__SMART_POWER_HDR_ENABLE command.
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* Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_ENABLE command.
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*/
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struct dmub_rb_cmd_smart_power_hdr_enable_data {
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struct dmub_rb_cmd_smart_power_oled_enable_data {
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/**
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* SMART_POWER_HDR enable or disable.
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* SMART_POWER_OLED enable or disable.
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*/
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uint8_t enable;
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/**
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@ -4777,53 +4923,53 @@ union dmub_replay_cmd_set {
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};
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/**
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* SMART POWER HDR command sub-types.
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* SMART POWER OLED command sub-types.
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*/
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enum dmub_cmd_smart_power_hdr_type {
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enum dmub_cmd_smart_power_oled_type {
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/**
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* Enable/Disable SMART_POWER_HDR.
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* Enable/Disable SMART_POWER_OLED.
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*/
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DMUB_CMD__SMART_POWER_HDR_ENABLE = 1,
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DMUB_CMD__SMART_POWER_OLED_ENABLE = 1,
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/**
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* Get current MaxCLL value if SMART POWER HDR is enabled.
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* Get current MaxCLL value if SMART POWER OLED is enabled.
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*/
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DMUB_CMD__SMART_POWER_HDR_GETMAXCLL = 2,
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DMUB_CMD__SMART_POWER_OLED_GETMAXCLL = 2,
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};
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/**
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* Definition of a DMUB_CMD__SMART_POWER_HDR command.
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* Definition of a DMUB_CMD__SMART_POWER_OLED command.
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*/
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struct dmub_rb_cmd_smart_power_hdr_enable {
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struct dmub_rb_cmd_smart_power_oled_enable {
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/**
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* Command header.
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*/
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struct dmub_cmd_header header;
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struct dmub_rb_cmd_smart_power_hdr_enable_data data;
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struct dmub_rb_cmd_smart_power_oled_enable_data data;
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};
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struct dmub_cmd_smart_power_hdr_getmaxcll_input {
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struct dmub_cmd_smart_power_oled_getmaxcll_input {
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uint8_t panel_inst;
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uint8_t pad[3];
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};
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struct dmub_cmd_smart_power_hdr_getmaxcll_output {
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struct dmub_cmd_smart_power_oled_getmaxcll_output {
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uint16_t current_max_cll;
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uint8_t pad[2];
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};
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/**
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* Definition of a DMUB_CMD__SMART_POWER_HDR command.
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* Definition of a DMUB_CMD__SMART_POWER_OLED command.
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*/
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struct dmub_rb_cmd_smart_power_hdr_getmaxcll {
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struct dmub_rb_cmd_smart_power_oled_getmaxcll {
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struct dmub_cmd_header header; /**< Command header */
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/**
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* Data passed from driver to FW in a DMUB_CMD__SMART_POWER_HDR_GETMAXCLL command.
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* Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command.
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*/
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union dmub_cmd_smart_power_hdr_getmaxcll_data {
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struct dmub_cmd_smart_power_hdr_getmaxcll_input input; /**< Input */
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struct dmub_cmd_smart_power_hdr_getmaxcll_output output; /**< Output */
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union dmub_cmd_smart_power_oled_getmaxcll_data {
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struct dmub_cmd_smart_power_oled_getmaxcll_input input; /**< Input */
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struct dmub_cmd_smart_power_oled_getmaxcll_output output; /**< Output */
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uint32_t output_raw; /**< Raw data output */
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} data;
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};
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@ -6356,6 +6502,223 @@ struct dmub_rb_cmd_cursor_offload_stream_cntl {
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struct dmub_cmd_cursor_offload_stream_data data;
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};
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/**
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* Data passed from driver to FW in a DMUB_CMD__PR_ENABLE command.
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*/
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struct dmub_cmd_pr_enable_data {
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/**
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* Panel Replay enable or disable.
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*/
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uint8_t enable;
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/**
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* Panel Instance.
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* Panel isntance to identify which replay_state to use
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* Currently the support is only for 0 or 1
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*/
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uint8_t panel_inst;
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/**
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* Phy state to enter.
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* Values to use are defined in dmub_phy_fsm_state
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*/
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uint8_t phy_fsm_state;
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/**
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* Phy rate for DP - RBR/HBR/HBR2/HBR3.
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* Set this using enum phy_link_rate.
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* This does not support HDMI/DP2 for now.
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*/
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uint8_t phy_rate;
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/**
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* @hpo_stream_enc_inst: HPO stream encoder instance
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*/
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uint8_t hpo_stream_enc_inst;
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/**
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* @hpo_link_enc_inst: HPO link encoder instance
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*/
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uint8_t hpo_link_enc_inst;
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/**
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* @pad: Align structure to 4 byte boundary.
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*/
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uint8_t pad[2];
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};
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/**
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* Definition of a DMUB_CMD__PR_ENABLE command.
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* Panel Replay enable/disable is controlled using action in data.
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*/
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struct dmub_rb_cmd_pr_enable {
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/**
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* Command header.
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*/
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struct dmub_cmd_header header;
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struct dmub_cmd_pr_enable_data data;
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};
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/**
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* Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command.
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*/
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struct dmub_cmd_pr_copy_settings_data {
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/**
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* Flags that can be set by driver to change some replay behaviour.
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*/
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union pr_debug_flags debug;
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/**
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* @flags: Flags used to determine feature functionality.
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*/
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union pr_hw_flags flags;
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/**
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* DPP HW instance.
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*/
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uint8_t dpp_inst;
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/**
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* OTG HW instance.
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*/
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uint8_t otg_inst;
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/**
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* DIG FE HW instance.
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*/
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uint8_t digfe_inst;
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/**
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* DIG BE HW instance.
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*/
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uint8_t digbe_inst;
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/**
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* AUX HW instance.
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*/
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uint8_t aux_inst;
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/**
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* Panel Instance.
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* Panel isntance to identify which psr_state to use
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* Currently the support is only for 0 or 1
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*/
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uint8_t panel_inst;
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/**
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* Length of each horizontal line in ns.
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*/
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uint32_t line_time_in_ns;
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/**
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* PHY instance.
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*/
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uint8_t dpphy_inst;
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/**
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* Determines if SMU optimzations are enabled/disabled.
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*/
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uint8_t smu_optimizations_en;
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/*
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* Use FSM state for Replay power up/down
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*/
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uint8_t use_phy_fsm;
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/*
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* Use FSFT afftet pixel clk
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*/
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uint32_t pix_clk_100hz;
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/*
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* Use Original pixel clock
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*/
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uint32_t sink_pix_clk_100hz;
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/**
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* Use for AUX-less ALPM LFPS wake operation
|
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*/
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struct dmub_alpm_auxless_data auxless_alpm_data;
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/**
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* @hpo_stream_enc_inst: HPO stream encoder instance
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*/
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uint8_t hpo_stream_enc_inst;
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/**
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* @hpo_link_enc_inst: HPO link encoder instance
|
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*/
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uint8_t hpo_link_enc_inst;
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/**
|
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* @pad: Align structure to 4 byte boundary.
|
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*/
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uint8_t pad[2];
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};
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/**
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* Definition of a DMUB_CMD__PR_COPY_SETTINGS command.
|
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*/
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struct dmub_rb_cmd_pr_copy_settings {
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/**
|
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* Command header.
|
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*/
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struct dmub_cmd_header header;
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/**
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* Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command.
|
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*/
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struct dmub_cmd_pr_copy_settings_data data;
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};
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struct dmub_cmd_pr_update_state_data {
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/**
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* Panel Instance.
|
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* Panel isntance to identify which psr_state to use
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* Currently the support is only for 0 or 1
|
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*/
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uint8_t panel_inst;
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uint8_t pad[3]; // align to 4-byte boundary
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/*
|
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* Update flags to control the update behavior.
|
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*/
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uint32_t update_flag;
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/**
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* state/data to set.
|
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*/
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uint32_t coasting_vtotal;
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uint32_t sync_mode;
|
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};
|
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struct dmub_cmd_pr_general_cmd_data {
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/**
|
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* Panel Instance.
|
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* Panel isntance to identify which psr_state to use
|
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* Currently the support is only for 0 or 1
|
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*/
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uint8_t panel_inst;
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/**
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* subtype: PR general cmd sub type
|
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*/
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uint8_t subtype;
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uint8_t pad[2];
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/**
|
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* config data by different subtypes
|
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*/
|
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union {
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uint32_t u32All;
|
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} data;
|
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};
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/**
|
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* Definition of a DMUB_CMD__PR_UPDATE_STATE command.
|
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*/
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struct dmub_rb_cmd_pr_update_state {
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/**
|
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* Command header.
|
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*/
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struct dmub_cmd_header header;
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/**
|
||||
* Data passed from driver to FW in a DMUB_CMD__PR_UPDATE_STATE command.
|
||||
*/
|
||||
struct dmub_cmd_pr_update_state_data data;
|
||||
};
|
||||
|
||||
/**
|
||||
* Definition of a DMUB_CMD__PR_GENERAL_CMD command.
|
||||
*/
|
||||
struct dmub_rb_cmd_pr_general_cmd {
|
||||
/**
|
||||
* Command header.
|
||||
*/
|
||||
struct dmub_cmd_header header;
|
||||
/**
|
||||
* Data passed from driver to FW in a DMUB_CMD__PR_GENERAL_CMD command.
|
||||
*/
|
||||
struct dmub_cmd_pr_general_cmd_data data;
|
||||
};
|
||||
|
||||
/**
|
||||
* union dmub_rb_cmd - DMUB inbox command.
|
||||
*/
|
||||
|
|
@ -6698,13 +7061,25 @@ union dmub_rb_cmd {
|
|||
*/
|
||||
struct dmub_rb_cmd_cursor_offload_stream_cntl cursor_offload_stream_ctnl;
|
||||
/**
|
||||
* Definition of a DMUB_CMD__SMART_POWER_HDR_ENABLE command.
|
||||
* Definition of a DMUB_CMD__SMART_POWER_OLED_ENABLE command.
|
||||
*/
|
||||
struct dmub_rb_cmd_smart_power_hdr_enable smart_power_hdr_enable;
|
||||
struct dmub_rb_cmd_smart_power_oled_enable smart_power_oled_enable;
|
||||
/**
|
||||
* Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_HDR_GETMAXCLL command.
|
||||
* Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command.
|
||||
*/
|
||||
struct dmub_rb_cmd_smart_power_hdr_getmaxcll smart_power_hdr_getmaxcll;
|
||||
struct dmub_rb_cmd_smart_power_oled_getmaxcll smart_power_oled_getmaxcll;
|
||||
/*
|
||||
* Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
|
||||
*/
|
||||
struct dmub_rb_cmd_pr_copy_settings pr_copy_settings;
|
||||
/**
|
||||
* Definition of a DMUB_CMD__REPLAY_ENABLE command.
|
||||
*/
|
||||
struct dmub_rb_cmd_pr_enable pr_enable;
|
||||
|
||||
struct dmub_rb_cmd_pr_update_state pr_update_state;
|
||||
|
||||
struct dmub_rb_cmd_pr_general_cmd pr_general_cmd;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user