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Pin control fixes for v7.2:
Qualcomm fixes: some incorrectly defined groups in IPQ9650, two pins needing to be marked as GPIO in IPQ806X. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmp2K4kACgkQQRCzN7AZ XXNfeRAAtZL/qwyt03wCaPCnpUVmtkcAdoKSKteUbGOf73w9VlEal8gZTY6K/EiE gCiLGJqBoB7cZqDUlt7wnv2SeW08P7NCwZz7QGWG728cx2c8gUrWtxUHbNcDrhps UpWIDF1E3khGDGki726nq2Qo1bYAG57tEVZtRsUjMTb+XQQI9JQKpvS3QECxTXwD f/QLUbkT5rRuOqXq+PQzCoD3zSkZTCWgJIL+B2uC+/CuHK682FPC+qa19i4Xdeju RZBbj6oEvt5jL52qq/jtFlRViUrdxPBb6ju1+2H3g2AUVLZe9kbSvbzO0XzO9Qvq dfLHRLBm9CcSBIcYJJwC1dVhh2Ekn5o87cxEQzBajpEaErTAac/xmblkKRKkpX/u VQTxH3IWs7ypoEB9u8c/nt6VixnvALJY/1ldznSANUstnSYrIO+mGQVDPqbfL41o K/JxaNvIKYQHfOpGcWG69hVf0ZP+NSsftfKubapiK0NO4cYnqzFpazfAvqL06Jeg jRiE0K4QWe/vraYXW/iXOw8Zb+IQAN3Z3w5KKeJg7qtPiYEdoyYp94mI3HQF5hdm hh42y0CIK3J9uXdE+s+5iNq65HGNZDzKceQ45j+Aof6w1ZhokwB3iJ4z7iQzNNgs 7VtSnTDWaqF2PS34gwLv36dAoeQ8qT33bmzVPA4xOwnIOJl2wfo= =8MB1 -----END PGP SIGNATURE----- Merge tag 'pinctrl-v7.2-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: "Qualcomm fixes: some incorrectly defined groups in IPQ9650, two pins needing to be marked as GPIO in IPQ806X" * tag 'pinctrl-v7.2-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: qcom: ipq806x: mark pci reset as a GPIO pin function pinctrl: qcom: ipq806x: mark gpio as a GPIO pin function pinctrl: qcom: ipq9650: fix audio_sec_mclk_in1/out1 group pins
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3f00828032
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@ -480,7 +480,7 @@ static const char * const ps_hold_groups[] = {
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};
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static const struct pinfunction ipq8064_functions[] = {
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IPQ_PIN_FUNCTION(gpio),
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IPQ_GPIO_PIN_FUNCTION(gpio),
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IPQ_PIN_FUNCTION(mdio),
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IPQ_PIN_FUNCTION(ssbi),
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IPQ_PIN_FUNCTION(spmi),
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@ -507,19 +507,19 @@ static const struct pinfunction ipq8064_functions[] = {
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IPQ_PIN_FUNCTION(usb2_hsic),
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IPQ_PIN_FUNCTION(rgmii2),
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IPQ_PIN_FUNCTION(sata),
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IPQ_PIN_FUNCTION(pcie1_rst),
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IPQ_GPIO_PIN_FUNCTION(pcie1_rst),
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IPQ_PIN_FUNCTION(pcie1_prsnt),
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IPQ_PIN_FUNCTION(pcie1_pwren_n),
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IPQ_PIN_FUNCTION(pcie1_pwren),
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IPQ_PIN_FUNCTION(pcie1_pwrflt),
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IPQ_PIN_FUNCTION(pcie1_clk_req),
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IPQ_PIN_FUNCTION(pcie2_rst),
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IPQ_GPIO_PIN_FUNCTION(pcie2_rst),
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IPQ_PIN_FUNCTION(pcie2_prsnt),
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IPQ_PIN_FUNCTION(pcie2_pwren_n),
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IPQ_PIN_FUNCTION(pcie2_pwren),
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IPQ_PIN_FUNCTION(pcie2_pwrflt),
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IPQ_PIN_FUNCTION(pcie2_clk_req),
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IPQ_PIN_FUNCTION(pcie3_rst),
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IPQ_GPIO_PIN_FUNCTION(pcie3_rst),
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IPQ_PIN_FUNCTION(pcie3_prsnt),
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IPQ_PIN_FUNCTION(pcie3_pwren_n),
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IPQ_PIN_FUNCTION(pcie3_pwren),
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@ -310,11 +310,11 @@ static const char *const audio_sec_mclk_out0_groups[] = {
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};
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static const char *const audio_sec_mclk_in1_groups[] = {
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"gpio37",
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"gpio39",
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};
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static const char *const audio_sec_mclk_out1_groups[] = {
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"gpio37",
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"gpio39",
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};
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static const char *const audio_sec_groups[] = {
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@ -24,6 +24,11 @@ struct pinctrl_pin_desc;
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fname##_groups, \
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ARRAY_SIZE(fname##_groups))
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#define IPQ_GPIO_PIN_FUNCTION(fname) \
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[IPQ_MUX_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \
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fname##_groups, \
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ARRAY_SIZE(fname##_groups))
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#define MSM_PIN_FUNCTION(fname) \
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[msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \
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fname##_groups, \
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