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arm64: dts: socfpga: agilex5: Add L2 and L3 cache

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Add L2 and L3 cache nodes to the device tree to resolve the
"unable to detect cache hierarchy" warning reported by cacheinfo.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Adrian Ng Ho Yin 2025-10-15 10:12:42 +08:00 committed by Dinh Nguyen
parent 2f6da95cfb
commit 3e99d51aaa
1 changed files with 18 additions and 0 deletions
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18
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
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@ -37,6 +37,7 @@ cpu0: cpu@0 {
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2>;
};
cpu1: cpu@1 {
@ -44,6 +45,7 @@ cpu1: cpu@1 {
reg = <0x100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2>;
};
cpu2: cpu@2 {
@ -51,6 +53,7 @@ cpu2: cpu@2 {
reg = <0x200>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2>;
};
cpu3: cpu@3 {
@ -58,7 +61,22 @@ cpu3: cpu@3 {
reg = <0x300>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&L2>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3>;
cache-unified;
};
L3: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
psci {