mirror of
https://github.com/torvalds/linux.git
synced 2026-05-27 16:44:58 +02:00
Merge branch 'for-next/sysregs' into for-next/core
* for-next/sysregs:
arm64/sysreg: Add missing system instruction definitions for FGT
arm64/sysreg: Add missing system register definitions for FGT
arm64/sysreg: Add missing ExtTrcBuff field definition to ID_AA64DFR0_EL1
arm64/sysreg: Add missing Pauth_LR field definitions to ID_AA64ISAR1_EL1
arm64/sysreg: Add new system registers for GCS
arm64/sysreg: Add definition for FPMR
arm64/sysreg: Update HCRX_EL2 definition for DDI0601 2023-09
arm64/sysreg: Update SCTLR_EL1 for DDI0601 2023-09
arm64/sysreg: Update ID_AA64SMFR0_EL1 definition for DDI0601 2023-09
arm64/sysreg: Add definition for ID_AA64FPFR0_EL1
arm64/sysreg: Add definition for ID_AA64ISAR3_EL1
arm64/sysreg: Update ID_AA64ISAR2_EL1 defintion for DDI0601 2023-09
arm64/sysreg: Add definition for ID_AA64PFR2_EL1
arm64/sysreg: update CPACR_EL1 register
arm64/sysreg: add system register POR_EL{0,1}
arm64/sysreg: Add definition for HAFGRTR_EL2
arm64/sysreg: Update HFGITR_EL2 definiton to DDI0601 2023-09
This commit is contained in:
Will Deacon
commit
3e8626b4ed
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|
@ -645,6 +645,7 @@
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|||
#define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
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||||
#define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
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||||
#define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
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||||
#define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
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#define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
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||||
#define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
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#define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
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@ -781,10 +782,16 @@
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#define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
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/* Misc instructions */
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#define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
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#define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
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#define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
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#define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
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#define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
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#define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
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#define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
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#define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
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#define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
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#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
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/* Common SCTLR_ELx flags. */
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@ -1044,6 +1051,19 @@
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#define PIRx_ELx_PERM(idx, perm) ((perm) << ((idx) * 4))
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/*
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* Permission Overlay Extension (POE) permission encodings.
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*/
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#define POE_NONE UL(0x0)
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#define POE_R UL(0x1)
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#define POE_X UL(0x2)
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#define POE_RX UL(0x3)
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#define POE_W UL(0x4)
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#define POE_RW UL(0x5)
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#define POE_XW UL(0x6)
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#define POE_RXW UL(0x7)
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#define POE_MASK UL(0xf)
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#define ARM64_FEATURE_FIELD_BITS 4
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/* Defined for compatibility only, do not add new users. */
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@ -1002,6 +1002,27 @@ UnsignedEnum 3:0 BT
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EndEnum
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EndSysreg
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Sysreg ID_AA64PFR2_EL1 3 0 0 4 2
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Res0 63:36
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UnsignedEnum 35:32 FPMR
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0b0000 NI
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0b0001 IMP
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EndEnum
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Res0 31:12
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UnsignedEnum 11:8 MTEFAR
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0b0000 NI
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0b0001 IMP
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EndEnum
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UnsignedEnum 7:4 MTESTOREONLY
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0b0000 NI
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0b0001 IMP
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EndEnum
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UnsignedEnum 3:0 MTEPERM
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0b0000 NI
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0b0001 IMP
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EndEnum
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EndSysreg
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Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4
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Res0 63:60
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UnsignedEnum 59:56 F64MM
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@ -1058,7 +1079,11 @@ UnsignedEnum 63 FA64
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0b0 NI
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0b1 IMP
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EndEnum
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Res0 62:60
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Res0 62:61
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UnsignedEnum 60 LUTv2
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0b0 NI
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0b1 IMP
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EndEnum
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UnsignedEnum 59:56 SMEver
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0b0000 SME
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0b0001 SME2
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|
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@ -1086,7 +1111,14 @@ UnsignedEnum 42 F16F16
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0b0 NI
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0b1 IMP
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EndEnum
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Res0 41:40
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UnsignedEnum 41 F8F16
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0b0 NI
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0b1 IMP
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EndEnum
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||||
UnsignedEnum 40 F8F32
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0b0 NI
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0b1 IMP
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EndEnum
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UnsignedEnum 39:36 I8I32
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0b0000 NI
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0b1111 IMP
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|
|
@ -1107,7 +1139,49 @@ UnsignedEnum 32 F32F32
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0b0 NI
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0b1 IMP
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EndEnum
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Res0 31:0
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Res0 31
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UnsignedEnum 30 SF8FMA
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0b0 NI
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0b1 IMP
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EndEnum
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||||
UnsignedEnum 29 SF8DP4
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0b0 NI
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0b1 IMP
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EndEnum
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UnsignedEnum 28 SF8DP2
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0b0 NI
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0b1 IMP
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EndEnum
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Res0 27:0
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EndSysreg
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Sysreg ID_AA64FPFR0_EL1 3 0 0 4 7
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Res0 63:32
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UnsignedEnum 31 F8CVT
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0b0 NI
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0b1 IMP
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EndEnum
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UnsignedEnum 30 F8FMA
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0b0 NI
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0b1 IMP
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EndEnum
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UnsignedEnum 29 F8DP4
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0b0 NI
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0b1 IMP
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EndEnum
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UnsignedEnum 28 F8DP2
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0b0 NI
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0b1 IMP
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EndEnum
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Res0 27:2
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UnsignedEnum 1 F8E4M3
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0b0 NI
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0b1 IMP
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EndEnum
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UnsignedEnum 0 F8E5M2
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0b0 NI
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0b1 IMP
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EndEnum
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EndSysreg
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Sysreg ID_AA64DFR0_EL1 3 0 0 5 0
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@ -1115,7 +1189,10 @@ Enum 63:60 HPMN0
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0b0000 UNPREDICTABLE
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0b0001 DEF
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EndEnum
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Res0 59:56
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UnsignedEnum 59:56 ExtTrcBuff
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0b0000 NI
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0b0001 IMP
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EndEnum
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UnsignedEnum 55:52 BRBE
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0b0000 NI
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0b0001 IMP
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@ -1327,6 +1404,7 @@ UnsignedEnum 11:8 API
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0b0011 PAuth2
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0b0100 FPAC
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0b0101 FPACCOMBINE
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0b0110 PAuth_LR
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EndEnum
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UnsignedEnum 7:4 APA
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0b0000 NI
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@ -1335,6 +1413,7 @@ UnsignedEnum 7:4 APA
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0b0011 PAuth2
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0b0100 FPAC
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0b0101 FPACCOMBINE
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0b0110 PAuth_LR
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EndEnum
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UnsignedEnum 3:0 DPB
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0b0000 NI
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@ -1344,7 +1423,14 @@ EndEnum
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EndSysreg
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Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2
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Res0 63:56
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UnsignedEnum 63:60 ATS1A
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0b0000 NI
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0b0001 IMP
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EndEnum
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UnsignedEnum 59:56 LUT
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0b0000 NI
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0b0001 IMP
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EndEnum
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UnsignedEnum 55:52 CSSC
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0b0000 NI
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0b0001 IMP
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|
@ -1353,7 +1439,19 @@ UnsignedEnum 51:48 RPRFM
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0b0000 NI
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0b0001 IMP
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EndEnum
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Res0 47:32
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||||
Res0 47:44
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UnsignedEnum 43:40 PRFMSLC
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0b0000 NI
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0b0001 IMP
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EndEnum
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UnsignedEnum 39:36 SYSINSTR_128
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0b0000 NI
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||||
0b0001 IMP
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||||
EndEnum
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UnsignedEnum 35:32 SYSREG_128
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0b0000 NI
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0b0001 IMP
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EndEnum
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UnsignedEnum 31:28 CLRBHB
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0b0000 NI
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0b0001 IMP
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@ -1377,6 +1475,7 @@ UnsignedEnum 15:12 APA3
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0b0011 PAuth2
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0b0100 FPAC
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0b0101 FPACCOMBINE
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0b0110 PAuth_LR
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EndEnum
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UnsignedEnum 11:8 GPA3
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0b0000 NI
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@ -1392,6 +1491,23 @@ UnsignedEnum 3:0 WFxT
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EndEnum
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EndSysreg
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Sysreg ID_AA64ISAR3_EL1 3 0 0 6 3
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Res0 63:12
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UnsignedEnum 11:8 TLBIW
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0b0000 NI
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0b0001 IMP
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||||
EndEnum
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UnsignedEnum 7:4 FAMINMAX
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0b0000 NI
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0b0001 IMP
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||||
EndEnum
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UnsignedEnum 3:0 CPA
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||||
0b0000 NI
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0b0001 IMP
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0b0010 CPA2
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EndEnum
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EndSysreg
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Sysreg ID_AA64MMFR0_EL1 3 0 0 7 0
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UnsignedEnum 63:60 ECV
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0b0000 NI
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|
@ -1680,7 +1796,8 @@ Field 63 TIDCP
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Field 62 SPINTMASK
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Field 61 NMI
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Field 60 EnTP2
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Res0 59:58
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Field 59 TCSO
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Field 58 TCSO0
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Field 57 EPAN
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Field 56 EnALS
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Field 55 EnAS0
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@ -1709,7 +1826,7 @@ EndEnum
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Field 37 ITFSB
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Field 36 BT1
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Field 35 BT0
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Res0 34
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Field 34 EnFPM
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Field 33 MSCEn
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Field 32 CMOW
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Field 31 EnIA
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|
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@ -1747,7 +1864,8 @@ Field 0 M
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EndSysreg
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SysregFields CPACR_ELx
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Res0 63:29
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Res0 63:30
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Field 29 E0POE
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Field 28 TTA
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Res0 27:26
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Field 25:24 SMEN
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|
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@ -1790,6 +1908,41 @@ Sysreg SMCR_EL1 3 0 1 2 6
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Fields SMCR_ELx
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EndSysreg
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||||
SysregFields GCSCR_ELx
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Res0 63:10
|
||||
Field 9 STREn
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||||
Field 8 PUSHMEn
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||||
Res0 7
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Field 6 EXLOCKEN
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Field 5 RVCHKEN
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Res0 4:1
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Field 0 PCRSEL
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EndSysregFields
|
||||
|
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Sysreg GCSCR_EL1 3 0 2 5 0
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Fields GCSCR_ELx
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EndSysreg
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SysregFields GCSPR_ELx
|
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Field 63:3 PTR
|
||||
Res0 2:0
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||||
EndSysregFields
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Sysreg GCSPR_EL1 3 0 2 5 1
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||||
Fields GCSPR_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg GCSCRE0_EL1 3 0 2 5 2
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||||
Res0 63:11
|
||||
Field 10 nTR
|
||||
Field 9 STREn
|
||||
Field 8 PUSHMEn
|
||||
Res0 7:6
|
||||
Field 5 RVCHKEN
|
||||
Res0 4:1
|
||||
Field 0 PCRSEL
|
||||
EndSysreg
|
||||
|
||||
Sysreg ALLINT 3 0 4 3 0
|
||||
Res0 63:14
|
||||
Field 13 ALLINT
|
||||
|
|
@ -1933,10 +2086,18 @@ Sysreg CONTEXTIDR_EL1 3 0 13 0 1
|
|||
Fields CONTEXTIDR_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg RCWSMASK_EL1 3 0 13 0 3
|
||||
Field 63:0 RCWSMASK
|
||||
EndSysreg
|
||||
|
||||
Sysreg TPIDR_EL1 3 0 13 0 4
|
||||
Field 63:0 ThreadID
|
||||
EndSysreg
|
||||
|
||||
Sysreg RCWMASK_EL1 3 0 13 0 6
|
||||
Field 63:0 RCWMASK
|
||||
EndSysreg
|
||||
|
||||
Sysreg SCXTNUM_EL1 3 0 13 0 7
|
||||
Field 63:0 SoftwareContextNumber
|
||||
EndSysreg
|
||||
|
|
@ -2021,12 +2182,39 @@ Field 4 DZP
|
|||
Field 3:0 BS
|
||||
EndSysreg
|
||||
|
||||
Sysreg GCSPR_EL0 3 3 2 5 1
|
||||
Fields GCSPR_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg SVCR 3 3 4 2 2
|
||||
Res0 63:2
|
||||
Field 1 ZA
|
||||
Field 0 SM
|
||||
EndSysreg
|
||||
|
||||
Sysreg FPMR 3 3 4 4 2
|
||||
Res0 63:38
|
||||
Field 37:32 LSCALE2
|
||||
Field 31:24 NSCALE
|
||||
Res0 23
|
||||
Field 22:16 LSCALE
|
||||
Field 15 OSC
|
||||
Field 14 OSM
|
||||
Res0 13:9
|
||||
UnsignedEnum 8:6 F8D
|
||||
0b000 E5M2
|
||||
0b001 E4M3
|
||||
EndEnum
|
||||
UnsignedEnum 5:3 F8S2
|
||||
0b000 E5M2
|
||||
0b001 E4M3
|
||||
EndEnum
|
||||
UnsignedEnum 2:0 F8S1
|
||||
0b000 E5M2
|
||||
0b001 E4M3
|
||||
EndEnum
|
||||
EndSysreg
|
||||
|
||||
SysregFields HFGxTR_EL2
|
||||
Field 63 nAMAIR2_EL1
|
||||
Field 62 nMAIR2_EL1
|
||||
|
|
@ -2103,7 +2291,9 @@ Fields HFGxTR_EL2
|
|||
EndSysreg
|
||||
|
||||
Sysreg HFGITR_EL2 3 4 1 1 6
|
||||
Res0 63:61
|
||||
Res0 63
|
||||
Field 62 ATS1E1A
|
||||
Res0 61
|
||||
Field 60 COSPRCTX
|
||||
Field 59 nGCSEPP
|
||||
Field 58 nGCSSTR_EL1
|
||||
|
|
@ -2296,12 +2486,57 @@ Field 1 DBGBVRn_EL1
|
|||
Field 0 DBGBCRn_EL1
|
||||
EndSysreg
|
||||
|
||||
Sysreg HAFGRTR_EL2 3 4 3 1 6
|
||||
Res0 63:50
|
||||
Field 49 AMEVTYPER115_EL0
|
||||
Field 48 AMEVCNTR115_EL0
|
||||
Field 47 AMEVTYPER114_EL0
|
||||
Field 46 AMEVCNTR114_EL0
|
||||
Field 45 AMEVTYPER113_EL0
|
||||
Field 44 AMEVCNTR113_EL0
|
||||
Field 43 AMEVTYPER112_EL0
|
||||
Field 42 AMEVCNTR112_EL0
|
||||
Field 41 AMEVTYPER111_EL0
|
||||
Field 40 AMEVCNTR111_EL0
|
||||
Field 39 AMEVTYPER110_EL0
|
||||
Field 38 AMEVCNTR110_EL0
|
||||
Field 37 AMEVTYPER19_EL0
|
||||
Field 36 AMEVCNTR19_EL0
|
||||
Field 35 AMEVTYPER18_EL0
|
||||
Field 34 AMEVCNTR18_EL0
|
||||
Field 33 AMEVTYPER17_EL0
|
||||
Field 32 AMEVCNTR17_EL0
|
||||
Field 31 AMEVTYPER16_EL0
|
||||
Field 30 AMEVCNTR16_EL0
|
||||
Field 29 AMEVTYPER15_EL0
|
||||
Field 28 AMEVCNTR15_EL0
|
||||
Field 27 AMEVTYPER14_EL0
|
||||
Field 26 AMEVCNTR14_EL0
|
||||
Field 25 AMEVTYPER13_EL0
|
||||
Field 24 AMEVCNTR13_EL0
|
||||
Field 23 AMEVTYPER12_EL0
|
||||
Field 22 AMEVCNTR12_EL0
|
||||
Field 21 AMEVTYPER11_EL0
|
||||
Field 20 AMEVCNTR11_EL0
|
||||
Field 19 AMEVTYPER10_EL0
|
||||
Field 18 AMEVCNTR10_EL0
|
||||
Field 17 AMCNTEN1
|
||||
Res0 16:5
|
||||
Field 4 AMEVCNTR03_EL0
|
||||
Field 3 AMEVCNTR02_EL0
|
||||
Field 2 AMEVCNTR01_EL0
|
||||
Field 1 AMEVCNTR00_EL0
|
||||
Field 0 AMCNTEN0
|
||||
EndSysreg
|
||||
|
||||
Sysreg ZCR_EL2 3 4 1 2 0
|
||||
Fields ZCR_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg HCRX_EL2 3 4 1 2 2
|
||||
Res0 63:23
|
||||
Res0 63:25
|
||||
Field 24 PACMEn
|
||||
Field 23 EnFPM
|
||||
Field 22 GCSEn
|
||||
Field 21 EnIDCP128
|
||||
Field 20 EnSDERR
|
||||
|
|
@ -2349,6 +2584,14 @@ Sysreg SMCR_EL2 3 4 1 2 6
|
|||
Fields SMCR_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg GCSCR_EL2 3 4 2 5 0
|
||||
Fields GCSCR_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg GCSPR_EL2 3 4 2 5 1
|
||||
Fields GCSPR_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg DACR32_EL2 3 4 3 0 0
|
||||
Res0 63:32
|
||||
Field 31:30 D15
|
||||
|
|
@ -2408,6 +2651,14 @@ Sysreg SMCR_EL12 3 5 1 2 6
|
|||
Fields SMCR_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg GCSCR_EL12 3 5 2 5 0
|
||||
Fields GCSCR_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg GCSPR_EL12 3 5 2 5 1
|
||||
Fields GCSPR_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg FAR_EL12 3 5 6 0 0
|
||||
Field 63:0 ADDR
|
||||
EndSysreg
|
||||
|
|
@ -2472,6 +2723,33 @@ Field 1 PIE
|
|||
Field 0 PnCH
|
||||
EndSysreg
|
||||
|
||||
SysregFields MAIR2_ELx
|
||||
Field 63:56 Attr7
|
||||
Field 55:48 Attr6
|
||||
Field 47:40 Attr5
|
||||
Field 39:32 Attr4
|
||||
Field 31:24 Attr3
|
||||
Field 23:16 Attr2
|
||||
Field 15:8 Attr1
|
||||
Field 7:0 Attr0
|
||||
EndSysregFields
|
||||
|
||||
Sysreg MAIR2_EL1 3 0 10 2 1
|
||||
Fields MAIR2_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg MAIR2_EL2 3 4 10 1 1
|
||||
Fields MAIR2_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg AMAIR2_EL1 3 0 10 3 1
|
||||
Field 63:0 ImpDef
|
||||
EndSysreg
|
||||
|
||||
Sysreg AMAIR2_EL2 3 4 10 3 1
|
||||
Field 63:0 ImpDef
|
||||
EndSysreg
|
||||
|
||||
SysregFields PIRx_ELx
|
||||
Field 63:60 Perm15
|
||||
Field 59:56 Perm14
|
||||
|
|
@ -2511,6 +2789,26 @@ Sysreg PIR_EL2 3 4 10 2 3
|
|||
Fields PIRx_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg POR_EL0 3 3 10 2 4
|
||||
Fields PIRx_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg POR_EL1 3 0 10 2 4
|
||||
Fields PIRx_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg POR_EL12 3 5 10 2 4
|
||||
Fields PIRx_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg S2POR_EL1 3 0 10 2 5
|
||||
Fields PIRx_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg S2PIR_EL2 3 4 10 2 5
|
||||
Fields PIRx_ELx
|
||||
EndSysreg
|
||||
|
||||
Sysreg LORSA_EL1 3 0 10 4 0
|
||||
Res0 63:52
|
||||
Field 51:16 SA
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user