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drm/i915/display: split out crtc state dump to a separate file
Declutter intel_display.c by splitting out crtc state dumping to a separate file. v2: intel_pipe_config_dump -> intel_crtc_state_dump Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f72a5626473692910263671af91e02251ed87eea.1655372759.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
parent
df17ff62b6
commit
3e29d3b318
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@ -210,6 +210,7 @@ i915-y += \
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display/intel_combo_phy.o \
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display/intel_connector.o \
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display/intel_crtc.o \
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display/intel_crtc_state_dump.o \
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display/intel_cursor.o \
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display/intel_display.o \
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display/intel_display_power.o \
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314
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
Normal file
314
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
Normal file
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@ -0,0 +1,314 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "intel_crtc_state_dump.h"
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#include "intel_display_types.h"
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#include "intel_hdmi.h"
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#include "intel_vrr.h"
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static void intel_dump_crtc_timings(struct drm_i915_private *i915,
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const struct drm_display_mode *mode)
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{
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drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
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"type: 0x%x flags: 0x%x\n",
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mode->crtc_clock,
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mode->crtc_hdisplay, mode->crtc_hsync_start,
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mode->crtc_hsync_end, mode->crtc_htotal,
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mode->crtc_vdisplay, mode->crtc_vsync_start,
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mode->crtc_vsync_end, mode->crtc_vtotal,
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mode->type, mode->flags);
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}
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static void
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intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
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const char *id, unsigned int lane_count,
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const struct intel_link_m_n *m_n)
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{
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struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
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drm_dbg_kms(&i915->drm,
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"%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
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id, lane_count,
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m_n->data_m, m_n->data_n,
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m_n->link_m, m_n->link_n, m_n->tu);
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}
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static void
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intel_dump_infoframe(struct drm_i915_private *dev_priv,
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const union hdmi_infoframe *frame)
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{
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if (!drm_debug_enabled(DRM_UT_KMS))
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return;
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hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
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}
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static void
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intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
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const struct drm_dp_vsc_sdp *vsc)
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{
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if (!drm_debug_enabled(DRM_UT_KMS))
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return;
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drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
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}
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#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
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static const char * const output_type_str[] = {
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OUTPUT_TYPE(UNUSED),
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OUTPUT_TYPE(ANALOG),
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OUTPUT_TYPE(DVO),
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OUTPUT_TYPE(SDVO),
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OUTPUT_TYPE(LVDS),
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OUTPUT_TYPE(TVOUT),
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OUTPUT_TYPE(HDMI),
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OUTPUT_TYPE(DP),
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OUTPUT_TYPE(EDP),
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OUTPUT_TYPE(DSI),
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OUTPUT_TYPE(DDI),
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OUTPUT_TYPE(DP_MST),
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};
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#undef OUTPUT_TYPE
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static void snprintf_output_types(char *buf, size_t len,
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unsigned int output_types)
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{
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char *str = buf;
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int i;
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str[0] = '\0';
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for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
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int r;
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if ((output_types & BIT(i)) == 0)
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continue;
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r = snprintf(str, len, "%s%s",
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str != buf ? "," : "", output_type_str[i]);
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if (r >= len)
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break;
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str += r;
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len -= r;
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output_types &= ~BIT(i);
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}
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WARN_ON_ONCE(output_types != 0);
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}
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static const char * const output_format_str[] = {
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[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
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[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
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[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
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};
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static const char *output_formats(enum intel_output_format format)
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{
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if (format >= ARRAY_SIZE(output_format_str))
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return "invalid";
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return output_format_str[format];
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}
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static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
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{
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struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
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struct drm_i915_private *i915 = to_i915(plane->base.dev);
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const struct drm_framebuffer *fb = plane_state->hw.fb;
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if (!fb) {
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drm_dbg_kms(&i915->drm,
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"[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
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plane->base.base.id, plane->base.name,
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str_yes_no(plane_state->uapi.visible));
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return;
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}
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drm_dbg_kms(&i915->drm,
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"[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
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plane->base.base.id, plane->base.name,
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fb->base.id, fb->width, fb->height, &fb->format->format,
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fb->modifier, str_yes_no(plane_state->uapi.visible));
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drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
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plane_state->hw.rotation, plane_state->scaler_id);
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if (plane_state->uapi.visible)
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drm_dbg_kms(&i915->drm,
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"\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
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DRM_RECT_FP_ARG(&plane_state->uapi.src),
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DRM_RECT_ARG(&plane_state->uapi.dst));
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}
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void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
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struct intel_atomic_state *state,
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const char *context)
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{
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struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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const struct intel_plane_state *plane_state;
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struct intel_plane *plane;
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char buf[64];
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int i;
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drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
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crtc->base.base.id, crtc->base.name,
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str_yes_no(pipe_config->hw.enable), context);
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if (!pipe_config->hw.enable)
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goto dump_planes;
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snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
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drm_dbg_kms(&dev_priv->drm,
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"active: %s, output_types: %s (0x%x), output format: %s\n",
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str_yes_no(pipe_config->hw.active),
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buf, pipe_config->output_types,
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output_formats(pipe_config->output_format));
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drm_dbg_kms(&dev_priv->drm,
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"cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
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transcoder_name(pipe_config->cpu_transcoder),
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pipe_config->pipe_bpp, pipe_config->dither);
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drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
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transcoder_name(pipe_config->mst_master_transcoder));
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drm_dbg_kms(&dev_priv->drm,
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"port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
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transcoder_name(pipe_config->master_transcoder),
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pipe_config->sync_mode_slaves_mask);
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drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n",
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intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" :
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intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no",
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pipe_config->bigjoiner_pipes);
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drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
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str_enabled_disabled(pipe_config->splitter.enable),
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pipe_config->splitter.link_count,
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pipe_config->splitter.pixel_overlap);
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if (pipe_config->has_pch_encoder)
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intel_dump_m_n_config(pipe_config, "fdi",
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pipe_config->fdi_lanes,
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&pipe_config->fdi_m_n);
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if (intel_crtc_has_dp_encoder(pipe_config)) {
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intel_dump_m_n_config(pipe_config, "dp m_n",
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pipe_config->lane_count,
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&pipe_config->dp_m_n);
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intel_dump_m_n_config(pipe_config, "dp m2_n2",
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pipe_config->lane_count,
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&pipe_config->dp_m2_n2);
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}
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drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n",
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pipe_config->framestart_delay, pipe_config->msa_timing_delay);
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drm_dbg_kms(&dev_priv->drm,
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"audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
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pipe_config->has_audio, pipe_config->has_infoframe,
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pipe_config->infoframes.enable);
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if (pipe_config->infoframes.enable &
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intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
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drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
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pipe_config->infoframes.gcp);
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if (pipe_config->infoframes.enable &
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intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
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intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
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if (pipe_config->infoframes.enable &
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intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
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intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
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if (pipe_config->infoframes.enable &
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intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
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intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
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if (pipe_config->infoframes.enable &
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intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
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intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
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if (pipe_config->infoframes.enable &
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intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
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intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
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if (pipe_config->infoframes.enable &
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intel_hdmi_infoframe_enable(DP_SDP_VSC))
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intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
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drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
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str_yes_no(pipe_config->vrr.enable),
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pipe_config->vrr.vmin, pipe_config->vrr.vmax,
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pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
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pipe_config->vrr.flipline,
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intel_vrr_vmin_vblank_start(pipe_config),
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intel_vrr_vmax_vblank_start(pipe_config));
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drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n",
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DRM_MODE_ARG(&pipe_config->hw.mode));
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drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n",
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DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
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intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
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drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n",
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DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
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intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
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drm_dbg_kms(&dev_priv->drm,
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"port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
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pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
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pipe_config->pixel_rate);
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drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
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pipe_config->linetime, pipe_config->ips_linetime);
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if (DISPLAY_VER(dev_priv) >= 9)
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drm_dbg_kms(&dev_priv->drm,
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"num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
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crtc->num_scalers,
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pipe_config->scaler_state.scaler_users,
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pipe_config->scaler_state.scaler_id);
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if (HAS_GMCH(dev_priv))
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drm_dbg_kms(&dev_priv->drm,
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"gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
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pipe_config->gmch_pfit.control,
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pipe_config->gmch_pfit.pgm_ratios,
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pipe_config->gmch_pfit.lvds_border_bits);
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else
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drm_dbg_kms(&dev_priv->drm,
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"pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
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DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
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str_enabled_disabled(pipe_config->pch_pfit.enabled),
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str_yes_no(pipe_config->pch_pfit.force_thru));
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drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n",
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pipe_config->ips_enabled, pipe_config->double_wide,
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pipe_config->has_drrs);
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intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
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if (IS_CHERRYVIEW(dev_priv))
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drm_dbg_kms(&dev_priv->drm,
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"cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
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pipe_config->cgm_mode, pipe_config->gamma_mode,
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pipe_config->gamma_enable, pipe_config->csc_enable);
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else
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drm_dbg_kms(&dev_priv->drm,
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"csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
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pipe_config->csc_mode, pipe_config->gamma_mode,
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pipe_config->gamma_enable, pipe_config->csc_enable);
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drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
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pipe_config->hw.degamma_lut ?
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drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
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pipe_config->hw.gamma_lut ?
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drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
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dump_planes:
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if (!state)
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return;
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for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
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if (plane->pipe == crtc->pipe)
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intel_dump_plane_state(plane_state);
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}
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}
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16
drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
Normal file
16
drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
Normal file
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@ -0,0 +1,16 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_CRTC_STATE_DUMP_H__
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#define __INTEL_CRTC_STATE_DUMP_H__
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struct intel_crtc_state;
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struct intel_atomic_state;
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void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,
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struct intel_atomic_state *state,
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const char *context);
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#endif /* __INTEL_CRTC_STATE_H__ */
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@ -87,6 +87,7 @@
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#include "intel_cdclk.h"
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#include "intel_color.h"
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#include "intel_crtc.h"
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#include "intel_crtc_state_dump.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_dmc.h"
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@ -5058,310 +5059,6 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
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return 0;
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}
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static void intel_dump_crtc_timings(struct drm_i915_private *i915,
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const struct drm_display_mode *mode)
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{
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drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
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"type: 0x%x flags: 0x%x\n",
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mode->crtc_clock,
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mode->crtc_hdisplay, mode->crtc_hsync_start,
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mode->crtc_hsync_end, mode->crtc_htotal,
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mode->crtc_vdisplay, mode->crtc_vsync_start,
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mode->crtc_vsync_end, mode->crtc_vtotal,
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mode->type, mode->flags);
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}
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static void
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intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
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const char *id, unsigned int lane_count,
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const struct intel_link_m_n *m_n)
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{
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struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
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drm_dbg_kms(&i915->drm,
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"%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
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id, lane_count,
|
||||
m_n->data_m, m_n->data_n,
|
||||
m_n->link_m, m_n->link_n, m_n->tu);
|
||||
}
|
||||
|
||||
static void
|
||||
intel_dump_infoframe(struct drm_i915_private *dev_priv,
|
||||
const union hdmi_infoframe *frame)
|
||||
{
|
||||
if (!drm_debug_enabled(DRM_UT_KMS))
|
||||
return;
|
||||
|
||||
hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
|
||||
}
|
||||
|
||||
static void
|
||||
intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
|
||||
const struct drm_dp_vsc_sdp *vsc)
|
||||
{
|
||||
if (!drm_debug_enabled(DRM_UT_KMS))
|
||||
return;
|
||||
|
||||
drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
|
||||
}
|
||||
|
||||
#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
|
||||
|
||||
static const char * const output_type_str[] = {
|
||||
OUTPUT_TYPE(UNUSED),
|
||||
OUTPUT_TYPE(ANALOG),
|
||||
OUTPUT_TYPE(DVO),
|
||||
OUTPUT_TYPE(SDVO),
|
||||
OUTPUT_TYPE(LVDS),
|
||||
OUTPUT_TYPE(TVOUT),
|
||||
OUTPUT_TYPE(HDMI),
|
||||
OUTPUT_TYPE(DP),
|
||||
OUTPUT_TYPE(EDP),
|
||||
OUTPUT_TYPE(DSI),
|
||||
OUTPUT_TYPE(DDI),
|
||||
OUTPUT_TYPE(DP_MST),
|
||||
};
|
||||
|
||||
#undef OUTPUT_TYPE
|
||||
|
||||
static void snprintf_output_types(char *buf, size_t len,
|
||||
unsigned int output_types)
|
||||
{
|
||||
char *str = buf;
|
||||
int i;
|
||||
|
||||
str[0] = '\0';
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
|
||||
int r;
|
||||
|
||||
if ((output_types & BIT(i)) == 0)
|
||||
continue;
|
||||
|
||||
r = snprintf(str, len, "%s%s",
|
||||
str != buf ? "," : "", output_type_str[i]);
|
||||
if (r >= len)
|
||||
break;
|
||||
str += r;
|
||||
len -= r;
|
||||
|
||||
output_types &= ~BIT(i);
|
||||
}
|
||||
|
||||
WARN_ON_ONCE(output_types != 0);
|
||||
}
|
||||
|
||||
static const char * const output_format_str[] = {
|
||||
[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
|
||||
[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
|
||||
[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
|
||||
};
|
||||
|
||||
static const char *output_formats(enum intel_output_format format)
|
||||
{
|
||||
if (format >= ARRAY_SIZE(output_format_str))
|
||||
return "invalid";
|
||||
return output_format_str[format];
|
||||
}
|
||||
|
||||
static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
|
||||
{
|
||||
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
|
||||
struct drm_i915_private *i915 = to_i915(plane->base.dev);
|
||||
const struct drm_framebuffer *fb = plane_state->hw.fb;
|
||||
|
||||
if (!fb) {
|
||||
drm_dbg_kms(&i915->drm,
|
||||
"[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
|
||||
plane->base.base.id, plane->base.name,
|
||||
str_yes_no(plane_state->uapi.visible));
|
||||
return;
|
||||
}
|
||||
|
||||
drm_dbg_kms(&i915->drm,
|
||||
"[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
|
||||
plane->base.base.id, plane->base.name,
|
||||
fb->base.id, fb->width, fb->height, &fb->format->format,
|
||||
fb->modifier, str_yes_no(plane_state->uapi.visible));
|
||||
drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
|
||||
plane_state->hw.rotation, plane_state->scaler_id);
|
||||
if (plane_state->uapi.visible)
|
||||
drm_dbg_kms(&i915->drm,
|
||||
"\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
|
||||
DRM_RECT_FP_ARG(&plane_state->uapi.src),
|
||||
DRM_RECT_ARG(&plane_state->uapi.dst));
|
||||
}
|
||||
|
||||
void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
|
||||
struct intel_atomic_state *state,
|
||||
const char *context)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
const struct intel_plane_state *plane_state;
|
||||
struct intel_plane *plane;
|
||||
char buf[64];
|
||||
int i;
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
|
||||
crtc->base.base.id, crtc->base.name,
|
||||
str_yes_no(pipe_config->hw.enable), context);
|
||||
|
||||
if (!pipe_config->hw.enable)
|
||||
goto dump_planes;
|
||||
|
||||
snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"active: %s, output_types: %s (0x%x), output format: %s\n",
|
||||
str_yes_no(pipe_config->hw.active),
|
||||
buf, pipe_config->output_types,
|
||||
output_formats(pipe_config->output_format));
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
|
||||
transcoder_name(pipe_config->cpu_transcoder),
|
||||
pipe_config->pipe_bpp, pipe_config->dither);
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
|
||||
transcoder_name(pipe_config->mst_master_transcoder));
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
|
||||
transcoder_name(pipe_config->master_transcoder),
|
||||
pipe_config->sync_mode_slaves_mask);
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n",
|
||||
intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" :
|
||||
intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no",
|
||||
pipe_config->bigjoiner_pipes);
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
|
||||
str_enabled_disabled(pipe_config->splitter.enable),
|
||||
pipe_config->splitter.link_count,
|
||||
pipe_config->splitter.pixel_overlap);
|
||||
|
||||
if (pipe_config->has_pch_encoder)
|
||||
intel_dump_m_n_config(pipe_config, "fdi",
|
||||
pipe_config->fdi_lanes,
|
||||
&pipe_config->fdi_m_n);
|
||||
|
||||
if (intel_crtc_has_dp_encoder(pipe_config)) {
|
||||
intel_dump_m_n_config(pipe_config, "dp m_n",
|
||||
pipe_config->lane_count,
|
||||
&pipe_config->dp_m_n);
|
||||
intel_dump_m_n_config(pipe_config, "dp m2_n2",
|
||||
pipe_config->lane_count,
|
||||
&pipe_config->dp_m2_n2);
|
||||
}
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n",
|
||||
pipe_config->framestart_delay, pipe_config->msa_timing_delay);
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
|
||||
pipe_config->has_audio, pipe_config->has_infoframe,
|
||||
pipe_config->infoframes.enable);
|
||||
|
||||
if (pipe_config->infoframes.enable &
|
||||
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
|
||||
drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
|
||||
pipe_config->infoframes.gcp);
|
||||
if (pipe_config->infoframes.enable &
|
||||
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
|
||||
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
|
||||
if (pipe_config->infoframes.enable &
|
||||
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
|
||||
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
|
||||
if (pipe_config->infoframes.enable &
|
||||
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
|
||||
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
|
||||
if (pipe_config->infoframes.enable &
|
||||
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
|
||||
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
|
||||
if (pipe_config->infoframes.enable &
|
||||
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
|
||||
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
|
||||
if (pipe_config->infoframes.enable &
|
||||
intel_hdmi_infoframe_enable(DP_SDP_VSC))
|
||||
intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
|
||||
str_yes_no(pipe_config->vrr.enable),
|
||||
pipe_config->vrr.vmin, pipe_config->vrr.vmax,
|
||||
pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
|
||||
pipe_config->vrr.flipline,
|
||||
intel_vrr_vmin_vblank_start(pipe_config),
|
||||
intel_vrr_vmax_vblank_start(pipe_config));
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n",
|
||||
DRM_MODE_ARG(&pipe_config->hw.mode));
|
||||
drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n",
|
||||
DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
|
||||
intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
|
||||
drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n",
|
||||
DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
|
||||
intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
|
||||
pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
|
||||
pipe_config->pixel_rate);
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
|
||||
pipe_config->linetime, pipe_config->ips_linetime);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 9)
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
|
||||
crtc->num_scalers,
|
||||
pipe_config->scaler_state.scaler_users,
|
||||
pipe_config->scaler_state.scaler_id);
|
||||
|
||||
if (HAS_GMCH(dev_priv))
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
|
||||
pipe_config->gmch_pfit.control,
|
||||
pipe_config->gmch_pfit.pgm_ratios,
|
||||
pipe_config->gmch_pfit.lvds_border_bits);
|
||||
else
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
|
||||
DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
|
||||
str_enabled_disabled(pipe_config->pch_pfit.enabled),
|
||||
str_yes_no(pipe_config->pch_pfit.force_thru));
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n",
|
||||
pipe_config->ips_enabled, pipe_config->double_wide,
|
||||
pipe_config->has_drrs);
|
||||
|
||||
intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
|
||||
|
||||
if (IS_CHERRYVIEW(dev_priv))
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
|
||||
pipe_config->cgm_mode, pipe_config->gamma_mode,
|
||||
pipe_config->gamma_enable, pipe_config->csc_enable);
|
||||
else
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
|
||||
pipe_config->csc_mode, pipe_config->gamma_mode,
|
||||
pipe_config->gamma_enable, pipe_config->csc_enable);
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
|
||||
pipe_config->hw.degamma_lut ?
|
||||
drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
|
||||
pipe_config->hw.gamma_lut ?
|
||||
drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
|
||||
|
||||
dump_planes:
|
||||
if (!state)
|
||||
return;
|
||||
|
||||
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
|
||||
if (plane->pipe == crtc->pipe)
|
||||
intel_dump_plane_state(plane_state);
|
||||
}
|
||||
}
|
||||
|
||||
static bool check_digital_port_conflicts(struct intel_atomic_state *state)
|
||||
{
|
||||
struct drm_device *dev = state->base.dev;
|
||||
|
|
@ -7392,9 +7089,9 @@ static int intel_atomic_check(struct drm_device *dev,
|
|||
!new_crtc_state->update_pipe)
|
||||
continue;
|
||||
|
||||
intel_dump_pipe_config(new_crtc_state, state,
|
||||
intel_crtc_needs_modeset(new_crtc_state) ?
|
||||
"[modeset]" : "[fastset]");
|
||||
intel_crtc_state_dump(new_crtc_state, state,
|
||||
intel_crtc_needs_modeset(new_crtc_state) ?
|
||||
"[modeset]" : "[fastset]");
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -7409,7 +7106,7 @@ static int intel_atomic_check(struct drm_device *dev,
|
|||
*/
|
||||
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
|
||||
new_crtc_state, i)
|
||||
intel_dump_pipe_config(new_crtc_state, state, "[failed]");
|
||||
intel_crtc_state_dump(new_crtc_state, state, "[failed]");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -9898,7 +9595,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
|
|||
to_intel_crtc_state(crtc->base.state);
|
||||
|
||||
intel_sanitize_crtc(crtc, ctx);
|
||||
intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
|
||||
intel_crtc_state_dump(crtc_state, NULL, "[setup_hw_state]");
|
||||
}
|
||||
|
||||
intel_modeset_update_connector_atomic_state(dev);
|
||||
|
|
|
|||
|
|
@ -563,9 +563,6 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
|
|||
bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
|
||||
const struct intel_crtc_state *pipe_config,
|
||||
bool fastset);
|
||||
void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
|
||||
struct intel_atomic_state *state,
|
||||
const char *context);
|
||||
|
||||
void intel_plane_destroy(struct drm_plane *plane);
|
||||
void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include "i915_drv.h"
|
||||
#include "intel_atomic.h"
|
||||
#include "intel_crtc.h"
|
||||
#include "intel_crtc_state_dump.h"
|
||||
#include "intel_display.h"
|
||||
#include "intel_display_types.h"
|
||||
#include "intel_fdi.h"
|
||||
|
|
@ -216,8 +217,8 @@ verify_crtc_state(struct intel_crtc *crtc,
|
|||
if (!intel_pipe_config_compare(new_crtc_state,
|
||||
pipe_config, false)) {
|
||||
I915_STATE_WARN(1, "pipe state doesn't match!\n");
|
||||
intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
|
||||
intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
|
||||
intel_crtc_state_dump(pipe_config, NULL, "[hw state]");
|
||||
intel_crtc_state_dump(new_crtc_state, NULL, "[sw state]");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user